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authorLinus Torvalds <torvalds@g5.osdl.org>2006-10-06 13:53:39 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-06 13:59:54 -0400
commit0cd61b68c340a4f901a06e8bb5e0dea4353161c0 (patch)
treecfd72be941ecd172627a06dd61d98b55cec63a39 /arch/arm/mach-versatile
parentda104a83692cf07434ab3b20bf10093bdbc3f97e (diff)
Initial blind fixup for arm for irq changes
Untested, but this should fix up the bulk of the totally mechanical issues, and should make the actual detail fixing easier. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/arm/mach-versatile')
-rw-r--r--arch/arm/mach-versatile/core.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index f2bbef07b1e4..2aa150b57ba1 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -77,12 +77,12 @@ static struct irq_chip sic_chip = {
77}; 77};
78 78
79static void 79static void
80sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) 80sic_handle_irq(unsigned int irq, struct irqdesc *desc)
81{ 81{
82 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS); 82 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
83 83
84 if (status == 0) { 84 if (status == 0) {
85 do_bad_IRQ(irq, desc, regs); 85 do_bad_IRQ(irq, desc);
86 return; 86 return;
87 } 87 }
88 88
@@ -93,7 +93,7 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
93 irq += IRQ_SIC_START; 93 irq += IRQ_SIC_START;
94 94
95 desc = irq_desc + irq; 95 desc = irq_desc + irq;
96 desc_handle_irq(irq, desc, regs); 96 desc_handle_irq(irq, desc);
97 } while (status); 97 } while (status);
98} 98}
99 99
@@ -851,14 +851,14 @@ static unsigned long versatile_gettimeoffset(void)
851/* 851/*
852 * IRQ handler for the timer 852 * IRQ handler for the timer
853 */ 853 */
854static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 854static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
855{ 855{
856 write_seqlock(&xtime_lock); 856 write_seqlock(&xtime_lock);
857 857
858 // ...clear the interrupt 858 // ...clear the interrupt
859 writel(1, TIMER0_VA_BASE + TIMER_INTCLR); 859 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
860 860
861 timer_tick(regs); 861 timer_tick();
862 862
863 write_sequnlock(&xtime_lock); 863 write_sequnlock(&xtime_lock);
864 864