diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-11-28 10:42:42 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-11-28 10:43:51 -0500 |
commit | ccaec3ec78d0f1840a67acce6aaeeab99f2d88bf (patch) | |
tree | b0cec3d9e1c386c6d0f16c625c6eea5443703bce /arch/arm/mach-versatile/include/mach/irqs.h | |
parent | 7ef4de17cc55a3c3b8d093743b1e3b845d8eba47 (diff) |
[ARM] versatile: remove IRQ mask definitions
These definitions are unused and serve no purpose with genirq.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-versatile/include/mach/irqs.h')
-rw-r--r-- | arch/arm/mach-versatile/include/mach/irqs.h | 86 |
1 files changed, 0 insertions, 86 deletions
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index 216a1312e62e..9bfdb30e1f3f 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h | |||
@@ -60,39 +60,6 @@ | |||
60 | #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) | 60 | #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) |
61 | #define IRQ_VIC_END (IRQ_VIC_START + 31) | 61 | #define IRQ_VIC_END (IRQ_VIC_START + 31) |
62 | 62 | ||
63 | #define IRQMASK_WDOGINT INTMASK_WDOGINT | ||
64 | #define IRQMASK_SOFTINT INTMASK_SOFTINT | ||
65 | #define IRQMASK_COMMRx INTMASK_COMMRx | ||
66 | #define IRQMASK_COMMTx INTMASK_COMMTx | ||
67 | #define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 | ||
68 | #define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 | ||
69 | #define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 | ||
70 | #define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 | ||
71 | #define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 | ||
72 | #define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 | ||
73 | #define IRQMASK_RTCINT INTMASK_RTCINT | ||
74 | #define IRQMASK_SSPINT INTMASK_SSPINT | ||
75 | #define IRQMASK_UARTINT0 INTMASK_UARTINT0 | ||
76 | #define IRQMASK_UARTINT1 INTMASK_UARTINT1 | ||
77 | #define IRQMASK_UARTINT2 INTMASK_UARTINT2 | ||
78 | #define IRQMASK_SCIINT INTMASK_SCIINT | ||
79 | #define IRQMASK_CLCDINT INTMASK_CLCDINT | ||
80 | #define IRQMASK_DMAINT INTMASK_DMAINT | ||
81 | #define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT | ||
82 | #define IRQMASK_MBXINT INTMASK_MBXINT | ||
83 | #define IRQMASK_GNDINT INTMASK_GNDINT | ||
84 | #define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21 | ||
85 | #define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22 | ||
86 | #define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23 | ||
87 | #define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24 | ||
88 | #define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25 | ||
89 | #define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26 | ||
90 | #define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27 | ||
91 | #define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28 | ||
92 | #define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29 | ||
93 | #define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30 | ||
94 | #define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31 | ||
95 | |||
96 | /* | 63 | /* |
97 | * FIQ interrupts definitions are the same as the INT definitions. | 64 | * FIQ interrupts definitions are the same as the INT definitions. |
98 | */ | 65 | */ |
@@ -130,39 +97,6 @@ | |||
130 | #define FIQ_VICSOURCE31 INT_VICSOURCE31 | 97 | #define FIQ_VICSOURCE31 INT_VICSOURCE31 |
131 | 98 | ||
132 | 99 | ||
133 | #define FIQMASK_WDOGINT INTMASK_WDOGINT | ||
134 | #define FIQMASK_SOFTINT INTMASK_SOFTINT | ||
135 | #define FIQMASK_COMMRx INTMASK_COMMRx | ||
136 | #define FIQMASK_COMMTx INTMASK_COMMTx | ||
137 | #define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 | ||
138 | #define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 | ||
139 | #define FIQMASK_GPIOINT0 INTMASK_GPIOINT0 | ||
140 | #define FIQMASK_GPIOINT1 INTMASK_GPIOINT1 | ||
141 | #define FIQMASK_GPIOINT2 INTMASK_GPIOINT2 | ||
142 | #define FIQMASK_GPIOINT3 INTMASK_GPIOINT3 | ||
143 | #define FIQMASK_RTCINT INTMASK_RTCINT | ||
144 | #define FIQMASK_SSPINT INTMASK_SSPINT | ||
145 | #define FIQMASK_UARTINT0 INTMASK_UARTINT0 | ||
146 | #define FIQMASK_UARTINT1 INTMASK_UARTINT1 | ||
147 | #define FIQMASK_UARTINT2 INTMASK_UARTINT2 | ||
148 | #define FIQMASK_SCIINT INTMASK_SCIINT | ||
149 | #define FIQMASK_CLCDINT INTMASK_CLCDINT | ||
150 | #define FIQMASK_DMAINT INTMASK_DMAINT | ||
151 | #define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT | ||
152 | #define FIQMASK_MBXINT INTMASK_MBXINT | ||
153 | #define FIQMASK_GNDINT INTMASK_GNDINT | ||
154 | #define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21 | ||
155 | #define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22 | ||
156 | #define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23 | ||
157 | #define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24 | ||
158 | #define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25 | ||
159 | #define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26 | ||
160 | #define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27 | ||
161 | #define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28 | ||
162 | #define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29 | ||
163 | #define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30 | ||
164 | #define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31 | ||
165 | |||
166 | /* | 100 | /* |
167 | * Secondary interrupt controller | 101 | * Secondary interrupt controller |
168 | */ | 102 | */ |
@@ -188,24 +122,4 @@ | |||
188 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) | 122 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) |
189 | #define IRQ_SIC_END 63 | 123 | #define IRQ_SIC_END 63 |
190 | 124 | ||
191 | #define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B | ||
192 | #define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B | ||
193 | #define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0 | ||
194 | #define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1 | ||
195 | #define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3 | ||
196 | #define SIC_IRQMASK_UART3 SIC_INTMASK_UART3 | ||
197 | #define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD | ||
198 | #define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH | ||
199 | #define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD | ||
200 | #define SIC_IRQMASK_DoC SIC_INTMASK_DoC | ||
201 | #define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A | ||
202 | #define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A | ||
203 | #define SIC_IRQMASK_AACI SIC_INTMASK_AACI | ||
204 | #define SIC_IRQMASK_ETH SIC_INTMASK_ETH | ||
205 | #define SIC_IRQMASK_USB SIC_INTMASK_USB | ||
206 | #define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0 | ||
207 | #define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1 | ||
208 | #define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2 | ||
209 | #define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3 | ||
210 | |||
211 | #define NR_IRQS 64 | 125 | #define NR_IRQS 64 |