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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 19:42:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 19:42:32 -0400
commitb5153163ed580e00c67bdfecb02b2e3843817b3e (patch)
treeb8c878601f07f5df8f694435857a5f3dcfd75482 /arch/arm/mach-ux500
parenta8cbf22559ceefdcdfac00701e8e6da7518b7e8e (diff)
parent6451d7783ba5ff24eb1a544eaa6665b890f30466 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (278 commits) arm: remove machine_desc.io_pg_offst and .phys_io arm: use addruart macro to establish debug mappings arm: return both physical and virtual addresses from addruart arm/debug: consolidate addruart macros for CONFIG_DEBUG_ICEDCC ARM: make struct machine_desc definition coherent with its comment eukrea_mbimxsd-baseboard: Pass the correct GPIO to gpio_free cpuimx27: fix compile when ULPI is selected mach-pcm037_eet: fix compile errors Fixing ethernet driver compilation error for i.MX31 ADS board cpuimx51: update board support mx5: add cpuimx51sd module and its baseboard iomux-mx51: fix GPIO_1_xx 's IOMUX configuration imx-esdhc: update devices registration mx51: add resources for SD/MMC on i.MX51 iomux-mx51: fix SD1 and SD2's iomux configuration clock-mx51: rename CLOCK1 to CLOCK_CCGR for better readability clock-mx51: factorize clk_set_parent and clk_get_rate eukrea_mbimxsd: add support for DVI displays cpuimx25 & cpuimx35: fix OTG port registration in host mode i.MX31 and i.MX35 : fix errate TLSbo65953 and ENGcm09472 ...
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r--arch/arm/mach-ux500/Kconfig18
-rw-r--r--arch/arm/mach-ux500/Makefile8
-rw-r--r--arch/arm/mach-ux500/board-mop500-regulators.c101
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c91
-rw-r--r--arch/arm/mach-ux500/board-mop500.c36
-rw-r--r--arch/arm/mach-ux500/board-mop500.h12
-rw-r--r--arch/arm/mach-ux500/board-u5500.c2
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c88
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c82
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c94
-rw-r--r--arch/arm/mach-ux500/hotplug.c75
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h14
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h2
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h7
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h23
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h18
-rw-r--r--arch/arm/mach-ux500/include/mach/mbox.h88
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-regs.h91
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu.h15
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h7
-rw-r--r--arch/arm/mach-ux500/include/mach/smp.h9
-rw-r--r--arch/arm/mach-ux500/mbox.c567
-rw-r--r--arch/arm/mach-ux500/modem_irq.c139
-rw-r--r--arch/arm/mach-ux500/pins-db5500.h620
-rw-r--r--arch/arm/mach-ux500/pins-db8500.h66
-rw-r--r--arch/arm/mach-ux500/platsmp.c2
-rw-r--r--arch/arm/mach-ux500/prcmu.c231
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db5500.h135
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db8500.h258
31 files changed, 2700 insertions, 208 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 6625e5bbf4d6..2dd44a0b4615 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -21,9 +21,7 @@ config MACH_U8500_MOP
21 bool "U8500 Development platform" 21 bool "U8500 Development platform"
22 select UX500_SOC_DB8500 22 select UX500_SOC_DB8500
23 help 23 help
24 Include support for mop500 development platform 24 Include support for the mop500 development platform.
25 based on U8500 architecture. The platform is based
26 on early drop silicon version of 8500.
27 25
28config MACH_U5500 26config MACH_U5500
29 bool "U5500 Development platform" 27 bool "U5500 Development platform"
@@ -39,4 +37,18 @@ config UX500_DEBUG_UART
39 Choose the UART on which kernel low-level debug messages should be 37 Choose the UART on which kernel low-level debug messages should be
40 output. 38 output.
41 39
40config U5500_MODEM_IRQ
41 bool "Modem IRQ support"
42 depends on MACH_U5500
43 default y
44 help
45 Add support for handling IRQ:s from modem side
46
47config U5500_MBOX
48 bool "Mailbox support"
49 depends on MACH_U5500 && U5500_MODEM_IRQ
50 default y
51 help
52 Add support for U5500 mailbox communication with modem side
53
42endif 54endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 4556aea9c3c5..9e27a84433cb 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -4,8 +4,12 @@
4 4
5obj-y := clock.o cpu.o devices.o 5obj-y := clock.o cpu.o devices.o
6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o 6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o 8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o
9obj-$(CONFIG_MACH_U5500) += board-u5500.o 9obj-$(CONFIG_MACH_U5500) += board-u5500.o
10obj-$(CONFIG_SMP) += platsmp.o headsmp.o 10obj-$(CONFIG_SMP) += platsmp.o headsmp.o
11obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
11obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 12obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
13obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o
14obj-$(CONFIG_U5500_MODEM_IRQ) += modem_irq.o
15obj-$(CONFIG_U5500_MBOX) += mbox.o
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
new file mode 100644
index 000000000000..1187f1fc2e53
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 *
8 * MOP500 board specific initialization for regulators
9 */
10#include <linux/kernel.h>
11#include <linux/regulator/machine.h>
12
13/* supplies to the display/camera */
14static struct regulator_init_data ab8500_vaux1_regulator = {
15 .constraints = {
16 .name = "V-DISPLAY",
17 .min_uV = 2500000,
18 .max_uV = 2900000,
19 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
20 REGULATOR_CHANGE_STATUS,
21 },
22};
23
24/* supplies to the on-board eMMC */
25static struct regulator_init_data ab8500_vaux2_regulator = {
26 .constraints = {
27 .name = "V-eMMC1",
28 .min_uV = 1100000,
29 .max_uV = 3300000,
30 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
31 REGULATOR_CHANGE_STATUS,
32 },
33};
34
35/* supply for VAUX3, supplies to SDcard slots */
36static struct regulator_init_data ab8500_vaux3_regulator = {
37 .constraints = {
38 .name = "V-MMC-SD",
39 .min_uV = 1100000,
40 .max_uV = 3300000,
41 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
42 REGULATOR_CHANGE_STATUS,
43 },
44};
45
46/* supply for tvout, gpadc, TVOUT LDO */
47static struct regulator_init_data ab8500_vtvout_init = {
48 .constraints = {
49 .name = "V-TVOUT",
50 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
51 },
52};
53
54/* supply for ab8500-vaudio, VAUDIO LDO */
55static struct regulator_init_data ab8500_vaudio_init = {
56 .constraints = {
57 .name = "V-AUD",
58 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
59 },
60};
61
62/* supply for v-anamic1 VAMic1-LDO */
63static struct regulator_init_data ab8500_vamic1_init = {
64 .constraints = {
65 .name = "V-AMIC1",
66 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
67 },
68};
69
70/* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
71static struct regulator_init_data ab8500_vamic2_init = {
72 .constraints = {
73 .name = "V-AMIC2",
74 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
75 },
76};
77
78/* supply for v-dmic, VDMIC LDO */
79static struct regulator_init_data ab8500_vdmic_init = {
80 .constraints = {
81 .name = "V-DMIC",
82 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
83 },
84};
85
86/* supply for v-intcore12, VINTCORE12 LDO */
87static struct regulator_init_data ab8500_vintcore_init = {
88 .constraints = {
89 .name = "V-INTCORE",
90 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
91 },
92};
93
94/* supply for U8500 CSI/DSI, VANA LDO */
95static struct regulator_init_data ab8500_vana_init = {
96 .constraints = {
97 .name = "V-CSI/DSI",
98 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
99 },
100};
101
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
new file mode 100644
index 000000000000..bac995665b58
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -0,0 +1,91 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/gpio.h>
10#include <linux/amba/bus.h>
11#include <linux/amba/mmci.h>
12#include <linux/mmc/host.h>
13#include <linux/platform_device.h>
14
15#include <plat/pincfg.h>
16#include <mach/devices.h>
17#include <mach/hardware.h>
18
19#include "pins-db8500.h"
20#include "board-mop500.h"
21
22static pin_cfg_t mop500_sdi_pins[] = {
23 /* SDI4 (on-board eMMC) */
24 GPIO197_MC4_DAT3,
25 GPIO198_MC4_DAT2,
26 GPIO199_MC4_DAT1,
27 GPIO200_MC4_DAT0,
28 GPIO201_MC4_CMD,
29 GPIO202_MC4_FBCLK,
30 GPIO203_MC4_CLK,
31 GPIO204_MC4_DAT7,
32 GPIO205_MC4_DAT6,
33 GPIO206_MC4_DAT5,
34 GPIO207_MC4_DAT4,
35};
36
37static pin_cfg_t mop500_sdi2_pins[] = {
38 /* SDI2 (POP eMMC) */
39 GPIO128_MC2_CLK,
40 GPIO129_MC2_CMD,
41 GPIO130_MC2_FBCLK,
42 GPIO131_MC2_DAT0,
43 GPIO132_MC2_DAT1,
44 GPIO133_MC2_DAT2,
45 GPIO134_MC2_DAT3,
46 GPIO135_MC2_DAT4,
47 GPIO136_MC2_DAT5,
48 GPIO137_MC2_DAT6,
49 GPIO138_MC2_DAT7,
50};
51
52/*
53 * SDI 2 (POP eMMC, not on DB8500ed)
54 */
55
56static struct mmci_platform_data mop500_sdi2_data = {
57 .ocr_mask = MMC_VDD_165_195,
58 .f_max = 100000000,
59 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
60 .gpio_cd = -1,
61 .gpio_wp = -1,
62};
63
64/*
65 * SDI 4 (on-board eMMC)
66 */
67
68static struct mmci_platform_data mop500_sdi4_data = {
69 .ocr_mask = MMC_VDD_29_30,
70 .f_max = 100000000,
71 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
72 MMC_CAP_MMC_HIGHSPEED,
73 .gpio_cd = -1,
74 .gpio_wp = -1,
75};
76
77void mop500_sdi_init(void)
78{
79 nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
80
81 u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data;
82 u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data;
83
84 if (!cpu_is_u8500ed()) {
85 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
86 amba_device_register(&u8500_sdi2_device, &iomem_resource);
87 }
88
89 /* On-board eMMC */
90 amba_device_register(&u8500_sdi4_device, &iomem_resource);
91}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 219ae0ca4eef..fcb587f825cc 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -28,8 +28,10 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/setup.h> 29#include <mach/setup.h>
30#include <mach/devices.h> 30#include <mach/devices.h>
31#include <mach/irqs.h>
31 32
32#include "pins-db8500.h" 33#include "pins-db8500.h"
34#include "board-mop500.h"
33 35
34static pin_cfg_t mop500_pins[] = { 36static pin_cfg_t mop500_pins[] = {
35 /* SSP0 */ 37 /* SSP0 */
@@ -69,9 +71,27 @@ static struct ab8500_platform_data ab8500_platdata = {
69 .irq_base = MOP500_AB8500_IRQ_BASE, 71 .irq_base = MOP500_AB8500_IRQ_BASE,
70}; 72};
71 73
72static struct spi_board_info u8500_spi_devices[] = { 74static struct resource ab8500_resources[] = {
75 [0] = {
76 .start = IRQ_AB8500,
77 .end = IRQ_AB8500,
78 .flags = IORESOURCE_IRQ
79 }
80};
81
82struct platform_device ab8500_device = {
83 .name = "ab8500-i2c",
84 .id = 0,
85 .dev = {
86 .platform_data = &ab8500_platdata,
87 },
88 .num_resources = 1,
89 .resource = ab8500_resources,
90};
91
92static struct spi_board_info ab8500_spi_devices[] = {
73 { 93 {
74 .modalias = "ab8500", 94 .modalias = "ab8500-spi",
75 .controller_data = &ab4500_chip_info, 95 .controller_data = &ab4500_chip_info,
76 .platform_data = &ab8500_platdata, 96 .platform_data = &ab8500_platdata,
77 .max_speed_hz = 12000000, 97 .max_speed_hz = 12000000,
@@ -157,14 +177,18 @@ static void __init u8500_init_machine(void)
157 177
158 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 178 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
159 179
160 spi_register_board_info(u8500_spi_devices, 180 mop500_sdi_init();
161 ARRAY_SIZE(u8500_spi_devices)); 181
182 /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */
183 if (cpu_is_u8500ed() || cpu_is_u8500v10())
184 spi_register_board_info(ab8500_spi_devices,
185 ARRAY_SIZE(ab8500_spi_devices));
186 else /* If HW is v.1.1 or later use I2C to access AB8500 */
187 platform_device_register(&ab8500_device);
162} 188}
163 189
164MACHINE_START(U8500, "ST-Ericsson MOP500 platform") 190MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
165 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ 191 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
166 .phys_io = U8500_UART2_BASE,
167 .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
168 .boot_params = 0x100, 192 .boot_params = 0x100,
169 .map_io = u8500_map_io, 193 .map_io = u8500_map_io,
170 .init_irq = ux500_init_irq, 194 .init_irq = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
new file mode 100644
index 000000000000..2d240322fa6f
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -0,0 +1,12 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __BOARD_MOP500_H
8#define __BOARD_MOP500_H
9
10extern void mop500_sdi_init(void);
11
12#endif
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 4430e69cf538..1ca094a45e71 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -31,8 +31,6 @@ static void __init u5500_init_machine(void)
31} 31}
32 32
33MACHINE_START(U8500, "ST-Ericsson U5500 Platform") 33MACHINE_START(U8500, "ST-Ericsson U5500 Platform")
34 .phys_io = UX500_UART0_BASE,
35 .io_pg_offst = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc,
36 .boot_params = 0x00000100, 34 .boot_params = 0x00000100,
37 .map_io = u5500_map_io, 35 .map_io = u5500_map_io,
38 .init_irq = ux500_init_irq, 36 .init_irq = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index e9278f6d67aa..2f87075e9d6f 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -14,6 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/devices.h> 15#include <mach/devices.h>
16#include <mach/setup.h> 16#include <mach/setup.h>
17#include <mach/irqs.h>
17 18
18static struct map_desc u5500_io_desc[] __initdata = { 19static struct map_desc u5500_io_desc[] __initdata = {
19 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), 20 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
@@ -24,6 +25,90 @@ static struct map_desc u5500_io_desc[] __initdata = {
24 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), 25 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
25}; 26};
26 27
28static struct resource mbox0_resources[] = {
29 {
30 .name = "mbox_peer",
31 .start = U5500_MBOX0_PEER_START,
32 .end = U5500_MBOX0_PEER_END,
33 .flags = IORESOURCE_MEM,
34 },
35 {
36 .name = "mbox_local",
37 .start = U5500_MBOX0_LOCAL_START,
38 .end = U5500_MBOX0_LOCAL_END,
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "mbox_irq",
43 .start = MBOX_PAIR0_VIRT_IRQ,
44 .end = MBOX_PAIR0_VIRT_IRQ,
45 .flags = IORESOURCE_IRQ,
46 }
47};
48
49static struct resource mbox1_resources[] = {
50 {
51 .name = "mbox_peer",
52 .start = U5500_MBOX1_PEER_START,
53 .end = U5500_MBOX1_PEER_END,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .name = "mbox_local",
58 .start = U5500_MBOX1_LOCAL_START,
59 .end = U5500_MBOX1_LOCAL_END,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .name = "mbox_irq",
64 .start = MBOX_PAIR1_VIRT_IRQ,
65 .end = MBOX_PAIR1_VIRT_IRQ,
66 .flags = IORESOURCE_IRQ,
67 }
68};
69
70static struct resource mbox2_resources[] = {
71 {
72 .name = "mbox_peer",
73 .start = U5500_MBOX2_PEER_START,
74 .end = U5500_MBOX2_PEER_END,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .name = "mbox_local",
79 .start = U5500_MBOX2_LOCAL_START,
80 .end = U5500_MBOX2_LOCAL_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .name = "mbox_irq",
85 .start = MBOX_PAIR2_VIRT_IRQ,
86 .end = MBOX_PAIR2_VIRT_IRQ,
87 .flags = IORESOURCE_IRQ,
88 }
89};
90
91static struct platform_device mbox0_device = {
92 .id = 0,
93 .name = "mbox",
94 .resource = mbox0_resources,
95 .num_resources = ARRAY_SIZE(mbox0_resources),
96};
97
98static struct platform_device mbox1_device = {
99 .id = 1,
100 .name = "mbox",
101 .resource = mbox1_resources,
102 .num_resources = ARRAY_SIZE(mbox1_resources),
103};
104
105static struct platform_device mbox2_device = {
106 .id = 2,
107 .name = "mbox",
108 .resource = mbox2_resources,
109 .num_resources = ARRAY_SIZE(mbox2_resources),
110};
111
27static struct platform_device *u5500_platform_devs[] __initdata = { 112static struct platform_device *u5500_platform_devs[] __initdata = {
28 &u5500_gpio_devs[0], 113 &u5500_gpio_devs[0],
29 &u5500_gpio_devs[1], 114 &u5500_gpio_devs[1],
@@ -33,6 +118,9 @@ static struct platform_device *u5500_platform_devs[] __initdata = {
33 &u5500_gpio_devs[5], 118 &u5500_gpio_devs[5],
34 &u5500_gpio_devs[6], 119 &u5500_gpio_devs[6],
35 &u5500_gpio_devs[7], 120 &u5500_gpio_devs[7],
121 &mbox0_device,
122 &mbox1_device,
123 &mbox2_device,
36}; 124};
37 125
38void __init u5500_map_io(void) 126void __init u5500_map_io(void)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f21c444edd99..4acab7544b3c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -38,10 +38,12 @@ static struct platform_device *platform_devs[] __initdata = {
38/* minimum static i/o mapping required to boot U8500 platforms */ 38/* minimum static i/o mapping required to boot U8500 platforms */
39static struct map_desc u8500_io_desc[] __initdata = { 39static struct map_desc u8500_io_desc[] __initdata = {
40 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 40 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 42 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
42 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 43 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
43 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 44 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
44 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 45 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
46 __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
45}; 47};
46 48
47static struct map_desc u8500ed_io_desc[] __initdata = { 49static struct map_desc u8500ed_io_desc[] __initdata = {
@@ -53,6 +55,69 @@ static struct map_desc u8500v1_io_desc[] __initdata = {
53 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
54}; 56};
55 57
58/*
59 * Functions to differentiate between later ASICs
60 * We look into the end of the ROM to locate the hardcoded ASIC ID.
61 * This is only needed to differentiate between minor revisions and
62 * process variants of an ASIC, the major revisions are encoded in
63 * the cpuid.
64 */
65#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4)
66#define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4)
67#define U8500_ASIC_REV_ED 0x01
68#define U8500_ASIC_REV_V10 0xA0
69#define U8500_ASIC_REV_V11 0xA1
70#define U8500_ASIC_REV_V20 0xB0
71
72/**
73 * struct db8500_asic_id - fields of the ASIC ID
74 * @process: the manufacturing process, 0x40 is 40 nm
75 * 0x00 is "standard"
76 * @partnumber: hithereto 0x8500 for DB8500
77 * @revision: version code in the series
78 * This field definion is not formally defined but makes
79 * sense.
80 */
81struct db8500_asic_id {
82 u8 process;
83 u16 partnumber;
84 u8 revision;
85};
86
87/* This isn't going to change at runtime */
88static struct db8500_asic_id db8500_id;
89
90static void __init get_db8500_asic_id(void)
91{
92 u32 asicid;
93
94 if (cpu_is_u8500v1() || cpu_is_u8500ed())
95 asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1));
96 else if (cpu_is_u8500v2())
97 asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2));
98 else
99 BUG();
100
101 db8500_id.process = (asicid >> 24);
102 db8500_id.partnumber = (asicid >> 16) & 0xFFFFU;
103 db8500_id.revision = asicid & 0xFFU;
104}
105
106bool cpu_is_u8500v10(void)
107{
108 return (db8500_id.revision == U8500_ASIC_REV_V10);
109}
110
111bool cpu_is_u8500v11(void)
112{
113 return (db8500_id.revision == U8500_ASIC_REV_V11);
114}
115
116bool cpu_is_u8500v20(void)
117{
118 return (db8500_id.revision == U8500_ASIC_REV_V20);
119}
120
56void __init u8500_map_io(void) 121void __init u8500_map_io(void)
57{ 122{
58 ux500_map_io(); 123 ux500_map_io();
@@ -63,6 +128,9 @@ void __init u8500_map_io(void)
63 iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc)); 128 iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
64 else 129 else
65 iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc)); 130 iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
131
132 /* Read out the ASIC ID as early as we can */
133 get_db8500_asic_id();
66} 134}
67 135
68/* 136/*
@@ -70,6 +138,20 @@ void __init u8500_map_io(void)
70 */ 138 */
71void __init u8500_init_devices(void) 139void __init u8500_init_devices(void)
72{ 140{
141 /* Display some ASIC boilerplate */
142 pr_info("DB8500: process: %02x, revision ID: 0x%02x\n",
143 db8500_id.process, db8500_id.revision);
144 if (cpu_is_u8500ed())
145 pr_info("DB8500: Early Drop (ED)\n");
146 else if (cpu_is_u8500v10())
147 pr_info("DB8500: version 1.0\n");
148 else if (cpu_is_u8500v11())
149 pr_info("DB8500: version 1.1\n");
150 else if (cpu_is_u8500v20())
151 pr_info("DB8500: version 2.0\n");
152 else
153 pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
154
73 ux500_init_devices(); 155 ux500_init_devices();
74 156
75 if (cpu_is_u8500ed()) 157 if (cpu_is_u8500ed())
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 9280d2561111..40032fecbc16 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -110,6 +110,82 @@ struct platform_device u8500_i2c4_device = {
110 .num_resources = ARRAY_SIZE(u8500_i2c4_resources), 110 .num_resources = ARRAY_SIZE(u8500_i2c4_resources),
111}; 111};
112 112
113/*
114 * SD/MMC
115 */
116
117struct amba_device u8500_sdi0_device = {
118 .dev = {
119 .init_name = "sdi0",
120 },
121 .res = {
122 .start = U8500_SDI0_BASE,
123 .end = U8500_SDI0_BASE + SZ_4K - 1,
124 .flags = IORESOURCE_MEM,
125 },
126 .irq = {IRQ_DB8500_SDMMC0, NO_IRQ},
127};
128
129struct amba_device u8500_sdi1_device = {
130 .dev = {
131 .init_name = "sdi1",
132 },
133 .res = {
134 .start = U8500_SDI1_BASE,
135 .end = U8500_SDI1_BASE + SZ_4K - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 .irq = {IRQ_DB8500_SDMMC1, NO_IRQ},
139};
140
141struct amba_device u8500_sdi2_device = {
142 .dev = {
143 .init_name = "sdi2",
144 },
145 .res = {
146 .start = U8500_SDI2_BASE,
147 .end = U8500_SDI2_BASE + SZ_4K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 .irq = {IRQ_DB8500_SDMMC2, NO_IRQ},
151};
152
153struct amba_device u8500_sdi3_device = {
154 .dev = {
155 .init_name = "sdi3",
156 },
157 .res = {
158 .start = U8500_SDI3_BASE,
159 .end = U8500_SDI3_BASE + SZ_4K - 1,
160 .flags = IORESOURCE_MEM,
161 },
162 .irq = {IRQ_DB8500_SDMMC3, NO_IRQ},
163};
164
165struct amba_device u8500_sdi4_device = {
166 .dev = {
167 .init_name = "sdi4",
168 },
169 .res = {
170 .start = U8500_SDI4_BASE,
171 .end = U8500_SDI4_BASE + SZ_4K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 .irq = {IRQ_DB8500_SDMMC4, NO_IRQ},
175};
176
177struct amba_device u8500_sdi5_device = {
178 .dev = {
179 .init_name = "sdi5",
180 },
181 .res = {
182 .start = U8500_SDI5_BASE,
183 .end = U8500_SDI5_BASE + SZ_4K - 1,
184 .flags = IORESOURCE_MEM,
185 },
186 .irq = {IRQ_DB8500_SDMMC5, NO_IRQ},
187};
188
113static struct resource dma40_resources[] = { 189static struct resource dma40_resources[] = {
114 [0] = { 190 [0] = {
115 .start = U8500_DMA_BASE, 191 .start = U8500_DMA_BASE,
@@ -170,23 +246,23 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
170 * Mapping between destination event lines and physical device address. 246 * Mapping between destination event lines and physical device address.
171 * The event line is tied to a device and therefor the address is constant. 247 * The event line is tied to a device and therefor the address is constant.
172 */ 248 */
173static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV]; 249static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV];
174 250
175/* Mapping between source event lines and physical device address */ 251/* Mapping between source event lines and physical device address */
176static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV]; 252static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV];
177 253
178/* Reserved event lines for memcpy only */ 254/* Reserved event lines for memcpy only */
179static int dma40_memcpy_event[] = { 255static int dma40_memcpy_event[] = {
180 STEDMA40_MEMCPY_TX_0, 256 DB8500_DMA_MEMCPY_TX_0,
181 STEDMA40_MEMCPY_TX_1, 257 DB8500_DMA_MEMCPY_TX_1,
182 STEDMA40_MEMCPY_TX_2, 258 DB8500_DMA_MEMCPY_TX_2,
183 STEDMA40_MEMCPY_TX_3, 259 DB8500_DMA_MEMCPY_TX_3,
184 STEDMA40_MEMCPY_TX_4, 260 DB8500_DMA_MEMCPY_TX_4,
185 STEDMA40_MEMCPY_TX_5, 261 DB8500_DMA_MEMCPY_TX_5,
186}; 262};
187 263
188static struct stedma40_platform_data dma40_plat_data = { 264static struct stedma40_platform_data dma40_plat_data = {
189 .dev_len = STEDMA40_NR_DEV, 265 .dev_len = DB8500_DMA_NR_DEV,
190 .dev_rx = dma40_rx_map, 266 .dev_rx = dma40_rx_map,
191 .dev_tx = dma40_tx_map, 267 .dev_tx = dma40_tx_map,
192 .memcpy = dma40_memcpy_event, 268 .memcpy = dma40_memcpy_event,
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
new file mode 100644
index 000000000000..b782a03024be
--- /dev/null
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Based on ARM realview platform
7 *
8 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
9 *
10 */
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/smp.h>
14#include <linux/completion.h>
15
16#include <asm/cacheflush.h>
17
18extern volatile int pen_release;
19
20static DECLARE_COMPLETION(cpu_killed);
21
22static inline void platform_do_lowpower(unsigned int cpu)
23{
24 flush_cache_all();
25
26 /* we put the platform to just WFI */
27 for (;;) {
28 __asm__ __volatile__("dsb\n\t" "wfi\n\t"
29 : : : "memory");
30 if (pen_release == cpu) {
31 /*
32 * OK, proper wakeup, we're done
33 */
34 break;
35 }
36 }
37}
38
39int platform_cpu_kill(unsigned int cpu)
40{
41 return wait_for_completion_timeout(&cpu_killed, 5000);
42}
43
44/*
45 * platform-specific code to shutdown a CPU
46 *
47 * Called with IRQs disabled
48 */
49void platform_cpu_die(unsigned int cpu)
50{
51#ifdef DEBUG
52 unsigned int this_cpu = hard_smp_processor_id();
53
54 if (cpu != this_cpu) {
55 printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
56 this_cpu, cpu);
57 BUG();
58 }
59#endif
60
61 printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
62 complete(&cpu_killed);
63
64 /* directly enter low power state, skipping secure registers */
65 platform_do_lowpower(cpu);
66}
67
68int platform_cpu_disable(unsigned int cpu)
69{
70 /*
71 * we don't allow CPU 0 to be shutdown (it is still too special
72 * e.g. clock tick interrupts)
73 */
74 return cpu == 0 ? -EPERM : 0;
75}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 545c80fc8024..3eafc0e24ba5 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -100,4 +100,18 @@
100#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) 100#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
101#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) 101#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
102 102
103#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000)
104#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40)
105#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F)
106#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
107#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F)
108#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80)
109#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F)
110#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
111#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF)
112#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00)
113#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F)
114#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
115#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
116
103#endif 117#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index f000218210c9..f07d0986409d 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -30,8 +30,6 @@
30#define U8500_ICN_BASE 0x81000000 30#define U8500_ICN_BASE 0x81000000
31 31
32#define U8500_BOOT_ROM_BASE 0x90000000 32#define U8500_BOOT_ROM_BASE 0x90000000
33/* ASIC ID is at 0xff4 offset within this region */
34#define U8500_ASIC_ID_BASE 0x9001F000
35 33
36#define U8500_PER6_BASE 0xa03c0000 34#define U8500_PER6_BASE 0xa03c0000
37#define U8500_PER5_BASE 0xa03e0000 35#define U8500_PER5_BASE 0xa03e0000
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index c5203b7ea552..be7c0f14e310 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -18,11 +18,9 @@
18#define UX500_UART(n) __UX500_UART(n) 18#define UX500_UART(n) __UX500_UART(n)
19#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) 19#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART)
20 20
21 .macro addruart, rx, tmp 21 .macro addruart, rp, rv
22 mrc p15, 0, \rx, c1, c0 22 ldr \rp, =UART_BASE @ no, physical address
23 tst \rx, #1 @ MMU enabled? 23 ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address
24 ldreq \rx, =UART_BASE @ no, physical address
25 ldrne \rx, =IO_ADDRESS(UART_BASE) @ yes, virtual address
26 .endm 24 .endm
27 25
28#include <asm/hardware/debug-pl01x.S> 26#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index c2b2f2574947..33a120c2e82e 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -27,6 +27,13 @@ extern struct platform_device u8500_i2c0_device;
27extern struct platform_device u8500_i2c4_device; 27extern struct platform_device u8500_i2c4_device;
28extern struct platform_device u8500_dma40_device; 28extern struct platform_device u8500_dma40_device;
29 29
30extern struct amba_device u8500_sdi0_device;
31extern struct amba_device u8500_sdi1_device;
32extern struct amba_device u8500_sdi2_device;
33extern struct amba_device u8500_sdi3_device;
34extern struct amba_device u8500_sdi4_device;
35extern struct amba_device u8500_sdi5_device;
36
30void dma40_u8500ed_fixup(void); 37void dma40_u8500ed_fixup(void);
31 38
32#endif 39#endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 8656379a8309..32e883a8f2a2 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -104,16 +104,35 @@ static inline bool cpu_is_u8500(void)
104#endif 104#endif
105} 105}
106 106
107#define CPUID_DB8500ED 0x410fc090
108#define CPUID_DB8500V1 0x411fc091
109#define CPUID_DB8500V2 0x412fc091
110
107static inline bool cpu_is_u8500ed(void) 111static inline bool cpu_is_u8500ed(void)
108{ 112{
109 return cpu_is_u8500() && (read_cpuid_id() & 15) == 0; 113 return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED);
110} 114}
111 115
112static inline bool cpu_is_u8500v1(void) 116static inline bool cpu_is_u8500v1(void)
113{ 117{
114 return cpu_is_u8500() && (read_cpuid_id() & 15) == 1; 118 return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1);
119}
120
121static inline bool cpu_is_u8500v2(void)
122{
123 return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2);
115} 124}
116 125
126#ifdef CONFIG_UX500_SOC_DB8500
127bool cpu_is_u8500v10(void);
128bool cpu_is_u8500v11(void);
129bool cpu_is_u8500v20(void);
130#else
131static inline bool cpu_is_u8500v10(void) { return false; }
132static inline bool cpu_is_u8500v11(void) { return false; }
133static inline bool cpu_is_u8500v20(void) { return false; }
134#endif
135
117static inline bool cpu_is_u5500(void) 136static inline bool cpu_is_u5500(void)
118{ 137{
119#ifdef CONFIG_UX500_SOC_DB5500 138#ifdef CONFIG_UX500_SOC_DB5500
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index 6fbfe5e2065a..bfa123dbec3b 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -61,6 +61,7 @@
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) 61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) 62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) 63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
64#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) 65#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
65#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) 66#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
66#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) 67#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 10385bdc2b77..693aa57de88d 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -40,7 +40,8 @@
40#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) 40#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) 41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) 42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
43#define IRQ_AB4500 (IRQ_SHPI_START + 40) 43#define IRQ_AB8500 (IRQ_SHPI_START + 40)
44#define IRQ_PRCMU (IRQ_SHPI_START + 47)
44#define IRQ_DISP (IRQ_SHPI_START + 48) 45#define IRQ_DISP (IRQ_SHPI_START + 48)
45#define IRQ_SiPI3 (IRQ_SHPI_START + 49) 46#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
46#define IRQ_I2C4 (IRQ_SHPI_START + 51) 47#define IRQ_I2C4 (IRQ_SHPI_START + 51)
@@ -83,6 +84,19 @@
83#include <mach/irqs-board-mop500.h> 84#include <mach/irqs-board-mop500.h>
84#endif 85#endif
85 86
86#define NR_IRQS IRQ_BOARD_END 87/*
88 * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual
89 * IRQ:s representing modem IRQ:s can be allocated
90 */
91#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
92#define IRQ_MODEM_EVENTS_NBR 72
93#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
94
95/* List of virtual IRQ:s that are allocated from the range above */
96#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
97#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
98#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
99
100#define NR_IRQS IRQ_MODEM_EVENTS_END
87 101
88#endif /* ASM_ARCH_IRQS_H */ 102#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox.h
new file mode 100644
index 000000000000..7f9da4d2fbda
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mbox.h
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __INC_STE_MBOX_H
9#define __INC_STE_MBOX_H
10
11#define MBOX_BUF_SIZE 16
12#define MBOX_NAME_SIZE 8
13
14/**
15 * mbox_recv_cb_t - Definition of the mailbox callback.
16 * @mbox_msg: The mailbox message.
17 * @priv: The clients private data as specified in the call to mbox_setup.
18 *
19 * This function will be called upon reception of new mailbox messages.
20 */
21typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
22
23/**
24 * struct mbox - Mailbox instance struct
25 * @list: Linked list head.
26 * @pdev: Pointer to device struct.
27 * @cb: Callback function. Will be called
28 * when new data is received.
29 * @client_data: Clients private data. Will be sent back
30 * in the callback function.
31 * @virtbase_peer: Virtual address for outgoing mailbox.
32 * @virtbase_local: Virtual address for incoming mailbox.
33 * @buffer: Then internal queue for outgoing messages.
34 * @name: Name of this mailbox.
35 * @buffer_available: Completion variable to achieve "blocking send".
36 * This variable will be signaled when there is
37 * internal buffer space available.
38 * @client_blocked: To keep track if any client is currently
39 * blocked.
40 * @lock: Spinlock to protect this mailbox instance.
41 * @write_index: Index in internal buffer to write to.
42 * @read_index: Index in internal buffer to read from.
43 * @allocated: Indicates whether this particular mailbox
44 * id has been allocated by someone.
45 */
46struct mbox {
47 struct list_head list;
48 struct platform_device *pdev;
49 mbox_recv_cb_t *cb;
50 void *client_data;
51 void __iomem *virtbase_peer;
52 void __iomem *virtbase_local;
53 u32 buffer[MBOX_BUF_SIZE];
54 char name[MBOX_NAME_SIZE];
55 struct completion buffer_available;
56 u8 client_blocked;
57 spinlock_t lock;
58 u8 write_index;
59 u8 read_index;
60 bool allocated;
61};
62
63/**
64 * mbox_setup - Set up a mailbox and return its instance.
65 * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU,
66 * 2 for modem DSP.
67 * @mbox_cb: Pointer to the callback function to be called when a new message
68 * is received.
69 * @priv: Client user data which will be returned in the callback.
70 *
71 * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
72 */
73struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
74
75/**
76 * mbox_send - Send a mailbox message.
77 * @mbox: Mailbox instance (returned by mbox_setup)
78 * @mbox_msg: The mailbox message to send.
79 * @block: Specifies whether this call will block until send is possible,
80 * or return an error if the mailbox buffer is full.
81 *
82 * Returns 0 on success or a negative error code on error. -ENOMEM indicates
83 * that the internal buffer is full and you have to try again later (or
84 * specify "block" in order to block until send is possible).
85 */
86int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
87
88#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
new file mode 100644
index 000000000000..8885f39a6421
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright (c) 2009 ST-Ericsson SA
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foundation.
7 */
8#ifndef __MACH_PRCMU_REGS_H
9#define __MACH_PRCMU_REGS_H
10
11#include <mach/hardware.h>
12
13#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
14
15#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
16#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
17#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
18#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
19#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
20#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
21#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
22#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
23
24/* ARM WFI Standby signal register */
25#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
26#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
27
28/* CPU mailbox registers */
29#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
30#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
31#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
32
33/* Dual A9 core interrupt management unit registers */
34#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
35#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
36#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
37#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
38#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
39#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
40#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
41#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
42#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
43#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
44#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
45
46#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
47#define ARM_WAKEUP_MODEM 0x1
48
49#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
50#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
51#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
52
53#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
54#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
55#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
56#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
57#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
58#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
59#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
60#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
61
62/* System reset register */
63#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
64
65/* Level shifter and clamp control registers */
66#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
67#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
68
69/* PRCMU clock/PLL/reset registers */
70#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
71#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
72#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
73#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
74#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
75#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
76#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
77#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
78#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
79#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
80
81/* ePOD and memory power signal control registers */
82#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
83#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
84
85/* Debug power control unit registers */
86#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
87
88/* Miscellaneous unit registers */
89#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
90
91#endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
new file mode 100644
index 000000000000..549843ff6dbe
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 *
7 * PRCMU f/w APIs
8 */
9#ifndef __MACH_PRCMU_H
10#define __MACH_PRCMU_H
11
12int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
13int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
14
15#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index e978dbd9e210..54bbe648bf58 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -38,4 +38,11 @@ extern struct sys_timer ux500_timer;
38 .type = MT_DEVICE, \ 38 .type = MT_DEVICE, \
39} 39}
40 40
41#define __MEM_DEV_DESC(x, sz) { \
42 .virtual = IO_ADDRESS(x), \
43 .pfn = __phys_to_pfn(x), \
44 .length = sz, \
45 .type = MT_MEMORY, \
46}
47
41#endif /* __ASM_ARCH_SETUP_H */ 48#endif /* __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc9725d..197e8417375e 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
10#define ASMARM_ARCH_SMP_H 10#define ASMARM_ARCH_SMP_H
11 11
12#include <asm/hardware/gic.h> 12#include <asm/hardware/gic.h>
13#include <asm/smp_mpidr.h>
13 14
14/* This is required to wakeup the secondary core */ 15/* This is required to wakeup the secondary core */
15extern void u8500_secondary_startup(void); 16extern void u8500_secondary_startup(void);
16 17
17#define hard_smp_processor_id() \
18 ({ \
19 unsigned int cpunum; \
20 __asm__("mrc p15, 0, %0, c0, c0, 5" \
21 : "=r" (cpunum)); \
22 cpunum &= 0x0F; \
23 })
24
25/* 18/*
26 * We use IRQ1 as the IPI 19 * We use IRQ1 as the IPI
27 */ 20 */
diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox.c
new file mode 100644
index 000000000000..63435389c544
--- /dev/null
+++ b/arch/arm/mach-ux500/mbox.c
@@ -0,0 +1,567 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8/*
9 * Mailbox nomenclature:
10 *
11 * APE MODEM
12 * mbox pairX
13 * ..........................
14 * . .
15 * . peer .
16 * . send ---- .
17 * . --> | | .
18 * . | | .
19 * . ---- .
20 * . .
21 * . local .
22 * . rec ---- .
23 * . | | <-- .
24 * . | | .
25 * . ---- .
26 * .........................
27 */
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/platform_device.h>
38#include <linux/debugfs.h>
39#include <linux/seq_file.h>
40#include <linux/completion.h>
41#include <mach/mbox.h>
42
43#define MBOX_NAME "mbox"
44
45#define MBOX_FIFO_DATA 0x000
46#define MBOX_FIFO_ADD 0x004
47#define MBOX_FIFO_REMOVE 0x008
48#define MBOX_FIFO_THRES_FREE 0x00C
49#define MBOX_FIFO_THRES_OCCUP 0x010
50#define MBOX_FIFO_STATUS 0x014
51
52#define MBOX_DISABLE_IRQ 0x4
53#define MBOX_ENABLE_IRQ 0x0
54#define MBOX_LATCH 1
55
56/* Global list of all mailboxes */
57static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
58
59static struct mbox *get_mbox_with_id(u8 id)
60{
61 u8 i;
62 struct list_head *pos = &mboxs;
63 for (i = 0; i <= id; i++)
64 pos = pos->next;
65
66 return (struct mbox *) list_entry(pos, struct mbox, list);
67}
68
69int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
70{
71 int res = 0;
72
73 spin_lock(&mbox->lock);
74
75 dev_dbg(&(mbox->pdev->dev),
76 "About to buffer 0x%X to mailbox 0x%X."
77 " ri = %d, wi = %d\n",
78 mbox_msg, (u32)mbox, mbox->read_index,
79 mbox->write_index);
80
81 /* Check if write buffer is full */
82 while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
83 if (!block) {
84 dev_dbg(&(mbox->pdev->dev),
85 "Buffer full in non-blocking call! "
86 "Returning -ENOMEM!\n");
87 res = -ENOMEM;
88 goto exit;
89 }
90 spin_unlock(&mbox->lock);
91 dev_dbg(&(mbox->pdev->dev),
92 "Buffer full in blocking call! Sleeping...\n");
93 mbox->client_blocked = 1;
94 wait_for_completion(&mbox->buffer_available);
95 dev_dbg(&(mbox->pdev->dev),
96 "Blocking send was woken up! Trying again...\n");
97 spin_lock(&mbox->lock);
98 }
99
100 mbox->buffer[mbox->write_index] = mbox_msg;
101 mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
102
103 /*
104 * Indicate that we want an IRQ as soon as there is a slot
105 * in the FIFO
106 */
107 writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
108
109exit:
110 spin_unlock(&mbox->lock);
111 return res;
112}
113EXPORT_SYMBOL(mbox_send);
114
115#if defined(CONFIG_DEBUG_FS)
116/*
117 * Expected input: <value> <nbr sends>
118 * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
119 */
120static ssize_t mbox_write_fifo(struct device *dev,
121 struct device_attribute *attr,
122 const char *buf,
123 size_t count)
124{
125 unsigned long mbox_mess;
126 unsigned long nbr_sends;
127 unsigned long i;
128 char int_buf[16];
129 char *token;
130 char *val;
131
132 struct mbox *mbox = (struct mbox *) dev->platform_data;
133
134 strncpy((char *) &int_buf, buf, sizeof(int_buf));
135 token = (char *) &int_buf;
136
137 /* Parse message */
138 val = strsep(&token, " ");
139 if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
140 mbox_mess = 0xDEADBEEF;
141
142 val = strsep(&token, " ");
143 if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
144 nbr_sends = 1;
145
146 dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
147 mbox_mess, nbr_sends, (u32) mbox);
148
149 for (i = 0; i < nbr_sends; i++)
150 mbox_send(mbox, mbox_mess, true);
151
152 return count;
153}
154
155static ssize_t mbox_read_fifo(struct device *dev,
156 struct device_attribute *attr,
157 char *buf)
158{
159 int mbox_value;
160 struct mbox *mbox = (struct mbox *) dev->platform_data;
161
162 if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
163 return sprintf(buf, "Mailbox is empty\n");
164
165 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
166 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
167
168 return sprintf(buf, "0x%X\n", mbox_value);
169}
170
171static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
172
173static int mbox_show(struct seq_file *s, void *data)
174{
175 struct list_head *pos;
176 u8 mbox_index = 0;
177
178 list_for_each(pos, &mboxs) {
179 struct mbox *m =
180 (struct mbox *) list_entry(pos, struct mbox, list);
181 if (m == NULL) {
182 seq_printf(s,
183 "Unable to retrieve mailbox %d\n",
184 mbox_index);
185 continue;
186 }
187
188 spin_lock(&m->lock);
189 if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
190 seq_printf(s, "MAILBOX %d not setup or corrupt\n",
191 mbox_index);
192 spin_unlock(&m->lock);
193 continue;
194 }
195
196 seq_printf(s,
197 "===========================\n"
198 " MAILBOX %d\n"
199 " PEER MAILBOX DUMP\n"
200 "---------------------------\n"
201 "FIFO: 0x%X (%d)\n"
202 "Free Threshold: 0x%.2X (%d)\n"
203 "Occupied Threshold: 0x%.2X (%d)\n"
204 "Status: 0x%.2X (%d)\n"
205 " Free spaces (ot): %d (%d)\n"
206 " Occup spaces (ot): %d (%d)\n"
207 "===========================\n"
208 " LOCAL MAILBOX DUMP\n"
209 "---------------------------\n"
210 "FIFO: 0x%.X (%d)\n"
211 "Free Threshold: 0x%.2X (%d)\n"
212 "Occupied Threshold: 0x%.2X (%d)\n"
213 "Status: 0x%.2X (%d)\n"
214 " Free spaces (ot): %d (%d)\n"
215 " Occup spaces (ot): %d (%d)\n"
216 "===========================\n"
217 "write_index: %d\n"
218 "read_index : %d\n"
219 "===========================\n"
220 "\n",
221 mbox_index,
222 readl(m->virtbase_peer + MBOX_FIFO_DATA),
223 readl(m->virtbase_peer + MBOX_FIFO_DATA),
224 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
225 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
226 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
227 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
228 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
229 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
230 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
231 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
232 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
233 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
234 readl(m->virtbase_local + MBOX_FIFO_DATA),
235 readl(m->virtbase_local + MBOX_FIFO_DATA),
236 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
237 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
238 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
239 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
240 readl(m->virtbase_local + MBOX_FIFO_STATUS),
241 readl(m->virtbase_local + MBOX_FIFO_STATUS),
242 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
243 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
244 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
245 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
246 m->write_index, m->read_index);
247 mbox_index++;
248 spin_unlock(&m->lock);
249 }
250
251 return 0;
252}
253
254static int mbox_open(struct inode *inode, struct file *file)
255{
256 return single_open(file, mbox_show, NULL);
257}
258
259static const struct file_operations mbox_operations = {
260 .owner = THIS_MODULE,
261 .open = mbox_open,
262 .read = seq_read,
263 .llseek = seq_lseek,
264 .release = single_release,
265};
266#endif
267
268static irqreturn_t mbox_irq(int irq, void *arg)
269{
270 u32 mbox_value;
271 int nbr_occup;
272 int nbr_free;
273 struct mbox *mbox = (struct mbox *) arg;
274
275 spin_lock(&mbox->lock);
276
277 dev_dbg(&(mbox->pdev->dev),
278 "mbox IRQ [%d] received. ri = %d, wi = %d\n",
279 irq, mbox->read_index, mbox->write_index);
280
281 /*
282 * Check if we have any outgoing messages, and if there is space for
283 * them in the FIFO.
284 */
285 if (mbox->read_index != mbox->write_index) {
286 /*
287 * Check by reading FREE for LOCAL since that indicates
288 * OCCUP for PEER
289 */
290 nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
291 >> 4) & 0x7;
292 dev_dbg(&(mbox->pdev->dev),
293 "Status indicates %d empty spaces in the FIFO!\n",
294 nbr_free);
295
296 while ((nbr_free > 0) &&
297 (mbox->read_index != mbox->write_index)) {
298 /* Write the message and latch it into the FIFO */
299 writel(mbox->buffer[mbox->read_index],
300 (mbox->virtbase_peer + MBOX_FIFO_DATA));
301 writel(MBOX_LATCH,
302 (mbox->virtbase_peer + MBOX_FIFO_ADD));
303 dev_dbg(&(mbox->pdev->dev),
304 "Wrote message 0x%X to addr 0x%X\n",
305 mbox->buffer[mbox->read_index],
306 (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
307
308 nbr_free--;
309 mbox->read_index =
310 (mbox->read_index + 1) % MBOX_BUF_SIZE;
311 }
312
313 /*
314 * Check if we still want IRQ:s when there is free
315 * space to send
316 */
317 if (mbox->read_index != mbox->write_index) {
318 dev_dbg(&(mbox->pdev->dev),
319 "Still have messages to send, but FIFO full. "
320 "Request IRQ again!\n");
321 writel(MBOX_ENABLE_IRQ,
322 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
323 } else {
324 dev_dbg(&(mbox->pdev->dev),
325 "No more messages to send. "
326 "Do not request IRQ again!\n");
327 writel(MBOX_DISABLE_IRQ,
328 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
329 }
330
331 /*
332 * Check if we can signal any blocked clients that it is OK to
333 * start buffering again
334 */
335 if (mbox->client_blocked &&
336 (((mbox->write_index + 1) % MBOX_BUF_SIZE)
337 != mbox->read_index)) {
338 dev_dbg(&(mbox->pdev->dev),
339 "Waking up blocked client\n");
340 complete(&mbox->buffer_available);
341 mbox->client_blocked = 0;
342 }
343 }
344
345 /* Check if we have any incoming messages */
346 nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
347 if (nbr_occup == 0)
348 goto exit;
349
350 if (mbox->cb == NULL) {
351 dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
352 "leaving %d incoming messages in fifo!\n", nbr_occup);
353 goto exit;
354 }
355
356 /* Read and acknowledge the message */
357 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
358 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
359
360 /* Notify consumer of new mailbox message */
361 dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
362 mbox_value);
363 mbox->cb(mbox_value, mbox->client_data);
364
365exit:
366 dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
367 mbox->read_index, mbox->write_index);
368 spin_unlock(&mbox->lock);
369
370 return IRQ_HANDLED;
371}
372
373/* Setup is executed once for each mbox pair */
374struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
375{
376 struct resource *resource;
377 int irq;
378 int res;
379 struct mbox *mbox;
380
381 mbox = get_mbox_with_id(mbox_id);
382 if (mbox == NULL) {
383 dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
384 mbox_id);
385 goto exit;
386 }
387
388 /*
389 * Check if mailbox has been allocated to someone else,
390 * otherwise allocate it
391 */
392 if (mbox->allocated) {
393 dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
394 mbox_id);
395 mbox = NULL;
396 goto exit;
397 }
398 mbox->allocated = true;
399
400 dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
401 mbox_id, (u32)mbox);
402
403 mbox->client_data = priv;
404 mbox->cb = mbox_cb;
405
406 /* Get addr for peer mailbox and ioremap it */
407 resource = platform_get_resource_byname(mbox->pdev,
408 IORESOURCE_MEM,
409 "mbox_peer");
410 if (resource == NULL) {
411 dev_err(&(mbox->pdev->dev),
412 "Unable to retrieve mbox peer resource\n");
413 mbox = NULL;
414 goto exit;
415 }
416 dev_dbg(&(mbox->pdev->dev),
417 "Resource name: %s start: 0x%X, end: 0x%X\n",
418 resource->name, resource->start, resource->end);
419 mbox->virtbase_peer =
420 ioremap(resource->start, resource->end - resource->start);
421 if (!mbox->virtbase_peer) {
422 dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
423 mbox = NULL;
424 goto exit;
425 }
426 dev_dbg(&(mbox->pdev->dev),
427 "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
428 resource->start, resource->end, (u32) mbox->virtbase_peer);
429
430 /* Get addr for local mailbox and ioremap it */
431 resource = platform_get_resource_byname(mbox->pdev,
432 IORESOURCE_MEM,
433 "mbox_local");
434 if (resource == NULL) {
435 dev_err(&(mbox->pdev->dev),
436 "Unable to retrieve mbox local resource\n");
437 mbox = NULL;
438 goto exit;
439 }
440 dev_dbg(&(mbox->pdev->dev),
441 "Resource name: %s start: 0x%X, end: 0x%X\n",
442 resource->name, resource->start, resource->end);
443 mbox->virtbase_local =
444 ioremap(resource->start, resource->end - resource->start);
445 if (!mbox->virtbase_local) {
446 dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
447 mbox = NULL;
448 goto exit;
449 }
450 dev_dbg(&(mbox->pdev->dev),
451 "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
452 resource->start, resource->end, (u32) mbox->virtbase_peer);
453
454 init_completion(&mbox->buffer_available);
455 mbox->client_blocked = 0;
456
457 /* Get IRQ for mailbox and allocate it */
458 irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
459 if (irq < 0) {
460 dev_err(&(mbox->pdev->dev),
461 "Unable to retrieve mbox irq resource\n");
462 mbox = NULL;
463 goto exit;
464 }
465
466 dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
467 res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
468 if (res < 0) {
469 dev_err(&(mbox->pdev->dev),
470 "Unable to allocate mbox irq %d\n", irq);
471 mbox = NULL;
472 goto exit;
473 }
474
475 /* Set up mailbox to not launch IRQ on free space in mailbox */
476 writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
477
478 /*
479 * Set up mailbox to launch IRQ on new message if we have
480 * a callback set. If not, do not raise IRQ, but keep message
481 * in FIFO for manual retrieval
482 */
483 if (mbox_cb != NULL)
484 writel(MBOX_ENABLE_IRQ,
485 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
486 else
487 writel(MBOX_DISABLE_IRQ,
488 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
489
490#if defined(CONFIG_DEBUG_FS)
491 res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
492 if (res != 0)
493 dev_warn(&(mbox->pdev->dev),
494 "Unable to create mbox sysfs entry");
495
496 (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
497 NULL, &mbox_operations);
498#endif
499
500 dev_info(&(mbox->pdev->dev),
501 "Mailbox driver with index %d initated!\n", mbox_id);
502
503exit:
504 return mbox;
505}
506EXPORT_SYMBOL(mbox_setup);
507
508
509int __init mbox_probe(struct platform_device *pdev)
510{
511 struct mbox local_mbox;
512 struct mbox *mbox;
513 int res = 0;
514 dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
515
516 memset(&local_mbox, 0x0, sizeof(struct mbox));
517
518 /* Associate our mbox data with the platform device */
519 res = platform_device_add_data(pdev,
520 (void *) &local_mbox,
521 sizeof(struct mbox));
522 if (res != 0) {
523 dev_err(&(pdev->dev),
524 "Unable to allocate driver platform data!\n");
525 goto exit;
526 }
527
528 mbox = (struct mbox *) pdev->dev.platform_data;
529 mbox->pdev = pdev;
530 mbox->write_index = 0;
531 mbox->read_index = 0;
532
533 INIT_LIST_HEAD(&(mbox->list));
534 list_add_tail(&(mbox->list), &mboxs);
535
536 sprintf(mbox->name, "%s", MBOX_NAME);
537 spin_lock_init(&mbox->lock);
538
539 dev_info(&(pdev->dev), "Mailbox driver loaded\n");
540
541exit:
542 return res;
543}
544
545static struct platform_driver mbox_driver = {
546 .driver = {
547 .name = MBOX_NAME,
548 .owner = THIS_MODULE,
549 },
550};
551
552static int __init mbox_init(void)
553{
554 return platform_driver_probe(&mbox_driver, mbox_probe);
555}
556
557module_init(mbox_init);
558
559void __exit mbox_exit(void)
560{
561 platform_driver_unregister(&mbox_driver);
562}
563
564module_exit(mbox_exit);
565
566MODULE_LICENSE("GPL");
567MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem_irq.c
new file mode 100644
index 000000000000..3187f8871169
--- /dev/null
+++ b/arch/arm/mach-ux500/modem_irq.c
@@ -0,0 +1,139 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14
15#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
16#define MODEM_INTCON_SIZE 0xFFF
17
18#define DEST_IRQ41_OFFSET 0x2A4
19#define DEST_IRQ43_OFFSET 0x2AC
20#define DEST_IRQ45_OFFSET 0x2B4
21
22#define PRIO_IRQ41_OFFSET 0x6A4
23#define PRIO_IRQ43_OFFSET 0x6AC
24#define PRIO_IRQ45_OFFSET 0x6B4
25
26#define ALLOW_IRQ_OFFSET 0x104
27
28#define MODEM_INTCON_CPU_NBR 0x1
29#define MODEM_INTCON_PRIO_HIGH 0x0
30
31#define MODEM_INTCON_ALLOW_IRQ41 0x0200
32#define MODEM_INTCON_ALLOW_IRQ43 0x0800
33#define MODEM_INTCON_ALLOW_IRQ45 0x2000
34
35#define MODEM_IRQ_REG_OFFSET 0x4
36
37struct modem_irq {
38 void __iomem *modem_intcon_base;
39};
40
41
42static void setup_modem_intcon(void __iomem *modem_intcon_base)
43{
44 /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
45 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
46 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
47 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
48
49 /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
50 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
51 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
52 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
53
54 /* IC_ALLOW_ARRAY - IRQ enable */
55 writel(MODEM_INTCON_ALLOW_IRQ41 |
56 MODEM_INTCON_ALLOW_IRQ43 |
57 MODEM_INTCON_ALLOW_IRQ45,
58 modem_intcon_base + ALLOW_IRQ_OFFSET);
59}
60
61static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
62{
63 int real_irq;
64 int virt_irq;
65 struct modem_irq *mi = (struct modem_irq *)data;
66
67 /* Read modem side IRQ number from modem IRQ controller */
68 real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
69 virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
70
71 pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
72 "which will be 0x%X (%d) which translates to "
73 "virtual IRQ 0x%X (%d)!\n",
74 (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
75 real_irq,
76 real_irq & 0xFF,
77 real_irq & 0xFF,
78 virt_irq,
79 virt_irq);
80
81 if (virt_irq != 0)
82 generic_handle_irq(virt_irq);
83
84 pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
85
86 return IRQ_HANDLED;
87}
88
89static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
90{
91 set_irq_chip(irq, modem_irq_chip);
92 set_irq_handler(irq, handle_simple_irq);
93 set_irq_flags(irq, IRQF_VALID);
94
95 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
96}
97
98static int modem_irq_init(void)
99{
100 int err;
101 static struct irq_chip modem_irq_chip;
102 struct modem_irq *mi;
103
104 pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
105 IRQ_DB5500_MODEM);
106
107 mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
108 if (!mi) {
109 pr_err("modem_irq: Could not allocate device\n");
110 return -ENOMEM;
111 }
112
113 mi->modem_intcon_base =
114 ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
115 pr_debug("modem_irq: ioremapped modem_intcon_base from "
116 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
117 (u32)mi->modem_intcon_base);
118
119 setup_modem_intcon(mi->modem_intcon_base);
120
121 modem_irq_chip = dummy_irq_chip;
122 modem_irq_chip.name = "modem_irq";
123
124 /* Create the virtual IRQ:s needed */
125 create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
126 create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
127 create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
128
129 err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
130 modem_cpu_irq_handler, IRQF_ONESHOT,
131 "modem_irq", mi);
132 if (err)
133 pr_err("modem_irq: Could not register IRQ %d\n",
134 IRQ_DB5500_MODEM);
135
136 return 0;
137}
138
139arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
new file mode 100644
index 000000000000..bf50c21fe69d
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db5500.h
@@ -0,0 +1,620 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_DB5500_PINS_H
9#define __MACH_DB5500_PINS_H
10
11#define GPIO0_GPIO PIN_CFG(0, GPIO)
12#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A)
13
14#define GPIO1_GPIO PIN_CFG(1, GPIO)
15#define GPIO1_SM_A3 PIN_CFG(1, ALT_A)
16
17#define GPIO2_GPIO PIN_CFG(2, GPIO)
18#define GPIO2_SM_A4 PIN_CFG(2, ALT_A)
19#define GPIO2_SM_AVD PIN_CFG(2, ALT_B)
20
21#define GPIO3_GPIO PIN_CFG(3, GPIO)
22#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A)
23
24#define GPIO4_GPIO PIN_CFG(4, GPIO)
25#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A)
26
27#define GPIO5_GPIO PIN_CFG(5, GPIO)
28#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A)
29#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B)
30
31#define GPIO6_GPIO PIN_CFG(6, GPIO)
32#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A)
33#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B)
34
35#define GPIO7_GPIO PIN_CFG(7, GPIO)
36#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A)
37#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B)
38
39#define GPIO8_GPIO PIN_CFG(8, GPIO)
40#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A)
41#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B)
42
43#define GPIO9_GPIO PIN_CFG(9, GPIO)
44#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A)
45#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B)
46
47#define GPIO10_GPIO PIN_CFG(10, GPIO)
48#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A)
49#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B)
50
51#define GPIO11_GPIO PIN_CFG(11, GPIO)
52#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A)
53#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B)
54
55#define GPIO12_GPIO PIN_CFG(12, GPIO)
56#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A)
57#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B)
58
59#define GPIO13_GPIO PIN_CFG(13, GPIO)
60#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A)
61#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B)
62#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C)
63
64#define GPIO14_GPIO PIN_CFG(14, GPIO)
65#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A)
66#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B)
67#define GPIO14_SM_CKO PIN_CFG(14, ALT_C)
68
69#define GPIO15_GPIO PIN_CFG(15, GPIO)
70#define GPIO15_SM_A5 PIN_CFG(15, ALT_A)
71#define GPIO15_SM_CLE PIN_CFG(15, ALT_B)
72
73#define GPIO16_GPIO PIN_CFG(16, GPIO)
74#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A)
75#define GPIO16_SM_OEn PIN_CFG(16, ALT_B)
76
77#define GPIO17_GPIO PIN_CFG(17, GPIO)
78#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A)
79#define GPIO17_SM_WEn PIN_CFG(17, ALT_B)
80
81#define GPIO18_GPIO PIN_CFG(18, GPIO)
82#define GPIO18_SM_A6 PIN_CFG(18, ALT_A)
83#define GPIO18_SM_ALE PIN_CFG(18, ALT_B)
84#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C)
85
86#define GPIO19_GPIO PIN_CFG(19, GPIO)
87#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A)
88#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B)
89
90#define GPIO20_GPIO PIN_CFG(20, GPIO)
91#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A)
92#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B)
93
94#define GPIO21_GPIO PIN_CFG(21, GPIO)
95#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A)
96#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B)
97
98#define GPIO22_GPIO PIN_CFG(22, GPIO)
99#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A)
100#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B)
101
102#define GPIO23_GPIO PIN_CFG(23, GPIO)
103#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A)
104#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B)
105#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C)
106
107#define GPIO24_GPIO PIN_CFG(24, GPIO)
108#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A)
109#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B)
110#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C)
111
112#define GPIO25_GPIO PIN_CFG(25, GPIO)
113#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A)
114#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B)
115#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C)
116
117#define GPIO26_GPIO PIN_CFG(26, GPIO)
118#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A)
119#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B)
120
121#define GPIO27_GPIO PIN_CFG(27, GPIO)
122#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A)
123#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B)
124
125#define GPIO28_GPIO PIN_CFG(28, GPIO)
126#define GPIO28_U0_TXD PIN_CFG(28, ALT_A)
127#define GPIO28_SM_A0 PIN_CFG(28, ALT_B)
128
129#define GPIO29_GPIO PIN_CFG(29, GPIO)
130#define GPIO29_U0_RXD PIN_CFG(29, ALT_A)
131#define GPIO29_SM_A1 PIN_CFG(29, ALT_B)
132#define GPIO29_PWM_0 PIN_CFG(29, ALT_C)
133
134#define GPIO30_GPIO PIN_CFG(30, GPIO)
135#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
136#define GPIO30_SM_A2 PIN_CFG(30, ALT_B)
137#define GPIO30_PWM_1 PIN_CFG(30, ALT_C)
138
139#define GPIO31_GPIO PIN_CFG(31, GPIO)
140#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A)
141#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B)
142#define GPIO31_PWM_2 PIN_CFG(31, ALT_C)
143
144#define GPIO32_GPIO PIN_CFG(32, GPIO)
145#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A)
146#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B)
147
148#define GPIO33_GPIO PIN_CFG(33, GPIO)
149#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A)
150#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B)
151
152#define GPIO34_GPIO PIN_CFG(34, GPIO)
153#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A)
154#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B)
155
156#define GPIO35_GPIO PIN_CFG(35, GPIO)
157#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A)
158#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B)
159
160#define GPIO64_GPIO PIN_CFG(64, GPIO)
161#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A)
162#define GPIO64_U0_TXD PIN_CFG(64, ALT_B)
163
164#define GPIO65_GPIO PIN_CFG(65, GPIO)
165#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A)
166#define GPIO65_U0_RXD PIN_CFG(65, ALT_B)
167
168#define GPIO66_GPIO PIN_CFG(66, GPIO)
169#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A)
170
171#define GPIO67_GPIO PIN_CFG(67, GPIO)
172#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A)
173
174#define GPIO68_GPIO PIN_CFG(68, GPIO)
175#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A)
176
177#define GPIO69_GPIO PIN_CFG(69, GPIO)
178#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A)
179
180#define GPIO70_GPIO PIN_CFG(70, GPIO)
181#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A)
182
183#define GPIO71_GPIO PIN_CFG(71, GPIO)
184#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A)
185
186#define GPIO72_GPIO PIN_CFG(72, GPIO)
187#define GPIO72_USB_STP PIN_CFG(72, ALT_A)
188
189#define GPIO73_GPIO PIN_CFG(73, GPIO)
190#define GPIO73_USB_DIR PIN_CFG(73, ALT_A)
191
192#define GPIO74_GPIO PIN_CFG(74, GPIO)
193#define GPIO74_USB_NXT PIN_CFG(74, ALT_A)
194
195#define GPIO75_GPIO PIN_CFG(75, GPIO)
196#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A)
197
198#define GPIO76_GPIO PIN_CFG(76, GPIO)
199
200#define GPIO77_GPIO PIN_CFG(77, GPIO)
201#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A)
202
203#define GPIO78_GPIO PIN_CFG(78, GPIO)
204#define GPIO78_IRQn PIN_CFG(78, ALT_A)
205
206#define GPIO79_GPIO PIN_CFG(79, GPIO)
207#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A)
208
209#define GPIO80_GPIO PIN_CFG(80, GPIO)
210#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A)
211
212#define GPIO81_GPIO PIN_CFG(81, GPIO)
213#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A)
214
215#define GPIO82_GPIO PIN_CFG(82, GPIO)
216#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A)
217
218#define GPIO96_GPIO PIN_CFG(96, GPIO)
219#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A)
220#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B)
221#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C)
222
223#define GPIO97_GPIO PIN_CFG(97, GPIO)
224#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A)
225#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B)
226#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C)
227
228#define GPIO98_GPIO PIN_CFG(98, GPIO)
229#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A)
230#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B)
231#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C)
232
233#define GPIO99_GPIO PIN_CFG(99, GPIO)
234#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A)
235#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B)
236#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C)
237
238#define GPIO100_GPIO PIN_CFG(100, GPIO)
239#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A)
240
241#define GPIO101_GPIO PIN_CFG(101, GPIO)
242#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A)
243
244#define GPIO128_GPIO PIN_CFG(128, GPIO)
245#define GPIO128_KP_I0 PIN_CFG(128, ALT_A)
246#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B)
247
248#define GPIO129_GPIO PIN_CFG(129, GPIO)
249#define GPIO129_KP_O0 PIN_CFG(129, ALT_A)
250#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B)
251
252#define GPIO130_GPIO PIN_CFG(130, GPIO)
253#define GPIO130_KP_I1 PIN_CFG(130, ALT_A)
254#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B)
255
256#define GPIO131_GPIO PIN_CFG(131, GPIO)
257#define GPIO131_KP_O1 PIN_CFG(131, ALT_A)
258#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B)
259
260#define GPIO132_GPIO PIN_CFG(132, GPIO)
261#define GPIO132_KP_I2 PIN_CFG(132, ALT_A)
262#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B)
263#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C)
264
265#define GPIO133_GPIO PIN_CFG(133, GPIO)
266#define GPIO133_KP_O2 PIN_CFG(133, ALT_A)
267#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B)
268#define GPIO133_U0_RXD PIN_CFG(133, ALT_C)
269
270#define GPIO134_GPIO PIN_CFG(134, GPIO)
271#define GPIO134_KP_I3 PIN_CFG(134, ALT_A)
272#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B)
273#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C)
274
275#define GPIO135_GPIO PIN_CFG(135, GPIO)
276#define GPIO135_KP_O3 PIN_CFG(135, ALT_A)
277#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B)
278#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C)
279
280#define GPIO136_GPIO PIN_CFG(136, GPIO)
281#define GPIO136_KP_I4 PIN_CFG(136, ALT_A)
282#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B)
283#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C)
284
285#define GPIO137_GPIO PIN_CFG(137, GPIO)
286#define GPIO137_KP_O4 PIN_CFG(137, ALT_A)
287#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B)
288#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C)
289
290#define GPIO138_GPIO PIN_CFG(138, GPIO)
291#define GPIO138_KP_I5 PIN_CFG(138, ALT_A)
292#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B)
293#define GPIO138_U0_TXD PIN_CFG(138, ALT_C)
294
295#define GPIO139_GPIO PIN_CFG(139, GPIO)
296#define GPIO139_KP_O5 PIN_CFG(139, ALT_A)
297#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B)
298#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C)
299
300#define GPIO140_GPIO PIN_CFG(140, GPIO)
301#define GPIO140_KP_I6 PIN_CFG(140, ALT_A)
302#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B)
303#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C)
304
305#define GPIO141_GPIO PIN_CFG(141, GPIO)
306#define GPIO141_KP_O6 PIN_CFG(141, ALT_A)
307#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B)
308#define GPIO141_U0_RXD PIN_CFG(141, ALT_C)
309
310#define GPIO142_GPIO PIN_CFG(142, GPIO)
311#define GPIO142_KP_I7 PIN_CFG(142, ALT_A)
312#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B)
313#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C)
314
315#define GPIO143_GPIO PIN_CFG(143, GPIO)
316#define GPIO143_KP_O7 PIN_CFG(143, ALT_A)
317#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B)
318#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C)
319
320#define GPIO144_GPIO PIN_CFG(144, GPIO)
321#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A)
322#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B)
323#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C)
324
325#define GPIO145_GPIO PIN_CFG(145, GPIO)
326#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A)
327#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B)
328#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C)
329
330#define GPIO146_GPIO PIN_CFG(146, GPIO)
331#define GPIO146_PWM_0 PIN_CFG(146, ALT_A)
332#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B)
333
334#define GPIO147_GPIO PIN_CFG(147, GPIO)
335#define GPIO147_PWM_1 PIN_CFG(147, ALT_A)
336#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B)
337
338#define GPIO148_GPIO PIN_CFG(148, GPIO)
339#define GPIO148_PWM_2 PIN_CFG(148, ALT_A)
340#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B)
341
342#define GPIO160_GPIO PIN_CFG(160, GPIO)
343#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A)
344
345#define GPIO161_GPIO PIN_CFG(161, GPIO)
346#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A)
347
348#define GPIO162_GPIO PIN_CFG(162, GPIO)
349#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A)
350
351#define GPIO163_GPIO PIN_CFG(163, GPIO)
352
353#define GPIO164_GPIO PIN_CFG(164, GPIO)
354#define GPIO164_GPS_START PIN_CFG(164, ALT_A)
355
356#define GPIO165_GPIO PIN_CFG(165, GPIO)
357#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A)
358#define GPIO165_U3_RXD PIN_CFG(165, ALT_B)
359#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C)
360
361#define GPIO166_GPIO PIN_CFG(166, GPIO)
362#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A)
363#define GPIO166_U3_TXD PIN_CFG(166, ALT_B)
364#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C)
365
366#define GPIO167_GPIO PIN_CFG(167, GPIO)
367#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A)
368#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B)
369#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C)
370
371#define GPIO168_GPIO PIN_CFG(168, GPIO)
372#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A)
373#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B)
374#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C)
375
376#define GPIO169_GPIO PIN_CFG(169, GPIO)
377#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A)
378#define GPIO169_DDR_RC PIN_CFG(169, ALT_B)
379#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C)
380
381#define GPIO170_GPIO PIN_CFG(170, GPIO)
382#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A)
383
384#define GPIO171_GPIO PIN_CFG(171, GPIO)
385#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A)
386#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B)
387#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C)
388
389#define GPIO172_GPIO PIN_CFG(172, GPIO)
390#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A)
391#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B)
392#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C)
393
394#define GPIO173_GPIO PIN_CFG(173, GPIO)
395#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A)
396#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B)
397#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C)
398
399#define GPIO174_GPIO PIN_CFG(174, GPIO)
400#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A)
401#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B)
402#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C)
403
404#define GPIO175_GPIO PIN_CFG(175, GPIO)
405#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A)
406#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B)
407#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C)
408
409#define GPIO176_GPIO PIN_CFG(176, GPIO)
410#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A)
411#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B)
412
413#define GPIO177_GPIO PIN_CFG(177, GPIO)
414#define GPIO177_U2_RXD PIN_CFG(177, ALT_A)
415#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B)
416#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C)
417
418#define GPIO178_GPIO PIN_CFG(178, GPIO)
419#define GPIO178_U2_TXD PIN_CFG(178, ALT_A)
420#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B)
421#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C)
422
423#define GPIO179_GPIO PIN_CFG(179, GPIO)
424#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A)
425#define GPIO179_U3_RXD PIN_CFG(179, ALT_B)
426#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C)
427
428#define GPIO180_GPIO PIN_CFG(180, GPIO)
429#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A)
430#define GPIO180_U3_TXD PIN_CFG(180, ALT_B)
431#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C)
432
433#define GPIO185_GPIO PIN_CFG(185, GPIO)
434#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A)
435#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B)
436
437#define GPIO186_GPIO PIN_CFG(186, GPIO)
438#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A)
439#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B)
440
441#define GPIO187_GPIO PIN_CFG(187, GPIO)
442#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A)
443#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B)
444
445#define GPIO188_GPIO PIN_CFG(188, GPIO)
446#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A)
447#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B)
448
449#define GPIO189_GPIO PIN_CFG(189, GPIO)
450#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A)
451#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B)
452
453#define GPIO190_GPIO PIN_CFG(190, GPIO)
454#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A)
455#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B)
456
457#define GPIO191_GPIO PIN_CFG(191, GPIO)
458#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A)
459#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B)
460#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C)
461
462#define GPIO192_GPIO PIN_CFG(192, GPIO)
463#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A)
464#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B)
465#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C)
466
467#define GPIO193_GPIO PIN_CFG(193, GPIO)
468#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A)
469#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B)
470#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C)
471
472#define GPIO194_GPIO PIN_CFG(194, GPIO)
473#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A)
474#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B)
475#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C)
476
477#define GPIO195_GPIO PIN_CFG(195, GPIO)
478#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A)
479#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B)
480#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C)
481
482#define GPIO196_GPIO PIN_CFG(196, GPIO)
483#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A)
484#define GPIO196_U0_RXD PIN_CFG(196, ALT_B)
485#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C)
486
487#define GPIO197_GPIO PIN_CFG(197, GPIO)
488#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A)
489#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B)
490
491#define GPIO198_GPIO PIN_CFG(198, GPIO)
492#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A)
493
494#define GPIO199_GPIO PIN_CFG(199, GPIO)
495#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A)
496#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B)
497
498#define GPIO200_GPIO PIN_CFG(200, GPIO)
499#define GPIO200_U1_TXD PIN_CFG(200, ALT_A)
500#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B)
501
502#define GPIO201_GPIO PIN_CFG(201, GPIO)
503#define GPIO201_U1_RXD PIN_CFG(201, ALT_A)
504#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B)
505
506#define GPIO202_GPIO PIN_CFG(202, GPIO)
507#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A)
508#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B)
509
510#define GPIO203_GPIO PIN_CFG(203, GPIO)
511#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A)
512#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B)
513
514#define GPIO204_GPIO PIN_CFG(204, GPIO)
515#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A)
516#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B)
517#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C)
518
519#define GPIO205_GPIO PIN_CFG(205, GPIO)
520#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A)
521#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B)
522#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C)
523
524#define GPIO206_GPIO PIN_CFG(206, GPIO)
525#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A)
526#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B)
527#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C)
528
529#define GPIO207_GPIO PIN_CFG(207, GPIO)
530#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A)
531#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B)
532#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C)
533
534#define GPIO208_GPIO PIN_CFG(208, GPIO)
535#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A)
536#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B)
537#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C)
538
539#define GPIO209_GPIO PIN_CFG(209, GPIO)
540#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A)
541#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B)
542#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C)
543
544#define GPIO210_GPIO PIN_CFG(210, GPIO)
545#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A)
546#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B)
547
548#define GPIO211_GPIO PIN_CFG(211, GPIO)
549#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A)
550#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B)
551
552#define GPIO212_GPIO PIN_CFG(212, GPIO)
553#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A)
554#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B)
555
556#define GPIO213_GPIO PIN_CFG(213, GPIO)
557#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A)
558#define GPIO213_LCD_DE PIN_CFG(213, ALT_B)
559#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C)
560
561#define GPIO214_GPIO PIN_CFG(214, GPIO)
562#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A)
563#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B)
564#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C)
565
566#define GPIO215_GPIO PIN_CFG(215, GPIO)
567#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A)
568#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B)
569#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C)
570
571#define GPIO216_GPIO PIN_CFG(216, GPIO)
572#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A)
573#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B)
574
575#define GPIO217_GPIO PIN_CFG(217, GPIO)
576#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A)
577#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B)
578#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C)
579
580#define GPIO218_GPIO PIN_CFG(218, GPIO)
581#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A)
582#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B)
583
584#define GPIO219_GPIO PIN_CFG(219, GPIO)
585#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A)
586#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B)
587
588#define GPIO220_GPIO PIN_CFG(220, GPIO)
589#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A)
590#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B)
591
592#define GPIO221_GPIO PIN_CFG(221, GPIO)
593#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A)
594#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B)
595
596#define GPIO222_GPIO PIN_CFG(222, GPIO)
597#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A)
598#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B)
599
600#define GPIO223_GPIO PIN_CFG(223, GPIO)
601#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A)
602#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B)
603
604#define GPIO224_GPIO PIN_CFG(224, GPIO)
605#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A)
606#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B)
607
608#define GPIO225_GPIO PIN_CFG(225, GPIO)
609#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A)
610#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B)
611
612#define GPIO226_GPIO PIN_CFG(226, GPIO)
613#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A)
614#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B)
615
616#define GPIO227_GPIO PIN_CFG(227, GPIO)
617#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A)
618#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B)
619
620#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 9055d5d3233c..66f8761cc823 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -96,57 +96,57 @@
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) 96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97 97
98#define GPIO18_GPIO PIN_CFG(18, GPIO) 98#define GPIO18_GPIO PIN_CFG(18, GPIO)
99#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) 99#define GPIO18_MC0_CMDDIR PIN_CFG_PULL(18, ALT_A, UP)
100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) 100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) 101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
102 102
103#define GPIO19_GPIO PIN_CFG(19, GPIO) 103#define GPIO19_GPIO PIN_CFG(19, GPIO)
104#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) 104#define GPIO19_MC0_DAT0DIR PIN_CFG_PULL(19, ALT_A, UP)
105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) 105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) 106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
107 107
108#define GPIO20_GPIO PIN_CFG(20, GPIO) 108#define GPIO20_GPIO PIN_CFG(20, GPIO)
109#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) 109#define GPIO20_MC0_DAT2DIR PIN_CFG_PULL(20, ALT_A, UP)
110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) 110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) 111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
112 112
113#define GPIO21_GPIO PIN_CFG(21, GPIO) 113#define GPIO21_GPIO PIN_CFG(21, GPIO)
114#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) 114#define GPIO21_MC0_DAT31DIR PIN_CFG_PULL(21, ALT_A, UP)
115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) 115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) 116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
117 117
118#define GPIO22_GPIO PIN_CFG(22, GPIO) 118#define GPIO22_GPIO PIN_CFG(22, GPIO)
119#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) 119#define GPIO22_MC0_FBCLK PIN_CFG_PULL(22, ALT_A, UP)
120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) 120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) 121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
122 122
123#define GPIO23_GPIO PIN_CFG(23, GPIO) 123#define GPIO23_GPIO PIN_CFG(23, GPIO)
124#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) 124#define GPIO23_MC0_CLK PIN_CFG_PULL(23, ALT_A, UP)
125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) 125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) 126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
127 127
128#define GPIO24_GPIO PIN_CFG(24, GPIO) 128#define GPIO24_GPIO PIN_CFG(24, GPIO)
129#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) 129#define GPIO24_MC0_CMD PIN_CFG_PULL(24, ALT_A, UP)
130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) 130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
131#define GPIO24_MS_BS PIN_CFG(24, ALT_C) 131#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
132 132
133#define GPIO25_GPIO PIN_CFG(25, GPIO) 133#define GPIO25_GPIO PIN_CFG(25, GPIO)
134#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) 134#define GPIO25_MC0_DAT0 PIN_CFG_PULL(25, ALT_A, UP)
135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) 135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) 136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
137 137
138#define GPIO26_GPIO PIN_CFG(26, GPIO) 138#define GPIO26_GPIO PIN_CFG(26, GPIO)
139#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) 139#define GPIO26_MC0_DAT1 PIN_CFG_PULL(26, ALT_A, UP)
140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) 140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) 141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
142 142
143#define GPIO27_GPIO PIN_CFG(27, GPIO) 143#define GPIO27_GPIO PIN_CFG(27, GPIO)
144#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) 144#define GPIO27_MC0_DAT2 PIN_CFG_PULL(27, ALT_A, UP)
145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) 145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) 146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
147 147
148#define GPIO28_GPIO PIN_CFG(28, GPIO) 148#define GPIO28_GPIO PIN_CFG(28, GPIO)
149#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) 149#define GPIO28_MC0_DAT3 PIN_CFG_PULL(28, ALT_A, UP)
150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) 150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) 151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
152 152
@@ -357,48 +357,48 @@
357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) 357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
358 358
359#define GPIO128_GPIO PIN_CFG(128, GPIO) 359#define GPIO128_GPIO PIN_CFG(128, GPIO)
360#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) 360#define GPIO128_MC2_CLK PIN_CFG_PULL(128, ALT_A, UP)
361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) 361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
362 362
363#define GPIO129_GPIO PIN_CFG(129, GPIO) 363#define GPIO129_GPIO PIN_CFG(129, GPIO)
364#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) 364#define GPIO129_MC2_CMD PIN_CFG_PULL(129, ALT_A, UP)
365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) 365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
366 366
367#define GPIO130_GPIO PIN_CFG(130, GPIO) 367#define GPIO130_GPIO PIN_CFG(130, GPIO)
368#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) 368#define GPIO130_MC2_FBCLK PIN_CFG_PULL(130, ALT_A, UP)
369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) 369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) 370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
371 371
372#define GPIO131_GPIO PIN_CFG(131, GPIO) 372#define GPIO131_GPIO PIN_CFG(131, GPIO)
373#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) 373#define GPIO131_MC2_DAT0 PIN_CFG_PULL(131, ALT_A, UP)
374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) 374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
375 375
376#define GPIO132_GPIO PIN_CFG(132, GPIO) 376#define GPIO132_GPIO PIN_CFG(132, GPIO)
377#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) 377#define GPIO132_MC2_DAT1 PIN_CFG_PULL(132, ALT_A, UP)
378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) 378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
379 379
380#define GPIO133_GPIO PIN_CFG(133, GPIO) 380#define GPIO133_GPIO PIN_CFG(133, GPIO)
381#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) 381#define GPIO133_MC2_DAT2 PIN_CFG_PULL(133, ALT_A, UP)
382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) 382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
383 383
384#define GPIO134_GPIO PIN_CFG(134, GPIO) 384#define GPIO134_GPIO PIN_CFG(134, GPIO)
385#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) 385#define GPIO134_MC2_DAT3 PIN_CFG_PULL(134, ALT_A, UP)
386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) 386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
387 387
388#define GPIO135_GPIO PIN_CFG(135, GPIO) 388#define GPIO135_GPIO PIN_CFG(135, GPIO)
389#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) 389#define GPIO135_MC2_DAT4 PIN_CFG_PULL(135, ALT_A, UP)
390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) 390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
391 391
392#define GPIO136_GPIO PIN_CFG(136, GPIO) 392#define GPIO136_GPIO PIN_CFG(136, GPIO)
393#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) 393#define GPIO136_MC2_DAT5 PIN_CFG_PULL(136, ALT_A, UP)
394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) 394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
395 395
396#define GPIO137_GPIO PIN_CFG(137, GPIO) 396#define GPIO137_GPIO PIN_CFG(137, GPIO)
397#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) 397#define GPIO137_MC2_DAT6 PIN_CFG_PULL(137, ALT_A, UP)
398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) 398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
399 399
400#define GPIO138_GPIO PIN_CFG(138, GPIO) 400#define GPIO138_GPIO PIN_CFG(138, GPIO)
401#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) 401#define GPIO138_MC2_DAT7 PIN_CFG_PULL(138, ALT_A, UP)
402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) 402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
403 403
404#define GPIO139_GPIO PIN_CFG(139, GPIO) 404#define GPIO139_GPIO PIN_CFG(139, GPIO)
@@ -569,39 +569,39 @@
569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) 569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
570 570
571#define GPIO197_GPIO PIN_CFG(197, GPIO) 571#define GPIO197_GPIO PIN_CFG(197, GPIO)
572#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) 572#define GPIO197_MC4_DAT3 PIN_CFG_PULL(197, ALT_A, UP)
573 573
574#define GPIO198_GPIO PIN_CFG(198, GPIO) 574#define GPIO198_GPIO PIN_CFG(198, GPIO)
575#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) 575#define GPIO198_MC4_DAT2 PIN_CFG_PULL(198, ALT_A, UP)
576 576
577#define GPIO199_GPIO PIN_CFG(199, GPIO) 577#define GPIO199_GPIO PIN_CFG(199, GPIO)
578#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) 578#define GPIO199_MC4_DAT1 PIN_CFG_PULL(199, ALT_A, UP)
579 579
580#define GPIO200_GPIO PIN_CFG(200, GPIO) 580#define GPIO200_GPIO PIN_CFG(200, GPIO)
581#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) 581#define GPIO200_MC4_DAT0 PIN_CFG_PULL(200, ALT_A, UP)
582 582
583#define GPIO201_GPIO PIN_CFG(201, GPIO) 583#define GPIO201_GPIO PIN_CFG(201, GPIO)
584#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) 584#define GPIO201_MC4_CMD PIN_CFG_PULL(201, ALT_A, UP)
585 585
586#define GPIO202_GPIO PIN_CFG(202, GPIO) 586#define GPIO202_GPIO PIN_CFG(202, GPIO)
587#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) 587#define GPIO202_MC4_FBCLK PIN_CFG_PULL(202, ALT_A, UP)
588#define GPIO202_PWL PIN_CFG(202, ALT_B) 588#define GPIO202_PWL PIN_CFG(202, ALT_B)
589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) 589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
590 590
591#define GPIO203_GPIO PIN_CFG(203, GPIO) 591#define GPIO203_GPIO PIN_CFG(203, GPIO)
592#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) 592#define GPIO203_MC4_CLK PIN_CFG_PULL(203, ALT_A, UP)
593 593
594#define GPIO204_GPIO PIN_CFG(204, GPIO) 594#define GPIO204_GPIO PIN_CFG(204, GPIO)
595#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) 595#define GPIO204_MC4_DAT7 PIN_CFG_PULL(204, ALT_A, UP)
596 596
597#define GPIO205_GPIO PIN_CFG(205, GPIO) 597#define GPIO205_GPIO PIN_CFG(205, GPIO)
598#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) 598#define GPIO205_MC4_DAT6 PIN_CFG_PULL(205, ALT_A, UP)
599 599
600#define GPIO206_GPIO PIN_CFG(206, GPIO) 600#define GPIO206_GPIO PIN_CFG(206, GPIO)
601#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) 601#define GPIO206_MC4_DAT5 PIN_CFG_PULL(206, ALT_A, UP)
602 602
603#define GPIO207_GPIO PIN_CFG(207, GPIO) 603#define GPIO207_GPIO PIN_CFG(207, GPIO)
604#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) 604#define GPIO207_MC4_DAT4 PIN_CFG_PULL(207, ALT_A, UP)
605 605
606#define GPIO208_GPIO PIN_CFG(208, GPIO) 606#define GPIO208_GPIO PIN_CFG(208, GPIO)
607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) 607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 438ef16aec90..9e4c678de785 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -78,6 +78,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
78 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); 78 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
79 outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); 79 outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
80 80
81 smp_cross_call(cpumask_of(cpu));
82
81 timeout = jiffies + (1 * HZ); 83 timeout = jiffies + (1 * HZ);
82 while (time_before(jiffies, timeout)) { 84 while (time_before(jiffies, timeout)) {
83 if (pen_release == -1) 85 if (pen_release == -1)
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
new file mode 100644
index 000000000000..293274d1342a
--- /dev/null
+++ b/arch/arm/mach-ux500/prcmu.c
@@ -0,0 +1,231 @@
1/*
2 * Copyright (C) ST Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
6 *
7 * U8500 PRCMU driver.
8 */
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/mutex.h>
15#include <linux/completion.h>
16#include <linux/jiffies.h>
17#include <linux/bitops.h>
18#include <linux/interrupt.h>
19
20#include <mach/hardware.h>
21#include <mach/prcmu-regs.h>
22
23#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
24
25#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
26#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
27
28#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
29#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
30#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
31#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
32
33#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
34#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
35
36#define I2C_WRITE(slave) ((slave) << 1)
37#define I2C_READ(slave) (((slave) << 1) | BIT(0))
38#define I2C_STOP_EN BIT(3)
39
40enum ack_mb5_status {
41 I2C_WR_OK = 0x01,
42 I2C_RD_OK = 0x02,
43};
44
45#define MBOX_BIT BIT
46#define NUM_MBOX 8
47
48static struct {
49 struct mutex lock;
50 struct completion work;
51 bool failed;
52 struct {
53 u8 status;
54 u8 value;
55 } ack;
56} mb5_transfer;
57
58/**
59 * prcmu_abb_read() - Read register value(s) from the ABB.
60 * @slave: The I2C slave address.
61 * @reg: The (start) register address.
62 * @value: The read out value(s).
63 * @size: The number of registers to read.
64 *
65 * Reads register value(s) from the ABB.
66 * @size has to be 1 for the current firmware version.
67 */
68int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
69{
70 int r;
71
72 if (size != 1)
73 return -EINVAL;
74
75 r = mutex_lock_interruptible(&mb5_transfer.lock);
76 if (r)
77 return r;
78
79 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
80 cpu_relax();
81
82 writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
83 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
84 writeb(reg, REQ_MB5_I2C_REG);
85
86 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
87 if (!wait_for_completion_timeout(&mb5_transfer.work,
88 msecs_to_jiffies(500))) {
89 pr_err("prcmu: prcmu_abb_read timed out.\n");
90 r = -EIO;
91 goto unlock_and_return;
92 }
93 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
94 if (!r)
95 *value = mb5_transfer.ack.value;
96
97unlock_and_return:
98 mutex_unlock(&mb5_transfer.lock);
99 return r;
100}
101EXPORT_SYMBOL(prcmu_abb_read);
102
103/**
104 * prcmu_abb_write() - Write register value(s) to the ABB.
105 * @slave: The I2C slave address.
106 * @reg: The (start) register address.
107 * @value: The value(s) to write.
108 * @size: The number of registers to write.
109 *
110 * Reads register value(s) from the ABB.
111 * @size has to be 1 for the current firmware version.
112 */
113int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
114{
115 int r;
116
117 if (size != 1)
118 return -EINVAL;
119
120 r = mutex_lock_interruptible(&mb5_transfer.lock);
121 if (r)
122 return r;
123
124
125 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
126 cpu_relax();
127
128 writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
129 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
130 writeb(reg, REQ_MB5_I2C_REG);
131 writeb(*value, REQ_MB5_I2C_VAL);
132
133 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
134 if (!wait_for_completion_timeout(&mb5_transfer.work,
135 msecs_to_jiffies(500))) {
136 pr_err("prcmu: prcmu_abb_write timed out.\n");
137 r = -EIO;
138 goto unlock_and_return;
139 }
140 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
141
142unlock_and_return:
143 mutex_unlock(&mb5_transfer.lock);
144 return r;
145}
146EXPORT_SYMBOL(prcmu_abb_write);
147
148static void read_mailbox_0(void)
149{
150 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
151}
152
153static void read_mailbox_1(void)
154{
155 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
156}
157
158static void read_mailbox_2(void)
159{
160 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
161}
162
163static void read_mailbox_3(void)
164{
165 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
166}
167
168static void read_mailbox_4(void)
169{
170 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
171}
172
173static void read_mailbox_5(void)
174{
175 mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
176 mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
177 complete(&mb5_transfer.work);
178 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
179}
180
181static void read_mailbox_6(void)
182{
183 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
184}
185
186static void read_mailbox_7(void)
187{
188 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
189}
190
191static void (* const read_mailbox[NUM_MBOX])(void) = {
192 read_mailbox_0,
193 read_mailbox_1,
194 read_mailbox_2,
195 read_mailbox_3,
196 read_mailbox_4,
197 read_mailbox_5,
198 read_mailbox_6,
199 read_mailbox_7
200};
201
202static irqreturn_t prcmu_irq_handler(int irq, void *data)
203{
204 u32 bits;
205 u8 n;
206
207 bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
208 if (unlikely(!bits))
209 return IRQ_NONE;
210
211 for (n = 0; bits; n++) {
212 if (bits & MBOX_BIT(n)) {
213 bits -= MBOX_BIT(n);
214 read_mailbox[n]();
215 }
216 }
217 return IRQ_HANDLED;
218}
219
220static int __init prcmu_init(void)
221{
222 mutex_init(&mb5_transfer.lock);
223 init_completion(&mb5_transfer.work);
224
225 /* Clean up the mailbox interrupts after pre-kernel code. */
226 writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
227
228 return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
229}
230
231arch_initcall(prcmu_init);
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
new file mode 100644
index 000000000000..cb2110c32858
--- /dev/null
+++ b/arch/arm/mach-ux500/ste-dma40-db5500.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * DB5500-SoC-specific configuration for DMA40
8 */
9
10#ifndef STE_DMA40_DB5500_H
11#define STE_DMA40_DB5500_H
12
13#define DB5500_DMA_NR_DEV 64
14
15enum dma_src_dev_type {
16 DB5500_DMA_DEV0_SPI0_RX = 0,
17 DB5500_DMA_DEV1_SPI1_RX = 1,
18 DB5500_DMA_DEV2_SPI2_RX = 2,
19 DB5500_DMA_DEV3_SPI3_RX = 3,
20 DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
21 DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
22 DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
23 DB5500_DMA_DEV7_IRDA_RFS = 7,
24 DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
25 DB5500_DMA_DEV9_MSP0_RX = 9,
26 DB5500_DMA_DEV10_MSP1_RX = 10,
27 DB5500_DMA_DEV11_MSP2_RX = 11,
28 DB5500_DMA_DEV12_UART0_RX = 12,
29 DB5500_DMA_DEV13_UART1_RX = 13,
30 DB5500_DMA_DEV14_UART2_RX = 14,
31 DB5500_DMA_DEV15_UART3_RX = 15,
32 DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
33 DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
34 DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
35 DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
36 DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
37 DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
38 DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
39 DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
40 DB5500_DMA_DEV24_SDMMC0_RX = 24,
41 DB5500_DMA_DEV25_SDMMC1_RX = 25,
42 DB5500_DMA_DEV26_SDMMC2_RX = 26,
43 DB5500_DMA_DEV27_SDMMC3_RX = 27,
44 DB5500_DMA_DEV28_SDMMC4_RX = 28,
45 /* 29 - 32 not used */
46 DB5500_DMA_DEV33_SDMMC0_RX = 33,
47 DB5500_DMA_DEV34_SDMMC1_RX = 34,
48 DB5500_DMA_DEV35_SDMMC2_RX = 35,
49 DB5500_DMA_DEV36_SDMMC3_RX = 36,
50 DB5500_DMA_DEV37_SDMMC4_RX = 37,
51 DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
52 DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
53 DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
54 DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
55 DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
56 DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
57 DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
58 DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
59 /* 46 not used */
60 DB5500_DMA_DEV47_MCDE_RX = 47,
61 DB5500_DMA_DEV48_CRYPTO1_RX = 48,
62 /* 49, 50 not used */
63 DB5500_DMA_DEV49_I2C1_RX = 51,
64 DB5500_DMA_DEV50_I2C3_RX = 52,
65 DB5500_DMA_DEV51_I2C2_RX = 53,
66 /* 54 - 60 not used */
67 DB5500_DMA_DEV61_CRYPTO0_RX = 61,
68 /* 62, 63 not used */
69};
70
71enum dma_dest_dev_type {
72 DB5500_DMA_DEV0_SPI0_TX = 0,
73 DB5500_DMA_DEV1_SPI1_TX = 1,
74 DB5500_DMA_DEV2_SPI2_TX = 2,
75 DB5500_DMA_DEV3_SPI3_TX = 3,
76 DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
77 DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
78 DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
79 DB5500_DMA_DEV7_IRRC_TX = 7,
80 DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
81 DB5500_DMA_DEV9_MSP0_TX = 9,
82 DB5500_DMA_DEV10_MSP1_TX = 10,
83 DB5500_DMA_DEV11_MSP2_TX = 11,
84 DB5500_DMA_DEV12_UART0_TX = 12,
85 DB5500_DMA_DEV13_UART1_TX = 13,
86 DB5500_DMA_DEV14_UART2_TX = 14,
87 DB5500_DMA_DEV15_UART3_TX = 15,
88 DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
89 DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
90 DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
91 DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
92 DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
93 DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
94 DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
95 DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
96 DB5500_DMA_DEV24_SDMMC0_TX = 24,
97 DB5500_DMA_DEV25_SDMMC1_TX = 25,
98 DB5500_DMA_DEV26_SDMMC2_TX = 26,
99 DB5500_DMA_DEV27_SDMMC3_TX = 27,
100 DB5500_DMA_DEV28_SDMMC4_TX = 28,
101 /* 29 - 31 not used */
102 DB5500_DMA_DEV32_FSMC_TX = 32,
103 DB5500_DMA_DEV33_SDMMC0_TX = 33,
104 DB5500_DMA_DEV34_SDMMC1_TX = 34,
105 DB5500_DMA_DEV35_SDMMC2_TX = 35,
106 DB5500_DMA_DEV36_SDMMC3_TX = 36,
107 DB5500_DMA_DEV37_SDMMC4_TX = 37,
108 DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
109 DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
110 DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
111 DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
112 DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
113 DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
114 DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
115 DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
116 /* 46 not used */
117 DB5500_DMA_DEV47_STM_TX = 47,
118 DB5500_DMA_DEV48_CRYPTO1_TX = 48,
119 DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
120 DB5500_DMA_DEV50_HASH1_TX = 50,
121 DB5500_DMA_DEV51_I2C1_TX = 51,
122 DB5500_DMA_DEV52_I2C3_TX = 52,
123 DB5500_DMA_DEV53_I2C2_TX = 53,
124 /* 54, 55 not used */
125 DB5500_DMA_MEMCPY_TX_1 = 56,
126 DB5500_DMA_MEMCPY_TX_2 = 57,
127 DB5500_DMA_MEMCPY_TX_3 = 58,
128 DB5500_DMA_MEMCPY_TX_4 = 59,
129 DB5500_DMA_MEMCPY_TX_5 = 60,
130 DB5500_DMA_DEV61_CRYPTO0_TX = 61,
131 DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
132 DB5500_DMA_DEV63_HASH0_TX = 63,
133};
134
135#endif
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index 9d9d3797b3b0..a616419bea76 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -10,145 +10,135 @@
10#ifndef STE_DMA40_DB8500_H 10#ifndef STE_DMA40_DB8500_H
11#define STE_DMA40_DB8500_H 11#define STE_DMA40_DB8500_H
12 12
13#define STEDMA40_NR_DEV 64 13#define DB8500_DMA_NR_DEV 64
14 14
15enum dma_src_dev_type { 15enum dma_src_dev_type {
16 STEDMA40_DEV_SPI0_RX = 0, 16 DB8500_DMA_DEV0_SPI0_RX = 0,
17 STEDMA40_DEV_SD_MMC0_RX = 1, 17 DB8500_DMA_DEV1_SD_MMC0_RX = 1,
18 STEDMA40_DEV_SD_MMC1_RX = 2, 18 DB8500_DMA_DEV2_SD_MMC1_RX = 2,
19 STEDMA40_DEV_SD_MMC2_RX = 3, 19 DB8500_DMA_DEV3_SD_MMC2_RX = 3,
20 STEDMA40_DEV_I2C1_RX = 4, 20 DB8500_DMA_DEV4_I2C1_RX = 4,
21 STEDMA40_DEV_I2C3_RX = 5, 21 DB8500_DMA_DEV5_I2C3_RX = 5,
22 STEDMA40_DEV_I2C2_RX = 6, 22 DB8500_DMA_DEV6_I2C2_RX = 6,
23 STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */ 23 DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
24 STEDMA40_DEV_SSP0_RX = 8, 24 DB8500_DMA_DEV8_SSP0_RX = 8,
25 STEDMA40_DEV_SSP1_RX = 9, 25 DB8500_DMA_DEV9_SSP1_RX = 9,
26 STEDMA40_DEV_MCDE_RX = 10, 26 DB8500_DMA_DEV10_MCDE_RX = 10,
27 STEDMA40_DEV_UART2_RX = 11, 27 DB8500_DMA_DEV11_UART2_RX = 11,
28 STEDMA40_DEV_UART1_RX = 12, 28 DB8500_DMA_DEV12_UART1_RX = 12,
29 STEDMA40_DEV_UART0_RX = 13, 29 DB8500_DMA_DEV13_UART0_RX = 13,
30 STEDMA40_DEV_MSP2_RX = 14, 30 DB8500_DMA_DEV14_MSP2_RX = 14,
31 STEDMA40_DEV_I2C0_RX = 15, 31 DB8500_DMA_DEV15_I2C0_RX = 15,
32 STEDMA40_DEV_USB_OTG_IEP_8 = 16, 32 DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
33 STEDMA40_DEV_USB_OTG_IEP_1_9 = 17, 33 DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
34 STEDMA40_DEV_USB_OTG_IEP_2_10 = 18, 34 DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
35 STEDMA40_DEV_USB_OTG_IEP_3_11 = 19, 35 DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
36 STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20, 36 DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
37 STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21, 37 DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
38 STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22, 38 DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
39 STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23, 39 DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
40 STEDMA40_DEV_SRC_SXA0_RX_TX = 24, 40 DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
41 STEDMA40_DEV_SRC_SXA1_RX_TX = 25, 41 DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
42 STEDMA40_DEV_SRC_SXA2_RX_TX = 26, 42 DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
43 STEDMA40_DEV_SRC_SXA3_RX_TX = 27, 43 DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
44 STEDMA40_DEV_SD_MM2_RX = 28, 44 DB8500_DMA_DEV28_SD_MM2_RX = 28,
45 STEDMA40_DEV_SD_MM0_RX = 29, 45 DB8500_DMA_DEV29_SD_MM0_RX = 29,
46 STEDMA40_DEV_MSP1_RX = 30, 46 DB8500_DMA_DEV30_MSP1_RX = 30,
47 /* 47 /* On DB8500v2, MSP3 RX replaces MSP1 RX */
48 * This channel is either SlimBus or MSP, 48 DB8500_DMA_DEV30_MSP3_RX = 30,
49 * never both at the same time. 49 DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
50 */ 50 DB8500_DMA_DEV32_SD_MM1_RX = 32,
51 STEDMA40_SLIM0_CH0_RX = 31, 51 DB8500_DMA_DEV33_SPI2_RX = 33,
52 STEDMA40_DEV_MSP0_RX = 31, 52 DB8500_DMA_DEV34_I2C3_RX2 = 34,
53 STEDMA40_DEV_SD_MM1_RX = 32, 53 DB8500_DMA_DEV35_SPI1_RX = 35,
54 STEDMA40_DEV_SPI2_RX = 33, 54 DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
55 STEDMA40_DEV_I2C3_RX2 = 34, 55 DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
56 STEDMA40_DEV_SPI1_RX = 35, 56 DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
57 STEDMA40_DEV_USB_OTG_IEP_4_12 = 36, 57 DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
58 STEDMA40_DEV_USB_OTG_IEP_5_13 = 37, 58 DB8500_DMA_DEV40_SPI3_RX = 40,
59 STEDMA40_DEV_USB_OTG_IEP_6_14 = 38, 59 DB8500_DMA_DEV41_SD_MM3_RX = 41,
60 STEDMA40_DEV_USB_OTG_IEP_7_15 = 39, 60 DB8500_DMA_DEV42_SD_MM4_RX = 42,
61 STEDMA40_DEV_SPI3_RX = 40, 61 DB8500_DMA_DEV43_SD_MM5_RX = 43,
62 STEDMA40_DEV_SD_MM3_RX = 41, 62 DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
63 STEDMA40_DEV_SD_MM4_RX = 42, 63 DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
64 STEDMA40_DEV_SD_MM5_RX = 43, 64 DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
65 STEDMA40_DEV_SRC_SXA4_RX_TX = 44, 65 DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
66 STEDMA40_DEV_SRC_SXA5_RX_TX = 45, 66 DB8500_DMA_DEV48_CAC1_RX = 48,
67 STEDMA40_DEV_SRC_SXA6_RX_TX = 46, 67 /* 49, 50 and 51 are not used */
68 STEDMA40_DEV_SRC_SXA7_RX_TX = 47, 68 DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
69 STEDMA40_DEV_CAC1_RX = 48, 69 DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
70 /* RX channels 49 and 50 are unused */ 70 DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
71 STEDMA40_DEV_MSHC_RX = 51, 71 DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
72 STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52, 72 /* 56, 57, 58, 59 and 60 are not used */
73 STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53, 73 DB8500_DMA_DEV61_CAC0_RX = 61,
74 STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54, 74 /* 62 and 63 are not used */
75 STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
76 /* RX channels 56 thru 60 are unused */
77 STEDMA40_DEV_CAC0_RX = 61,
78 /* RX channels 62 and 63 are unused */
79}; 75};
80 76
81enum dma_dest_dev_type { 77enum dma_dest_dev_type {
82 STEDMA40_DEV_SPI0_TX = 0, 78 DB8500_DMA_DEV0_SPI0_TX = 0,
83 STEDMA40_DEV_SD_MMC0_TX = 1, 79 DB8500_DMA_DEV1_SD_MMC0_TX = 1,
84 STEDMA40_DEV_SD_MMC1_TX = 2, 80 DB8500_DMA_DEV2_SD_MMC1_TX = 2,
85 STEDMA40_DEV_SD_MMC2_TX = 3, 81 DB8500_DMA_DEV3_SD_MMC2_TX = 3,
86 STEDMA40_DEV_I2C1_TX = 4, 82 DB8500_DMA_DEV4_I2C1_TX = 4,
87 STEDMA40_DEV_I2C3_TX = 5, 83 DB8500_DMA_DEV5_I2C3_TX = 5,
88 STEDMA40_DEV_I2C2_TX = 6, 84 DB8500_DMA_DEV6_I2C2_TX = 6,
89 STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */ 85 DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
90 STEDMA40_DEV_SSP0_TX = 8, 86 DB8500_DMA_DEV8_SSP0_TX = 8,
91 STEDMA40_DEV_SSP1_TX = 9, 87 DB8500_DMA_DEV9_SSP1_TX = 9,
92 /* TX channel 10 is unused */ 88 /* 10 is not used*/
93 STEDMA40_DEV_UART2_TX = 11, 89 DB8500_DMA_DEV11_UART2_TX = 11,
94 STEDMA40_DEV_UART1_TX = 12, 90 DB8500_DMA_DEV12_UART1_TX = 12,
95 STEDMA40_DEV_UART0_TX= 13, 91 DB8500_DMA_DEV13_UART0_TX = 13,
96 STEDMA40_DEV_MSP2_TX = 14, 92 DB8500_DMA_DEV14_MSP2_TX = 14,
97 STEDMA40_DEV_I2C0_TX = 15, 93 DB8500_DMA_DEV15_I2C0_TX = 15,
98 STEDMA40_DEV_USB_OTG_OEP_8 = 16, 94 DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
99 STEDMA40_DEV_USB_OTG_OEP_1_9 = 17, 95 DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
100 STEDMA40_DEV_USB_OTG_OEP_2_10= 18, 96 DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
101 STEDMA40_DEV_USB_OTG_OEP_3_11 = 19, 97 DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
102 STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20, 98 DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
103 STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21, 99 DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
104 STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22, 100 DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
105 STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23, 101 DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
106 STEDMA40_DEV_DST_SXA0_RX_TX = 24, 102 DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
107 STEDMA40_DEV_DST_SXA1_RX_TX = 25, 103 DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
108 STEDMA40_DEV_DST_SXA2_RX_TX = 26, 104 DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
109 STEDMA40_DEV_DST_SXA3_RX_TX = 27, 105 DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
110 STEDMA40_DEV_SD_MM2_TX = 28, 106 DB8500_DMA_DEV28_SD_MM2_TX = 28,
111 STEDMA40_DEV_SD_MM0_TX = 29, 107 DB8500_DMA_DEV29_SD_MM0_TX = 29,
112 STEDMA40_DEV_MSP1_TX = 30, 108 DB8500_DMA_DEV30_MSP1_TX = 30,
113 /* 109 DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
114 * This channel is either SlimBus or MSP, 110 DB8500_DMA_DEV32_SD_MM1_TX = 32,
115 * never both at the same time. 111 DB8500_DMA_DEV33_SPI2_TX = 33,
116 */ 112 DB8500_DMA_DEV34_I2C3_TX2 = 34,
117 STEDMA40_SLIM0_CH0_TX = 31, 113 DB8500_DMA_DEV35_SPI1_TX = 35,
118 STEDMA40_DEV_MSP0_TX = 31, 114 DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
119 STEDMA40_DEV_SD_MM1_TX = 32, 115 DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
120 STEDMA40_DEV_SPI2_TX = 33, 116 DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
121 /* Secondary I2C3 channel */ 117 DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
122 STEDMA40_DEV_I2C3_TX2 = 34, 118 DB8500_DMA_DEV40_SPI3_TX = 40,
123 STEDMA40_DEV_SPI1_TX = 35, 119 DB8500_DMA_DEV41_SD_MM3_TX = 41,
124 STEDMA40_DEV_USB_OTG_OEP_4_12 = 36, 120 DB8500_DMA_DEV42_SD_MM4_TX = 42,
125 STEDMA40_DEV_USB_OTG_OEP_5_13 = 37, 121 DB8500_DMA_DEV43_SD_MM5_TX = 43,
126 STEDMA40_DEV_USB_OTG_OEP_6_14 = 38, 122 DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
127 STEDMA40_DEV_USB_OTG_OEP_7_15 = 39, 123 DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
128 STEDMA40_DEV_SPI3_TX = 40, 124 DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
129 STEDMA40_DEV_SD_MM3_TX = 41, 125 DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
130 STEDMA40_DEV_SD_MM4_TX = 42, 126 DB8500_DMA_DEV48_CAC1_TX = 48,
131 STEDMA40_DEV_SD_MM5_TX = 43, 127 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
132 STEDMA40_DEV_DST_SXA4_RX_TX = 44, 128 DB8500_DMA_DEV50_HAC1_TX = 50,
133 STEDMA40_DEV_DST_SXA5_RX_TX = 45, 129 DB8500_DMA_MEMCPY_TX_0 = 51,
134 STEDMA40_DEV_DST_SXA6_RX_TX = 46, 130 DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
135 STEDMA40_DEV_DST_SXA7_RX_TX = 47, 131 DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
136 STEDMA40_DEV_CAC1_TX = 48, 132 DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
137 STEDMA40_DEV_CAC1_TX_HAC1_TX = 49, 133 DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
138 STEDMA40_DEV_HAC1_TX = 50, 134 DB8500_DMA_MEMCPY_TX_1 = 56,
139 STEDMA40_MEMCPY_TX_0 = 51, 135 DB8500_DMA_MEMCPY_TX_2 = 57,
140 STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52, 136 DB8500_DMA_MEMCPY_TX_3 = 58,
141 STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53, 137 DB8500_DMA_MEMCPY_TX_4 = 59,
142 STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54, 138 DB8500_DMA_MEMCPY_TX_5 = 60,
143 STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55, 139 DB8500_DMA_DEV61_CAC0_TX = 61,
144 STEDMA40_MEMCPY_TX_1 = 56, 140 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
145 STEDMA40_MEMCPY_TX_2 = 57, 141 DB8500_DMA_DEV63_HAC0_TX = 63,
146 STEDMA40_MEMCPY_TX_3 = 58,
147 STEDMA40_MEMCPY_TX_4 = 59,
148 STEDMA40_MEMCPY_TX_5 = 60,
149 STEDMA40_DEV_CAC0_TX = 61,
150 STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
151 STEDMA40_DEV_HAC0_TX = 63,
152}; 142};
153 143
154#endif 144#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 09:23:44 -0500