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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 21:57:33 -0400
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 10:26:23 -0400
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/arm/mach-ux500
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r--arch/arm/mach-ux500/board-mop500.c2
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h10
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index dc8746d7826e..af913741e6ec 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -52,7 +52,7 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
52 * on value present in GpioSel1 to GpioSel6 and AlternatFunction 52 * on value present in GpioSel1 to GpioSel6 and AlternatFunction
53 * register. This is the array of 7 configuration settings. 53 * register. This is the array of 7 configuration settings.
54 * One has to compile time decide these settings. Below is the 54 * One has to compile time decide these settings. Below is the
55 * explaination of these setting 55 * explanation of these setting
56 * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO 56 * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
57 * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO 57 * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
58 * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO 58 * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 0fefb34c11e4..16647b255378 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -58,7 +58,7 @@
58#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) 58#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
59#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) 59#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
60 60
61/* per7 base addressess */ 61/* per7 base addresses */
62#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) 62#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
63#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) 63#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
64#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) 64#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
@@ -68,7 +68,7 @@
68#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) 68#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
69#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) 69#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
70 70
71/* per6 base addressess */ 71/* per6 base addresses */
72#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) 72#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
73#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) 73#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
74#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) 74#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
@@ -79,11 +79,11 @@
79#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) 79#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
80#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) 80#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
81 81
82/* per5 base addressess */ 82/* per5 base addresses */
83#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) 83#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
84#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) 84#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
85 85
86/* per4 base addressess */ 86/* per4 base addresses */
87#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) 87#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
88#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) 88#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
89#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) 89#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
@@ -106,7 +106,7 @@
106#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) 106#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
107#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) 107#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
108 108
109/* per2 base addressess */ 109/* per2 base addresses */
110#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) 110#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
111#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) 111#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
112#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) 112#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)