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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-12-04 11:01:03 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-14 14:21:40 -0500
commit384895330e0f3954d9478fd0853145f9c169df12 (patch)
treec90f70f4e070b640a1f1f2a76cf4acf864354093 /arch/arm/mach-ux500
parentb580b899dd05a007ad232ee49a07b32d91876462 (diff)
ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r--arch/arm/mach-ux500/platsmp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 9e4c678de785..b5077b4c419f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
44 * core (e.g. timer irq), then they will not have been enabled 44 * core (e.g. timer irq), then they will not have been enabled
45 * for us: do so 45 * for us: do so
46 */ 46 */
47 gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); 47 gic_secondary_init(0);
48 48
49 /* 49 /*
50 * let the primary processor know we're out of the 50 * let the primary processor know we're out of the