Merge branch 'next/timer' of git://git.linaro.org/people/arnd/arm-soc

* 'next/timer' of git://git.linaro.org/people/arnd/arm-soc:
  clocksource: fixup ux500 build problems
  ARM: omap: use __devexit_p in dmtimer driver
  ARM: ux500: Reprogram timers upon resume
  ARM: plat-nomadik: timer: Export reset functions
  ARM: plat-nomadik: timer: Add support for periodic timers
  ARM: ux500: Move timer code to separate file
  ARM: ux500: add support for clocksource DBX500 PRCMU
  clocksource: add DBX500 PRCMU Timer support
  ARM: plat-nomadik: MTU sched_clock as an option
  ARM: OMAP: dmtimer: add error handling to export APIs
  ARM: OMAP: dmtimer: low-power mode support
  ARM: OMAP: dmtimer: skip reserved timers
  ARM: OMAP: dmtimer: pm_runtime support
  ARM: OMAP: dmtimer: switch-over to platform device driver
  ARM: OMAP: dmtimer: platform driver
  ARM: OMAP2+: dmtimer: convert to platform devices
  ARM: OMAP1: dmtimer: conversion to platform devices
  ARM: OMAP2+: dmtimer: add device names to flck nodes
  ARM: OMAP: Add support for dmtimer v2 ip

5 files changed, 75 insertions, 29 deletions

diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 9fd00a6d4248..6bd2f451c185 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,7 @@
 #
 
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
-                                   id.o usb.o
+                                   id.o usb.o timer.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 252e8b3c5706..1405d0eb7edb 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,12 +10,12 @@
 #include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/mfd/db5500-prcmu.h>
+#include <linux/clksrc-dbx500-prcmu.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/localtimer.h>
 
-#include <plat/mtu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
@@ -50,30 +50,3 @@ void __init ux500_init_irq(void)
                 prcmu_early_init();
         clk_init();
 }
-
-static void __init ux500_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
-        /* Setup the local timer base */
-        if (cpu_is_u5500())
-                twd_base = __io_address(U5500_TWD_BASE);
-        else if (cpu_is_u8500())
-                twd_base = __io_address(U8500_TWD_BASE);
-        else
-                ux500_unknown_soc();
-#endif
-        if (cpu_is_u5500())
-                mtu_base = __io_address(U5500_MTU0_BASE);
-        else if (cpu_is_u8500ed())
-                mtu_base = __io_address(U8500_MTU0_BASE_ED);
-        else if (cpu_is_u8500())
-                mtu_base = __io_address(U8500_MTU0_BASE);
-        else
-                ux500_unknown_soc();
-
-        nmdk_timer_init();
-}
-
-struct sys_timer ux500_timer = {
-        .init   = ux500_timer_init,
-};
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 6ad983294103..994b5fe6f85a 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -61,6 +61,8 @@
 #define U5500_SCR_BASE          (U5500_PER4_BASE + 0x5000)
 #define U5500_DMC_BASE          (U5500_PER4_BASE + 0x6000)
 #define U5500_PRCMU_BASE        (U5500_PER4_BASE + 0x7000)
+#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
+#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
 #define U5500_MSP1_BASE         (U5500_PER4_BASE + 0x9000)
 #define U5500_GPIO2_BASE        (U5500_PER4_BASE + 0xA000)
 #define U5500_CDETECT_BASE      (U5500_PER4_BASE + 0xF000)
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 049997109cf9..751b0e6938d4 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -102,10 +102,13 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
+#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
 #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 
+
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
 #define U8500_SSP0_BASE         (U8500_PER3_BASE + 0x2000)
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
new file mode 100644
index 000000000000..aea467d04ff7
--- /dev/null
+++ b/arch/arm/mach-ux500/timer.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
+ */
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/clksrc-dbx500-prcmu.h>
+
+#include <asm/localtimer.h>
+
+#include <plat/mtu.h>
+
+#include <mach/setup.h>
+#include <mach/hardware.h>
+
+static void __init ux500_timer_init(void)
+{
+        void __iomem *prcmu_timer_base;
+
+        if (cpu_is_u5500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+                twd_base = __io_address(U5500_TWD_BASE);
+#endif
+                mtu_base = __io_address(U5500_MTU0_BASE);
+                prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
+        } else if (cpu_is_u8500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+                twd_base = __io_address(U8500_TWD_BASE);
+#endif
+                mtu_base = __io_address(U8500_MTU0_BASE);
+                prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
+        } else {
+                ux500_unknown_soc();
+        }
+
+        /*
+         * Here we register the timerblocks active in the system.
+         * Localtimers (twd) is started when both cpu is up and running.
+         * MTU register a clocksource, clockevent and sched_clock.
+         * Since the MTU is located in the VAPE power domain
+         * it will be cleared in sleep which makes it unsuitable.
+         * We however need it as a timer tick (clockevent)
+         * during boot to calibrate delay until twd is started.
+         * RTC-RTT have problems as timer tick during boot since it is
+         * depending on delay which is not yet calibrated. RTC-RTT is in the
+         * always-on powerdomain and is used as clockevent instead of twd when
+         * sleeping.
+         * The PRCMU timer 4(3 for DB5500) register a clocksource and
+         * sched_clock with higher rating then MTU since is always-on.
+         *
+         */
+
+        nmdk_timer_init();
+        clksrc_dbx500_prcmu_init(prcmu_timer_base);
+}
+
+static void ux500_timer_reset(void)
+{
+        nmdk_clkevt_reset();
+        nmdk_clksrc_reset();
+}
+
+struct sys_timer ux500_timer = {
+        .init           = ux500_timer_init,
+        .resume         = ux500_timer_reset,
+};