diff options
author | Mattias Wallin <mattias.wallin@stericsson.com> | 2011-05-27 04:30:34 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2011-09-22 09:43:20 -0400 |
commit | 7ed00af7a960031ad00017e3ebcf1d3ef22af498 (patch) | |
tree | e96b004167dcdb8a4c9643c5d2fc82139267c079 /arch/arm/mach-ux500 | |
parent | 489bccea6334514a8e13436f10d0a274777bf17a (diff) |
ARM: ux500: add support for clocksource DBX500 PRCMU
This patch adds support for the DBX500 PRCMU clocksource
to ux500 platforms.
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.co>
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r-- | arch/arm/mach-ux500/cpu.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/db5500-regs.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/db8500-regs.h | 3 |
3 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 1da23bb87c16..c0e4593f7719 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
@@ -10,6 +10,7 @@ | |||
10 | #include <linux/clk.h> | 10 | #include <linux/clk.h> |
11 | #include <linux/mfd/db8500-prcmu.h> | 11 | #include <linux/mfd/db8500-prcmu.h> |
12 | #include <linux/mfd/db5500-prcmu.h> | 12 | #include <linux/mfd/db5500-prcmu.h> |
13 | #include <linux/clksrc-dbx500-prcmu.h> | ||
13 | 14 | ||
14 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
15 | #include <asm/hardware/cache-l2x0.h> | 16 | #include <asm/hardware/cache-l2x0.h> |
@@ -140,7 +141,15 @@ static void __init ux500_timer_init(void) | |||
140 | else | 141 | else |
141 | ux500_unknown_soc(); | 142 | ux500_unknown_soc(); |
142 | 143 | ||
144 | if (cpu_is_u8500()) | ||
145 | clksrc_dbx500_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); | ||
146 | else if (cpu_is_u5500()) | ||
147 | clksrc_dbx500_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); | ||
148 | else | ||
149 | ux500_unknown_soc(); | ||
150 | |||
143 | nmdk_timer_init(); | 151 | nmdk_timer_init(); |
152 | clksrc_dbx500_prcmu_init(); | ||
144 | } | 153 | } |
145 | 154 | ||
146 | struct sys_timer ux500_timer = { | 155 | struct sys_timer ux500_timer = { |
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 6ad983294103..994b5fe6f85a 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h | |||
@@ -61,6 +61,8 @@ | |||
61 | #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) | 61 | #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) |
62 | #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) | 62 | #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) |
63 | #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) | 63 | #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) |
64 | #define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) | ||
65 | #define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) | ||
64 | #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) | 66 | #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) |
65 | #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) | 67 | #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) |
66 | #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) | 68 | #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) |
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 049997109cf9..751b0e6938d4 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h | |||
@@ -102,10 +102,13 @@ | |||
102 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) | 102 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) |
103 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) | 103 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) |
104 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) | 104 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) |
105 | #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) | ||
106 | #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) | ||
105 | #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) | 107 | #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) |
106 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) | 108 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) |
107 | #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) | 109 | #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) |
108 | 110 | ||
111 | |||
109 | /* per3 base addresses */ | 112 | /* per3 base addresses */ |
110 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) | 113 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) |
111 | #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) | 114 | #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) |