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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-25 18:35:03 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-25 18:35:03 -0400
commitad363e0916423b2e6cdfcdc30ae707ec709f0a65 (patch)
treec47cc9062f7adc0ceb27f634b63b8548b733f01c /arch/arm/mach-ux500
parented0795aa12129df9f3d2cc81ee579a9e54e12885 (diff)
parent1032fbfd792f2b384ac16a63993b8fae5eea9083 (diff)
Merge branch 'for-torvalds' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson
* 'for-torvalds' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: mach-ux500: voltage domain regulators for DB8500 cpufreq: make DB8500 cpufreq driver compile cpufreq: update DB8500 cpufreq driver mach-ux500: move CPUfreq driver to cpufreq subsystem mfd: add DB5500 PRCMU driver mfd: update DB8500 PRCMU driver mach-ux500: move the DB8500 PRCMU driver to MFD mach-ux500: make PRCMU base address dynamic mach-ux500: rename PRCMU driver per SoC mach-ux500: update ASIC version detection mach-ux500: update SoC and board IRQ handling mach-ux500: update the DB5500 register file mach-ux500: update the DB8500 register file
Diffstat (limited to 'arch/arm/mach-ux500')
-rw-r--r--arch/arm/mach-ux500/Kconfig3
-rw-r--r--arch/arm/mach-ux500/Makefile4
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c2
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c7
-rw-r--r--arch/arm/mach-ux500/cpu.c7
-rw-r--r--arch/arm/mach-ux500/cpufreq.c211
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h20
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h37
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/id.h20
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h5
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-u5500.h21
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h27
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db8500.h54
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h46
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-defs.h30
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-regs.h96
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu.h28
-rw-r--r--arch/arm/mach-ux500/prcmu.c394
19 files changed, 218 insertions, 795 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 58626013aa32..54429d015954 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -12,9 +12,12 @@ menu "Ux500 SoC"
12 12
13config UX500_SOC_DB5500 13config UX500_SOC_DB5500
14 bool "DB5500" 14 bool "DB5500"
15 select MFD_DB5500_PRCMU
15 16
16config UX500_SOC_DB8500 17config UX500_SOC_DB8500
17 bool "DB8500" 18 bool "DB8500"
19 select MFD_DB8500_PRCMU
20 select REGULATOR_DB8500_PRCMU
18 21
19endmenu 22endmenu
20 23
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index b549a8fb4231..1694916e6822 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,7 +5,7 @@
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := clock.o cpu.o devices.o devices-common.o \
6 id.o usb.o 6 id.o usb.o
7obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o 7obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o 8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
9obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ 9obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \
10 board-mop500-regulators.o \ 10 board-mop500-regulators.o \
11 board-mop500-uib.o board-mop500-stuib.o \ 11 board-mop500-uib.o board-mop500-stuib.o \
@@ -17,4 +17,4 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
17obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 17obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o 18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o
19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o 19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o
20obj-$(CONFIG_CPU_FREQ) += cpufreq.o 20
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index c9dc2eff3cb2..c01bc19e3c5e 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -188,6 +188,8 @@ void __init u5500_map_io(void)
188 ux500_map_io(); 188 ux500_map_io();
189 189
190 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); 190 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
191
192 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
191} 193}
192 194
193static int usb_db5500_rx_dma_cfg[] = { 195static int usb_db5500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 516126cb357d..c3c417656bd9 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -87,6 +87,8 @@ void __init u8500_map_io(void)
87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); 87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
88 else if (cpu_is_u8500v2()) 88 else if (cpu_is_u8500v2())
89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
90
91 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
90} 92}
91 93
92static struct resource db8500_pmu_resources[] = { 94static struct resource db8500_pmu_resources[] = {
@@ -129,9 +131,14 @@ static struct platform_device db8500_pmu_device = {
129 .dev.platform_data = &db8500_pmu_platdata, 131 .dev.platform_data = &db8500_pmu_platdata,
130}; 132};
131 133
134static struct platform_device db8500_prcmu_device = {
135 .name = "db8500-prcmu",
136};
137
132static struct platform_device *platform_devs[] __initdata = { 138static struct platform_device *platform_devs[] __initdata = {
133 &u8500_dma40_device, 139 &u8500_dma40_device,
134 &db8500_pmu_device, 140 &db8500_pmu_device,
141 &db8500_prcmu_device,
135}; 142};
136 143
137static resource_size_t __initdata db8500_gpio_base[] = { 144static resource_size_t __initdata db8500_gpio_base[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 5a43107c6232..1da23bb87c16 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,6 +8,8 @@
8#include <linux/platform_device.h> 8#include <linux/platform_device.h>
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/mfd/db8500-prcmu.h>
12#include <linux/mfd/db5500-prcmu.h>
11 13
12#include <asm/cacheflush.h> 14#include <asm/cacheflush.h>
13#include <asm/hardware/cache-l2x0.h> 15#include <asm/hardware/cache-l2x0.h>
@@ -19,10 +21,11 @@
19#include <mach/hardware.h> 21#include <mach/hardware.h>
20#include <mach/setup.h> 22#include <mach/setup.h>
21#include <mach/devices.h> 23#include <mach/devices.h>
22#include <mach/prcmu.h>
23 24
24#include "clock.h" 25#include "clock.h"
25 26
27void __iomem *_PRCMU_BASE;
28
26#ifdef CONFIG_CACHE_L2X0 29#ifdef CONFIG_CACHE_L2X0
27static void __iomem *l2x0_base; 30static void __iomem *l2x0_base;
28#endif 31#endif
@@ -47,6 +50,8 @@ void __init ux500_init_irq(void)
47 * Init clocks here so that they are available for system timer 50 * Init clocks here so that they are available for system timer
48 * initialization. 51 * initialization.
49 */ 52 */
53 if (cpu_is_u5500())
54 db5500_prcmu_early_init();
50 if (cpu_is_u8500()) 55 if (cpu_is_u8500())
51 prcmu_early_init(); 56 prcmu_early_init();
52 clk_init(); 57 clk_init();
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
deleted file mode 100644
index 5c5b747f134d..000000000000
--- a/arch/arm/mach-ux500/cpufreq.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * CPU frequency scaling for u8500
3 * Inspired by linux/arch/arm/mach-davinci/cpufreq.c
4 *
5 * Copyright (C) STMicroelectronics 2009
6 * Copyright (C) ST-Ericsson SA 2010
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
11 * Author: Martin Persson <martin.persson@stericsson.com>
12 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
13 *
14 */
15
16#include <linux/platform_device.h>
17#include <linux/kernel.h>
18#include <linux/cpufreq.h>
19#include <linux/delay.h>
20
21#include <mach/hardware.h>
22#include <mach/prcmu.h>
23#include <mach/prcmu-defs.h>
24
25#define DRIVER_NAME "cpufreq-u8500"
26#define CPUFREQ_NAME "u8500"
27
28static struct device *dev;
29
30static struct cpufreq_frequency_table freq_table[] = {
31 [0] = {
32 .index = 0,
33 .frequency = 200000,
34 },
35 [1] = {
36 .index = 1,
37 .frequency = 300000,
38 },
39 [2] = {
40 .index = 2,
41 .frequency = 600000,
42 },
43 [3] = {
44 /* Used for CPU_OPP_MAX, if available */
45 .index = 3,
46 .frequency = CPUFREQ_TABLE_END,
47 },
48 [4] = {
49 .index = 4,
50 .frequency = CPUFREQ_TABLE_END,
51 },
52};
53
54static enum prcmu_cpu_opp index2opp[] = {
55 CPU_OPP_EXT_CLK,
56 CPU_OPP_50,
57 CPU_OPP_100,
58 CPU_OPP_MAX
59};
60
61static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
62{
63 return cpufreq_frequency_table_verify(policy, freq_table);
64}
65
66static int u8500_cpufreq_target(struct cpufreq_policy *policy,
67 unsigned int target_freq,
68 unsigned int relation)
69{
70 struct cpufreq_freqs freqs;
71 unsigned int index;
72 int ret = 0;
73
74 /*
75 * Ensure desired rate is within allowed range. Some govenors
76 * (ondemand) will just pass target_freq=0 to get the minimum.
77 */
78 if (target_freq < policy->cpuinfo.min_freq)
79 target_freq = policy->cpuinfo.min_freq;
80 if (target_freq > policy->cpuinfo.max_freq)
81 target_freq = policy->cpuinfo.max_freq;
82
83 ret = cpufreq_frequency_table_target(policy, freq_table,
84 target_freq, relation, &index);
85 if (ret < 0) {
86 dev_err(dev, "Could not look up next frequency\n");
87 return ret;
88 }
89
90 freqs.old = policy->cur;
91 freqs.new = freq_table[index].frequency;
92 freqs.cpu = policy->cpu;
93
94 if (freqs.old == freqs.new) {
95 dev_dbg(dev, "Current and target frequencies are equal\n");
96 return 0;
97 }
98
99 dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new);
100 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
101
102 ret = prcmu_set_cpu_opp(index2opp[index]);
103 if (ret < 0) {
104 dev_err(dev, "Failed to set OPP level\n");
105 return ret;
106 }
107
108 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
109
110 return ret;
111}
112
113static unsigned int u8500_cpufreq_getspeed(unsigned int cpu)
114{
115 int i;
116
117 for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++)
118 ;
119 return freq_table[i].frequency;
120}
121
122static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
123{
124 int res;
125
126 BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table));
127
128 if (cpu_is_u8500v2()) {
129 freq_table[1].frequency = 400000;
130 freq_table[2].frequency = 800000;
131 if (prcmu_has_arm_maxopp())
132 freq_table[3].frequency = 1000000;
133 }
134
135 /* get policy fields based on the table */
136 res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
137 if (!res)
138 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
139 else {
140 dev_err(dev, "u8500-cpufreq : Failed to read policy table\n");
141 return res;
142 }
143
144 policy->min = policy->cpuinfo.min_freq;
145 policy->max = policy->cpuinfo.max_freq;
146 policy->cur = u8500_cpufreq_getspeed(policy->cpu);
147 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
148
149 /*
150 * FIXME : Need to take time measurement across the target()
151 * function with no/some/all drivers in the notification
152 * list.
153 */
154 policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
155
156 /* policy sharing between dual CPUs */
157 cpumask_copy(policy->cpus, &cpu_present_map);
158
159 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
160
161 return res;
162}
163
164static struct freq_attr *u8500_cpufreq_attr[] = {
165 &cpufreq_freq_attr_scaling_available_freqs,
166 NULL,
167};
168static int u8500_cpu_exit(struct cpufreq_policy *policy)
169{
170 cpufreq_frequency_table_put_attr(policy->cpu);
171 return 0;
172}
173
174static struct cpufreq_driver u8500_driver = {
175 .owner = THIS_MODULE,
176 .flags = CPUFREQ_STICKY,
177 .verify = u8500_cpufreq_verify_speed,
178 .target = u8500_cpufreq_target,
179 .get = u8500_cpufreq_getspeed,
180 .init = u8500_cpu_init,
181 .exit = u8500_cpu_exit,
182 .name = CPUFREQ_NAME,
183 .attr = u8500_cpufreq_attr,
184};
185
186static int __init u8500_cpufreq_probe(struct platform_device *pdev)
187{
188 dev = &pdev->dev;
189 return cpufreq_register_driver(&u8500_driver);
190}
191
192static int __exit u8500_cpufreq_remove(struct platform_device *pdev)
193{
194 return cpufreq_unregister_driver(&u8500_driver);
195}
196
197static struct platform_driver u8500_cpufreq_driver = {
198 .driver = {
199 .name = DRIVER_NAME,
200 .owner = THIS_MODULE,
201 },
202 .remove = __exit_p(u8500_cpufreq_remove),
203};
204
205static int __init u8500_cpufreq_init(void)
206{
207 return platform_driver_probe(&u8500_cpufreq_driver,
208 &u8500_cpufreq_probe);
209}
210
211device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index bd88c1e74060..6ad983294103 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -17,6 +17,8 @@
17#define U5500_GIC_DIST_BASE 0xA0411000 17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100 18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000 19#define U5500_DMA_BASE 0x90030000
20#define U5500_STM_BASE 0x90020000
21#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
20#define U5500_MCDE_BASE 0xA0400000 22#define U5500_MCDE_BASE 0xA0400000
21#define U5500_MODEM_BASE 0xB0000000 23#define U5500_MODEM_BASE 0xB0000000
22#define U5500_L2CC_BASE 0xA0412000 24#define U5500_L2CC_BASE 0xA0412000
@@ -29,7 +31,9 @@
29#define U5500_NAND0_BASE 0x60000000 31#define U5500_NAND0_BASE 0x60000000
30#define U5500_NAND1_BASE 0x70000000 32#define U5500_NAND1_BASE 0x70000000
31#define U5500_TWD_BASE 0xa0410600 33#define U5500_TWD_BASE 0xa0410600
34#define U5500_ICN_BASE 0xA0040000
32#define U5500_B2R2_BASE 0xa0200000 35#define U5500_B2R2_BASE 0xa0200000
36#define U5500_BOOT_ROM_BASE 0x90000000
33 37
34#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) 38#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
35#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) 39#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
@@ -60,6 +64,7 @@
60#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) 64#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
61#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) 65#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
62#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) 66#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
67#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
63 68
64#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) 69#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
65#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) 70#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
@@ -83,7 +88,7 @@
83#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) 88#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
84#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) 89#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
85#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) 90#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
86#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000) 91#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
87#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) 92#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
88#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) 93#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
89#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) 94#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
@@ -114,8 +119,19 @@
114#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) 119#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
115#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) 120#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
116 121
117#define U5500_ESRAM_BASE 0x40000000 122#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
123#define U5500_ACCCON_BASE (0xBFFF1000)
124#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
125#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
126
127#define U5500_ESRAM_BASE 0x40000000
118#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 128#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
119#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) 129#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
120 130
131#define U5500_MCDE_SIZE 0x1000
132#define U5500_DSI_LINK_SIZE 0x1000
133#define U5500_DSI_LINK_COUNT 0x2
134#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
135#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
136
121#endif 137#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 16647b255378..049997109cf9 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -15,8 +15,13 @@
15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) 15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) 16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) 17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
18/* Use bank 4 for DMA LCPA */ 18/*
19#define U8500_DMA_LCPA_BASE U8500_ESRAM_BANK4 19 * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
20 * reserved for security
21 */
22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
23
24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
20#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) 25#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000)
21 26
22#define U8500_PER3_BASE 0x80000000 27#define U8500_PER3_BASE 0x80000000
@@ -27,9 +32,12 @@
27#define U8500_B2R2_BASE 0x80130000 32#define U8500_B2R2_BASE 0x80130000
28#define U8500_HSEM_BASE 0x80140000 33#define U8500_HSEM_BASE 0x80140000
29#define U8500_PER4_BASE 0x80150000 34#define U8500_PER4_BASE 0x80150000
35#define U8500_TPIU_BASE 0x80190000
30#define U8500_ICN_BASE 0x81000000 36#define U8500_ICN_BASE 0x81000000
31 37
32#define U8500_BOOT_ROM_BASE 0x90000000 38#define U8500_BOOT_ROM_BASE 0x90000000
39/* ASIC ID is at 0xbf4 offset within this region */
40#define U8500_ASIC_ID_BASE 0x9001D000
33 41
34#define U8500_PER6_BASE 0xa03c0000 42#define U8500_PER6_BASE 0xa03c0000
35#define U8500_PER5_BASE 0xa03e0000 43#define U8500_PER5_BASE 0xa03e0000
@@ -70,13 +78,15 @@
70 78
71/* per6 base addresses */ 79/* per6 base addresses */
72#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) 80#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
73#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) 81#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
74#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) 82#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
83#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
84#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
75#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ 85#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
76#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ 86#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
77#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ 87#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
78#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) 88#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
79#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) 89#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
80#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) 90#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
81 91
82/* per5 base addresses */ 92/* per5 base addresses */
@@ -93,7 +103,8 @@
93#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) 103#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
94#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) 104#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
95#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) 105#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
96#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) 106#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
107#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
97 108
98/* per3 base addresses */ 109/* per3 base addresses */
99#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) 110#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
@@ -124,6 +135,7 @@
124#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) 135#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
125#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) 136#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
126#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) 137#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
138#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
127#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) 139#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
128#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) 140#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
129#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) 141#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
@@ -143,4 +155,15 @@
143#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) 155#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
144#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE 156#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
145 157
158#define U8500_MCDE_SIZE 0x1000
159#define U8500_DSI_LINK_SIZE 0x1000
160#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
161#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
162#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
163#define U8500_DSI_LINK_COUNT 0x3
164
165/* Modem and APE physical addresses */
166#define U8500_MODEM_BASE 0xe000000
167#define U8500_APE_BASE 0x6000000
168
146#endif 169#endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index bf63f2631ba0..2c6f71049f2e 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -35,6 +35,7 @@
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36 36
37#include <mach/id.h> 37#include <mach/id.h>
38extern void __iomem *_PRCMU_BASE;
38 39
39#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) 40#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
40 41
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index f1288d10b6ab..02b541a37ee5 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -75,6 +75,26 @@ static inline bool __attribute_const__ cpu_is_u8500v2(void)
75 return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0); 75 return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0);
76} 76}
77 77
78static inline bool cpu_is_u8500v20(void)
79{
80 return cpu_is_u8500() && (dbx500_revision() == 0xB0);
81}
82
83static inline bool cpu_is_u8500v21(void)
84{
85 return cpu_is_u8500() && (dbx500_revision() == 0xB1);
86}
87
88static inline bool cpu_is_u8500v20_or_later(void)
89{
90 return cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11();
91}
92
93static inline bool ux500_is_svp(void)
94{
95 return false;
96}
97
78#define ux500_unknown_soc() BUG() 98#define ux500_unknown_soc() BUG()
79 99
80#endif 100#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 97ef55f84934..47969909836c 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -50,6 +50,11 @@
50 50
51#define MOP500_IRQ_END MOP500_NR_IRQS 51#define MOP500_IRQ_END MOP500_NR_IRQS
52 52
53/*
54 * We may have several boards, but only one will run at a
55 * time, so the one with most IRQs will bump this ahead,
56 * but the IRQ_BOARD_START remains the same for either board.
57 */
53#if MOP500_IRQ_END > IRQ_BOARD_END 58#if MOP500_IRQ_END > IRQ_BOARD_END
54#undef IRQ_BOARD_END 59#undef IRQ_BOARD_END
55#define IRQ_BOARD_END MOP500_IRQ_END 60#define IRQ_BOARD_END MOP500_IRQ_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
new file mode 100644
index 000000000000..29d972c7717b
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_IRQS_BOARD_U5500_H
8#define __MACH_IRQS_BOARD_U5500_H
9
10#define AB5500_NR_IRQS 5
11#define IRQ_AB5500_BASE IRQ_BOARD_START
12#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
13
14#define U5500_IRQ_END IRQ_AB5500_END
15
16#if IRQ_BOARD_END < U5500_IRQ_END
17#undef IRQ_BOARD_END
18#define IRQ_BOARD_END U5500_IRQ_END
19#endif
20
21#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index bfa123dbec3b..77239776a6f2 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -83,4 +83,31 @@
83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) 83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) 84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
85 85
86#ifdef CONFIG_UX500_SOC_DB5500
87
88/*
89 * After the GPIO ones we reserve a range of IRQ:s in which virtual
90 * IRQ:s representing modem IRQ:s can be allocated
91 */
92#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
93#define IRQ_MODEM_EVENTS_NBR 72
94#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
95
96/* List of virtual IRQ:s that are allocated from the range above */
97#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
98#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
99#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
100
101/*
102 * We may have several SoCs, but only one will run at a
103 * time, so the one with most IRQs will bump this ahead,
104 * but the IRQ_SOC_START remains the same for either SoC.
105 */
106#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
107#undef IRQ_SOC_END
108#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
109#endif
110
111#endif /* CONFIG_UX500_SOC_DB5500 */
112
86#endif 113#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
index 8b5d9f0a1633..68bc14974608 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -93,4 +93,58 @@
93#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) 93#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
94#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) 94#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
95 95
96#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71)
97#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66)
98#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64)
99#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67)
100#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65)
101
102#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83)
103#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78)
104#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76)
105#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79)
106#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77)
107
108#ifdef CONFIG_UX500_SOC_DB8500
109
110/* Virtual interrupts corresponding to the PRCMU wakeups. */
111#define IRQ_PRCMU_BASE IRQ_SOC_START
112#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
113
114#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
115#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
116#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
117#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
118#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
119#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
120#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
121#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
122#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
123#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
124#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
125#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
126#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
127#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
128#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
129#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
130#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
131#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
132#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
133#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
134#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
135#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
136#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
137#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
138
139/*
140 * We may have several SoCs, but only one will run at a
141 * time, so the one with most IRQs will bump this ahead,
142 * but the IRQ_SOC_START remains the same for either SoC.
143 */
144#if IRQ_SOC_END < IRQ_PRCMU_END
145#undef IRQ_SOC_END
146#define IRQ_SOC_END IRQ_PRCMU_END
147#endif
148
149#endif /* CONFIG_UX500_SOC_DB8500 */
96#endif 150#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index ba1294c13c4d..9db68d264c5f 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,49 +10,47 @@
10#ifndef ASM_ARCH_IRQS_H 10#ifndef ASM_ARCH_IRQS_H
11#define ASM_ARCH_IRQS_H 11#define ASM_ARCH_IRQS_H
12 12
13#include <mach/irqs-db5500.h> 13#include <mach/hardware.h>
14#include <mach/irqs-db8500.h>
15 14
16#define IRQ_LOCALTIMER 29 15#define IRQ_LOCALTIMER 29
17#define IRQ_LOCALWDOG 30 16#define IRQ_LOCALWDOG 30
18 17
19/* Shared Peripheral Interrupt (SHPI) */ 18/* Shared Peripheral Interrupt (SHPI) */
20#define IRQ_SHPI_START 32 19#define IRQ_SHPI_START 32
21 20
22/* Interrupt numbers generic for shared peripheral */ 21/*
22 * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't
23 * add any other IRQs here, use the irqs-dbx500.h files.
24 */
23#define IRQ_MTU0 (IRQ_SHPI_START + 4) 25#define IRQ_MTU0 (IRQ_SHPI_START + 4)
24 26
25/* There are 128 shared peripheral interrupts assigned to 27#define DBX500_NR_INTERNAL_IRQS 160
26 * INTID[160:32]. The first 32 interrupts are reserved.
27 */
28#define DBX500_NR_INTERNAL_IRQS 161
29 28
30/* After chip-specific IRQ numbers we have the GPIO ones */ 29/* After chip-specific IRQ numbers we have the GPIO ones */
31#define NOMADIK_NR_GPIO 288 30#define NOMADIK_NR_GPIO 288
32#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) 31#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS)
33#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) 32#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS)
34#define IRQ_BOARD_START NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) 33#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
34
35#define IRQ_SOC_START IRQ_GPIO_END
36/* This will be overridden by SoC-specific irq headers */
37#define IRQ_SOC_END IRQ_SOC_START
35 38
39#include <mach/irqs-db5500.h>
40#include <mach/irqs-db8500.h>
41
42#define IRQ_BOARD_START IRQ_SOC_END
36/* This will be overridden by board-specific irq headers */ 43/* This will be overridden by board-specific irq headers */
37#define IRQ_BOARD_END IRQ_BOARD_START 44#define IRQ_BOARD_END IRQ_BOARD_START
38 45
39#ifdef CONFIG_MACH_U8500 46#ifdef CONFIG_MACH_U8500
40#include <mach/irqs-board-mop500.h> 47#include <mach/irqs-board-mop500.h>
41#endif 48#endif
42 49
43/* 50#ifdef CONFIG_MACH_U5500
44 * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual 51#include <mach/irqs-board-u5500.h>
45 * IRQ:s representing modem IRQ:s can be allocated 52#endif
46 */
47#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
48#define IRQ_MODEM_EVENTS_NBR 72
49#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
50
51/* List of virtual IRQ:s that are allocated from the range above */
52#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
53#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
54#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
55 53
56#define NR_IRQS IRQ_MODEM_EVENTS_END 54#define NR_IRQS IRQ_BOARD_END
57 55
58#endif /* ASM_ARCH_IRQS_H */ 56#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
deleted file mode 100644
index 848ba64b561f..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-defs.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
6 * Author: Martin Persson <martin.persson@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit definitions
11 */
12
13#ifndef __MACH_PRCMU_DEFS_H
14#define __MACH_PRCMU_DEFS_H
15
16enum prcmu_cpu_opp {
17 CPU_OPP_INIT = 0x00,
18 CPU_OPP_NO_CHANGE = 0x01,
19 CPU_OPP_100 = 0x02,
20 CPU_OPP_50 = 0x03,
21 CPU_OPP_MAX = 0x04,
22 CPU_OPP_EXT_CLK = 0x07
23};
24enum prcmu_ape_opp {
25 APE_OPP_NO_CHANGE = 0x00,
26 APE_OPP_100 = 0x02,
27 APE_OPP_50 = 0x03,
28};
29
30#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
deleted file mode 100644
index 455467e88791..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit registers
11 */
12
13#ifndef __MACH_PRCMU_REGS_H
14#define __MACH_PRCMU_REGS_H
15
16#include <mach/hardware.h>
17
18#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
19
20#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
21#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
22#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
23#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
24#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
25#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
26#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
27#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
28
29/* ARM WFI Standby signal register */
30#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
31#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
32
33/* CPU mailbox registers */
34#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
35#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
36#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
37
38/* Dual A9 core interrupt management unit registers */
39#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
40#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
41#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
42#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
43#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
44#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
45#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
46#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
47#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
48#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
49#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
50
51#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
52#define ARM_WAKEUP_MODEM 0x1
53
54#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
55#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
56#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
57
58#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
59#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
60#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
61#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
62#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
63#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
64#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
65#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
66
67/* System reset register */
68#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
69
70/* Level shifter and clamp control registers */
71#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
72#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
73
74/* PRCMU clock/PLL/reset registers */
75#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
76#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
77#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
78#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
79#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
80#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
81#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
82#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
83#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
84#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
85
86/* ePOD and memory power signal control registers */
87#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
88#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
89
90/* Debug power control unit registers */
91#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
92
93/* Miscellaneous unit registers */
94#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
95
96#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
deleted file mode 100644
index c49e456162ef..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
8 *
9 * License Terms: GNU General Public License v2
10 *
11 * PRCM Unit f/w API
12 */
13#ifndef __MACH_PRCMU_H
14#define __MACH_PRCMU_H
15#include <mach/prcmu-defs.h>
16
17void __init prcmu_early_init(void);
18int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
19int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
20int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
21int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
22int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
23 enum prcmu_cpu_opp cpu_opp);
24int prcmu_get_ape_opp(void);
25int prcmu_get_cpu_opp(void);
26bool prcmu_has_arm_maxopp(void);
27
28#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
deleted file mode 100644
index c522d26ef348..000000000000
--- a/arch/arm/mach-ux500/prcmu.c
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
10 * U8500 PRCM Unit interface driver
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/mutex.h>
19#include <linux/completion.h>
20#include <linux/jiffies.h>
21#include <linux/bitops.h>
22#include <linux/interrupt.h>
23
24#include <mach/hardware.h>
25#include <mach/prcmu-regs.h>
26#include <mach/prcmu-defs.h>
27
28/* Global var to runtime determine TCDM base for v2 or v1 */
29static __iomem void *tcdm_base;
30
31#define _MBOX_HEADER (tcdm_base + 0xFE8)
32#define MBOX_HEADER_REQ_MB0 (_MBOX_HEADER + 0x0)
33
34#define REQ_MB1 (tcdm_base + 0xFD0)
35#define REQ_MB5 (tcdm_base + 0xE44)
36
37#define REQ_MB1_ARMOPP (REQ_MB1 + 0x0)
38#define REQ_MB1_APEOPP (REQ_MB1 + 0x1)
39#define REQ_MB1_BOOSTOPP (REQ_MB1 + 0x2)
40
41#define ACK_MB1 (tcdm_base + 0xE04)
42#define ACK_MB5 (tcdm_base + 0xDF4)
43
44#define ACK_MB1_CURR_ARMOPP (ACK_MB1 + 0x0)
45#define ACK_MB1_CURR_APEOPP (ACK_MB1 + 0x1)
46
47#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
48#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
49#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
50#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
51
52#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
53#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
54
55#define PRCM_AVS_VARM_MAX_OPP (tcdm_base + 0x2E4)
56#define PRCM_AVS_ISMODEENABLE 7
57#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
58
59#define I2C_WRITE(slave) \
60 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
61#define I2C_READ(slave) \
62 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
63#define I2C_STOP_EN BIT(3)
64
65enum mb1_h {
66 MB1H_ARM_OPP = 1,
67 MB1H_APE_OPP,
68 MB1H_ARM_APE_OPP,
69};
70
71static struct {
72 struct mutex lock;
73 struct completion work;
74 struct {
75 u8 arm_opp;
76 u8 ape_opp;
77 u8 arm_status;
78 u8 ape_status;
79 } ack;
80} mb1_transfer;
81
82enum ack_mb5_status {
83 I2C_WR_OK = 0x01,
84 I2C_RD_OK = 0x02,
85};
86
87#define MBOX_BIT BIT
88#define NUM_MBOX 8
89
90static struct {
91 struct mutex lock;
92 struct completion work;
93 bool failed;
94 struct {
95 u8 status;
96 u8 value;
97 } ack;
98} mb5_transfer;
99
100/**
101 * prcmu_abb_read() - Read register value(s) from the ABB.
102 * @slave: The I2C slave address.
103 * @reg: The (start) register address.
104 * @value: The read out value(s).
105 * @size: The number of registers to read.
106 *
107 * Reads register value(s) from the ABB.
108 * @size has to be 1 for the current firmware version.
109 */
110int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
111{
112 int r;
113
114 if (size != 1)
115 return -EINVAL;
116
117 r = mutex_lock_interruptible(&mb5_transfer.lock);
118 if (r)
119 return r;
120
121 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
122 cpu_relax();
123
124 writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
125 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
126 writeb(reg, REQ_MB5_I2C_REG);
127
128 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
129 if (!wait_for_completion_timeout(&mb5_transfer.work,
130 msecs_to_jiffies(500))) {
131 pr_err("prcmu: prcmu_abb_read timed out.\n");
132 r = -EIO;
133 goto unlock_and_return;
134 }
135 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
136 if (!r)
137 *value = mb5_transfer.ack.value;
138
139unlock_and_return:
140 mutex_unlock(&mb5_transfer.lock);
141 return r;
142}
143EXPORT_SYMBOL(prcmu_abb_read);
144
145/**
146 * prcmu_abb_write() - Write register value(s) to the ABB.
147 * @slave: The I2C slave address.
148 * @reg: The (start) register address.
149 * @value: The value(s) to write.
150 * @size: The number of registers to write.
151 *
152 * Reads register value(s) from the ABB.
153 * @size has to be 1 for the current firmware version.
154 */
155int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
156{
157 int r;
158
159 if (size != 1)
160 return -EINVAL;
161
162 r = mutex_lock_interruptible(&mb5_transfer.lock);
163 if (r)
164 return r;
165
166
167 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
168 cpu_relax();
169
170 writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
171 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
172 writeb(reg, REQ_MB5_I2C_REG);
173 writeb(*value, REQ_MB5_I2C_VAL);
174
175 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
176 if (!wait_for_completion_timeout(&mb5_transfer.work,
177 msecs_to_jiffies(500))) {
178 pr_err("prcmu: prcmu_abb_write timed out.\n");
179 r = -EIO;
180 goto unlock_and_return;
181 }
182 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
183
184unlock_and_return:
185 mutex_unlock(&mb5_transfer.lock);
186 return r;
187}
188EXPORT_SYMBOL(prcmu_abb_write);
189
190static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
191 enum prcmu_cpu_opp cpu_opp)
192{
193 bool do_ape;
194 bool do_arm;
195 int err = 0;
196
197 do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
198 do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
199
200 mutex_lock(&mb1_transfer.lock);
201
202 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
203 cpu_relax();
204
205 writeb(0, MBOX_HEADER_REQ_MB0);
206 writeb(cpu_opp, REQ_MB1_ARMOPP);
207 writeb(ape_opp, REQ_MB1_APEOPP);
208 writeb(0, REQ_MB1_BOOSTOPP);
209 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
210 wait_for_completion(&mb1_transfer.work);
211 if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
212 err = -EIO;
213 if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
214 err = -EIO;
215
216 mutex_unlock(&mb1_transfer.lock);
217
218 return err;
219}
220
221/**
222 * prcmu_set_ape_opp() - Set the OPP of the APE.
223 * @opp: The OPP to set.
224 *
225 * This function sets the OPP of the APE.
226 */
227int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
228{
229 return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
230}
231EXPORT_SYMBOL(prcmu_set_ape_opp);
232
233/**
234 * prcmu_set_cpu_opp() - Set the OPP of the CPU.
235 * @opp: The OPP to set.
236 *
237 * This function sets the OPP of the CPU.
238 */
239int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
240{
241 return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
242}
243EXPORT_SYMBOL(prcmu_set_cpu_opp);
244
245/**
246 * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
247 * @ape_opp: The APE OPP to set.
248 * @cpu_opp: The CPU OPP to set.
249 *
250 * This function sets the OPPs of the APE and the CPU.
251 */
252int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
253 enum prcmu_cpu_opp cpu_opp)
254{
255 return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
256}
257EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
258
259/**
260 * prcmu_get_ape_opp() - Get the OPP of the APE.
261 *
262 * This function gets the OPP of the APE.
263 */
264enum prcmu_ape_opp prcmu_get_ape_opp(void)
265{
266 return readb(ACK_MB1_CURR_APEOPP);
267}
268EXPORT_SYMBOL(prcmu_get_ape_opp);
269
270/**
271 * prcmu_get_cpu_opp() - Get the OPP of the CPU.
272 *
273 * This function gets the OPP of the CPU. The OPP is specified in %%.
274 * PRCMU_OPP_EXT is a special OPP value, not specified in %%.
275 */
276int prcmu_get_cpu_opp(void)
277{
278 return readb(ACK_MB1_CURR_ARMOPP);
279}
280EXPORT_SYMBOL(prcmu_get_cpu_opp);
281
282bool prcmu_has_arm_maxopp(void)
283{
284 return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
285 == PRCM_AVS_ISMODEENABLE_MASK;
286}
287
288static void read_mailbox_0(void)
289{
290 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
291}
292
293static void read_mailbox_1(void)
294{
295 mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
296 mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
297 complete(&mb1_transfer.work);
298 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
299}
300
301static void read_mailbox_2(void)
302{
303 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
304}
305
306static void read_mailbox_3(void)
307{
308 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
309}
310
311static void read_mailbox_4(void)
312{
313 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
314}
315
316static void read_mailbox_5(void)
317{
318 mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
319 mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
320 complete(&mb5_transfer.work);
321 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
322}
323
324static void read_mailbox_6(void)
325{
326 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
327}
328
329static void read_mailbox_7(void)
330{
331 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
332}
333
334static void (* const read_mailbox[NUM_MBOX])(void) = {
335 read_mailbox_0,
336 read_mailbox_1,
337 read_mailbox_2,
338 read_mailbox_3,
339 read_mailbox_4,
340 read_mailbox_5,
341 read_mailbox_6,
342 read_mailbox_7
343};
344
345static irqreturn_t prcmu_irq_handler(int irq, void *data)
346{
347 u32 bits;
348 u8 n;
349
350 bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
351 if (unlikely(!bits))
352 return IRQ_NONE;
353
354 for (n = 0; bits; n++) {
355 if (bits & MBOX_BIT(n)) {
356 bits -= MBOX_BIT(n);
357 read_mailbox[n]();
358 }
359 }
360 return IRQ_HANDLED;
361}
362
363void __init prcmu_early_init(void)
364{
365 if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
366 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
367 } else if (cpu_is_u8500v2()) {
368 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
369 } else {
370 pr_err("prcmu: Unsupported chip version\n");
371 BUG();
372 }
373}
374
375static int __init prcmu_init(void)
376{
377 if (cpu_is_u8500ed()) {
378 pr_err("prcmu: Unsupported chip version\n");
379 return 0;
380 }
381
382 mutex_init(&mb1_transfer.lock);
383 init_completion(&mb1_transfer.work);
384 mutex_init(&mb5_transfer.lock);
385 init_completion(&mb5_transfer.work);
386
387 /* Clean up the mailbox interrupts after pre-kernel code. */
388 writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
389
390 return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
391 "prcmu", NULL);
392}
393
394arch_initcall(prcmu_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 16:18:28 -0500