diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2013-03-19 10:41:55 -0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-04-08 07:59:28 -0400 |
| commit | 174e7796624d2749359c3fdc673c1232b060d7f6 (patch) | |
| tree | b72c821e4c7aa32765fe0509d0ccd00c9c2b68d1 /arch/arm/mach-ux500/include/mach/db8500-regs.h | |
| parent | e5a1f68203e4dab8fdbb4c7d20977e6a5dbc7a49 (diff) | |
ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
This removes <mach/hardware.h> and <mach/db8500-regs.h>
from the Ux500, merging them into the local include
"db8500-regs.h" in mach-ux500. There is some impact
outside the ux500 machine, but most of it is dealt with
in earlier patches.
Contains portions of a clean-up patch from Arnd Bergmann.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500/include/mach/db8500-regs.h')
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/db8500-regs.h | 173 |
1 files changed, 0 insertions, 173 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h deleted file mode 100644 index 1530d493879d..000000000000 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ /dev/null | |||
| @@ -1,173 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * License terms: GNU General Public License (GPL) version 2 | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __MACH_DB8500_REGS_H | ||
| 8 | #define __MACH_DB8500_REGS_H | ||
| 9 | |||
| 10 | /* Base address and bank offsets for ESRAM */ | ||
| 11 | #define U8500_ESRAM_BASE 0x40000000 | ||
| 12 | #define U8500_ESRAM_BANK_SIZE 0x00020000 | ||
| 13 | #define U8500_ESRAM_BANK0 U8500_ESRAM_BASE | ||
| 14 | #define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) | ||
| 15 | #define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) | ||
| 16 | #define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) | ||
| 17 | #define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) | ||
| 18 | /* | ||
| 19 | * on V1 DMA uses 4KB for logical parameters position is right after the 64KB | ||
| 20 | * reserved for security | ||
| 21 | */ | ||
| 22 | #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 | ||
| 23 | |||
| 24 | #define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) | ||
| 25 | |||
| 26 | /* This address fulfills the 256k alignment requirement of the lcla base */ | ||
| 27 | #define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 | ||
| 28 | |||
| 29 | #define U8500_PER3_BASE 0x80000000 | ||
| 30 | #define U8500_STM_BASE 0x80100000 | ||
| 31 | #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) | ||
| 32 | #define U8500_PER2_BASE 0x80110000 | ||
| 33 | #define U8500_PER1_BASE 0x80120000 | ||
| 34 | #define U8500_B2R2_BASE 0x80130000 | ||
| 35 | #define U8500_HSEM_BASE 0x80140000 | ||
| 36 | #define U8500_PER4_BASE 0x80150000 | ||
| 37 | #define U8500_TPIU_BASE 0x80190000 | ||
| 38 | #define U8500_ICN_BASE 0x81000000 | ||
| 39 | |||
| 40 | #define U8500_BOOT_ROM_BASE 0x90000000 | ||
| 41 | /* ASIC ID is at 0xbf4 offset within this region */ | ||
| 42 | #define U8500_ASIC_ID_BASE 0x9001D000 | ||
| 43 | |||
| 44 | #define U9540_BOOT_ROM_BASE 0xFFFE0000 | ||
| 45 | /* ASIC ID is at 0xbf4 offset within this region */ | ||
| 46 | #define U9540_ASIC_ID_BASE 0xFFFFD000 | ||
| 47 | |||
| 48 | #define U8500_PER6_BASE 0xa03c0000 | ||
| 49 | #define U8500_PER7_BASE 0xa03d0000 | ||
| 50 | #define U8500_PER5_BASE 0xa03e0000 | ||
| 51 | |||
| 52 | #define U8500_SVA_BASE 0xa0100000 | ||
| 53 | #define U8500_SIA_BASE 0xa0200000 | ||
| 54 | |||
| 55 | #define U8500_SGA_BASE 0xa0300000 | ||
| 56 | #define U8500_MCDE_BASE 0xa0350000 | ||
| 57 | #define U8500_DMA_BASE 0x801C0000 /* v1 */ | ||
| 58 | |||
| 59 | #define U8500_SBAG_BASE 0xa0390000 | ||
| 60 | |||
| 61 | #define U8500_SCU_BASE 0xa0410000 | ||
| 62 | #define U8500_GIC_CPU_BASE 0xa0410100 | ||
| 63 | #define U8500_TWD_BASE 0xa0410600 | ||
| 64 | #define U8500_GIC_DIST_BASE 0xa0411000 | ||
| 65 | #define U8500_L2CC_BASE 0xa0412000 | ||
| 66 | |||
| 67 | #define U8500_MODEM_I2C 0xb7e02000 | ||
| 68 | |||
| 69 | #define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) | ||
| 70 | #define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) | ||
| 71 | #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) | ||
| 72 | #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) | ||
| 73 | |||
| 74 | #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) | ||
| 75 | #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) | ||
| 76 | |||
| 77 | /* per6 base addresses */ | ||
| 78 | #define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) | ||
| 79 | #define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000) | ||
| 80 | #define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000) | ||
| 81 | #define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000) | ||
| 82 | #define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100) | ||
| 83 | #define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ | ||
| 84 | #define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ | ||
| 85 | #define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ | ||
| 86 | #define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000) | ||
| 87 | #define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000) | ||
| 88 | #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) | ||
| 89 | |||
| 90 | /* per5 base addresses */ | ||
| 91 | #define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) | ||
| 92 | #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) | ||
| 93 | |||
| 94 | /* per4 base addresses */ | ||
| 95 | #define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) | ||
| 96 | #define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) | ||
| 97 | #define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) | ||
| 98 | #define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) | ||
| 99 | #define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) | ||
| 100 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) | ||
| 101 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) | ||
| 102 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) | ||
| 103 | #define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000) | ||
| 104 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) | ||
| 105 | #define U9540_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x6A000) | ||
| 106 | #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) | ||
| 107 | #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) | ||
| 108 | #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) | ||
| 109 | |||
| 110 | /* per3 base addresses */ | ||
| 111 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) | ||
| 112 | #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) | ||
| 113 | #define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) | ||
| 114 | #define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) | ||
| 115 | #define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) | ||
| 116 | #define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) | ||
| 117 | #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) | ||
| 118 | #define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) | ||
| 119 | #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) | ||
| 120 | |||
| 121 | /* per2 base addresses */ | ||
| 122 | #define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) | ||
| 123 | #define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) | ||
| 124 | #define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) | ||
| 125 | #define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) | ||
| 126 | #define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) | ||
| 127 | #define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) | ||
| 128 | #define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) | ||
| 129 | #define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) | ||
| 130 | #define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) | ||
| 131 | #define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) | ||
| 132 | #define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) | ||
| 133 | #define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) | ||
| 134 | |||
| 135 | /* per1 base addresses */ | ||
| 136 | #define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) | ||
| 137 | #define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) | ||
| 138 | #define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) | ||
| 139 | #define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000) | ||
| 140 | #define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) | ||
| 141 | #define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) | ||
| 142 | #define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) | ||
| 143 | #define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) | ||
| 144 | #define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) | ||
| 145 | #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) | ||
| 146 | |||
| 147 | #define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 | ||
| 148 | |||
| 149 | #define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE | ||
| 150 | #define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) | ||
| 151 | #define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE | ||
| 152 | #define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) | ||
| 153 | #define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) | ||
| 154 | #define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) | ||
| 155 | #define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE | ||
| 156 | #define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) | ||
| 157 | #define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE | ||
| 158 | |||
| 159 | #define U8500_MCDE_SIZE 0x1000 | ||
| 160 | #define U8500_DSI_LINK_SIZE 0x1000 | ||
| 161 | #define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE) | ||
| 162 | #define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) | ||
| 163 | #define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) | ||
| 164 | #define U8500_DSI_LINK_COUNT 0x3 | ||
| 165 | |||
| 166 | /* Modem and APE physical addresses */ | ||
| 167 | #define U8500_MODEM_BASE 0xe000000 | ||
| 168 | #define U8500_APE_BASE 0x6000000 | ||
| 169 | |||
| 170 | /* SoC identification number information */ | ||
| 171 | #define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0) | ||
| 172 | |||
| 173 | #endif | ||