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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-10 00:00:07 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-10 00:00:07 -0400
commitdcded10f6dce10411b16134ce9cc87bfdf75c13f (patch)
treeda6d0face147072c9eadc8a01af4e49958769138 /arch/arm/mach-ux500/devices-db8500.c
parent9e0ba741aabdf129d561e62d207c75146adef5e8 (diff)
parentb0ebeb9c09cb5b84bb2f33927c84c7648845fcec (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (30 commits) DMAENGINE: at_hdmac: locking fixlet DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l dma: dmatest: fix potential sign bug ioat2: catch and recover from broken vtd configurations v6 DMAENGINE: add runtime slave control to COH 901 318 v3 DMAENGINE: add runtime slave config to DMA40 v3 DMAENGINE: generic slave channel control v3 dmaengine: Driver for Topcliff PCH DMA controller intel_mid: Add Mrst & Mfld DMA Drivers drivers/dma: Eliminate a NULL pointer dereference dma/timb_dma: compile warning on 32 bit DMAENGINE: ste_dma40: support older silicon DMAENGINE: ste_dma40: support disabling physical channels DMAENGINE: ste_dma40: no disabled phy channels on ux500 DMAENGINE: ste_dma40: fix suspend bug DMAENGINE: ste_dma40: add DB8500 memcpy channels DMAENGINE: ste_dma40: no flow control on memcpy DMAENGINE: ste_dma40: arch updates for LCLA and LCPA DMAENGINE: ste_dma40: allocate LCLA dynamically DMAENGINE: ste_dma40: no premature stop ... Fix up trivial conflicts in arch/arm/mach-ux500/devices-db8500.c
Diffstat (limited to 'arch/arm/mach-ux500/devices-db8500.c')
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c28
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 654fca944e65..9280d2561111 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -113,26 +113,21 @@ struct platform_device u8500_i2c4_device = {
113static struct resource dma40_resources[] = { 113static struct resource dma40_resources[] = {
114 [0] = { 114 [0] = {
115 .start = U8500_DMA_BASE, 115 .start = U8500_DMA_BASE,
116 .end = U8500_DMA_BASE + SZ_4K - 1, 116 .end = U8500_DMA_BASE + SZ_4K - 1,
117 .flags = IORESOURCE_MEM, 117 .flags = IORESOURCE_MEM,
118 .name = "base", 118 .name = "base",
119 }, 119 },
120 [1] = { 120 [1] = {
121 .start = U8500_DMA_LCPA_BASE, 121 .start = U8500_DMA_LCPA_BASE,
122 .end = U8500_DMA_LCPA_BASE + SZ_4K - 1, 122 .end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
123 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
124 .name = "lcpa", 124 .name = "lcpa",
125 }, 125 },
126 [2] = { 126 [2] = {
127 .start = U8500_DMA_LCLA_BASE,
128 .end = U8500_DMA_LCLA_BASE + 16 * 1024 - 1,
129 .flags = IORESOURCE_MEM,
130 .name = "lcla",
131 },
132 [3] = {
133 .start = IRQ_DB8500_DMA, 127 .start = IRQ_DB8500_DMA,
134 .end = IRQ_DB8500_DMA, 128 .end = IRQ_DB8500_DMA,
135 .flags = IORESOURCE_IRQ} 129 .flags = IORESOURCE_IRQ,
130 }
136}; 131};
137 132
138/* Default configuration for physcial memcpy */ 133/* Default configuration for physcial memcpy */
@@ -145,11 +140,12 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
145 .src_info.endianess = STEDMA40_LITTLE_ENDIAN, 140 .src_info.endianess = STEDMA40_LITTLE_ENDIAN,
146 .src_info.data_width = STEDMA40_BYTE_WIDTH, 141 .src_info.data_width = STEDMA40_BYTE_WIDTH,
147 .src_info.psize = STEDMA40_PSIZE_PHY_1, 142 .src_info.psize = STEDMA40_PSIZE_PHY_1,
143 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
148 144
149 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, 145 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
150 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 146 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
151 .dst_info.psize = STEDMA40_PSIZE_PHY_1, 147 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
152 148 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
153}; 149};
154/* Default configuration for logical memcpy */ 150/* Default configuration for logical memcpy */
155struct stedma40_chan_cfg dma40_memcpy_conf_log = { 151struct stedma40_chan_cfg dma40_memcpy_conf_log = {
@@ -162,11 +158,12 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
162 .src_info.endianess = STEDMA40_LITTLE_ENDIAN, 158 .src_info.endianess = STEDMA40_LITTLE_ENDIAN,
163 .src_info.data_width = STEDMA40_BYTE_WIDTH, 159 .src_info.data_width = STEDMA40_BYTE_WIDTH,
164 .src_info.psize = STEDMA40_PSIZE_LOG_1, 160 .src_info.psize = STEDMA40_PSIZE_LOG_1,
161 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
165 162
166 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, 163 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
167 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 164 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
168 .dst_info.psize = STEDMA40_PSIZE_LOG_1, 165 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
169 166 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
170}; 167};
171 168
172/* 169/*
@@ -180,10 +177,12 @@ static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV];
180 177
181/* Reserved event lines for memcpy only */ 178/* Reserved event lines for memcpy only */
182static int dma40_memcpy_event[] = { 179static int dma40_memcpy_event[] = {
180 STEDMA40_MEMCPY_TX_0,
183 STEDMA40_MEMCPY_TX_1, 181 STEDMA40_MEMCPY_TX_1,
184 STEDMA40_MEMCPY_TX_2, 182 STEDMA40_MEMCPY_TX_2,
185 STEDMA40_MEMCPY_TX_3, 183 STEDMA40_MEMCPY_TX_3,
186 STEDMA40_MEMCPY_TX_4, 184 STEDMA40_MEMCPY_TX_4,
185 STEDMA40_MEMCPY_TX_5,
187}; 186};
188 187
189static struct stedma40_platform_data dma40_plat_data = { 188static struct stedma40_platform_data dma40_plat_data = {
@@ -195,6 +194,7 @@ static struct stedma40_platform_data dma40_plat_data = {
195 .memcpy_conf_phy = &dma40_memcpy_conf_phy, 194 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
196 .memcpy_conf_log = &dma40_memcpy_conf_log, 195 .memcpy_conf_log = &dma40_memcpy_conf_log,
197 .llis_per_log = 8, 196 .llis_per_log = 8,
197 .disabled_channels = {-1},
198}; 198};
199 199
200struct platform_device u8500_dma40_device = { 200struct platform_device u8500_dma40_device = {
@@ -213,4 +213,6 @@ void dma40_u8500ed_fixup(void)
213 dma40_plat_data.memcpy_len = 0; 213 dma40_plat_data.memcpy_len = 0;
214 dma40_resources[0].start = U8500_DMA_BASE_ED; 214 dma40_resources[0].start = U8500_DMA_BASE_ED;
215 dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; 215 dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
216 dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;
217 dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;
216} 218}