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authorIngo Molnar <mingo@elte.hu>2010-12-08 14:15:26 -0500
committerIngo Molnar <mingo@elte.hu>2010-12-08 14:15:29 -0500
commit8e9255e6a2141e050d51bc4d96dbef494a87d653 (patch)
treef190b142830153eaab05555a93c4f71a144ba3d4 /arch/arm/mach-ux500/cpu.c
parent5091faa449ee0b7d73bc296a93bca9540fc51d0a (diff)
parent6313e3c21743cc88bb5bd8aa72948ee1e83937b6 (diff)
Merge branch 'linus' into sched/core
Merge reason: we want to queue up dependent cleanup Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mach-ux500/cpu.c')
-rw-r--r--arch/arm/mach-ux500/cpu.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 73fb1a551ec6..608a1372b172 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -75,14 +75,14 @@ void __init ux500_init_irq(void)
75static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) 75static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
76{ 76{
77 /* wait for the operation to complete */ 77 /* wait for the operation to complete */
78 while (readl(reg) & mask) 78 while (readl_relaxed(reg) & mask)
79 ; 79 ;
80} 80}
81 81
82static inline void ux500_cache_sync(void) 82static inline void ux500_cache_sync(void)
83{ 83{
84 void __iomem *base = __io_address(UX500_L2CC_BASE); 84 void __iomem *base = __io_address(UX500_L2CC_BASE);
85 writel(0, base + L2X0_CACHE_SYNC); 85 writel_relaxed(0, base + L2X0_CACHE_SYNC);
86 ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); 86 ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
87} 87}
88 88
@@ -107,7 +107,7 @@ static void ux500_l2x0_inv_all(void)
107 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ 107 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
108 108
109 /* invalidate all ways */ 109 /* invalidate all ways */
110 writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); 110 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
111 ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); 111 ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
112 ux500_cache_sync(); 112 ux500_cache_sync();
113} 113}