ARM: l2c: ux500: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 13 deletions

diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 067c37a054fb..5b891d051054 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -45,8 +45,6 @@ static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
 
 static int __init ux500_l2x0_init(void)
 {
-        u32 aux_val = 0x3e000000;
-
         if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 l2x0_base = __io_address(U8500_L2CC_BASE);
         else
@@ -56,21 +54,12 @@ static int __init ux500_l2x0_init(void)
         /* Unlock before init */
         ux500_l2x0_unlock();
 
-        /* DBx540's L2 has 128KB way size */
-        if (cpu_is_ux540_family())
-                /* 128KB way size */
-                aux_val |= L2C_AUX_CTRL_WAY_SIZE(4);
-        else
-                /* 64KB way size */
-                aux_val |= L2C_AUX_CTRL_WAY_SIZE(3);
-
         outer_cache.write_sec = ux500_l2c310_write_sec;
 
-        /* 64KB way size, 8 way associativity, force WA */
         if (of_have_populated_dt())
-                l2x0_of_init(aux_val, 0xc0000fff);
+                l2x0_of_init(0x3e000000, 0xc00f0fff);
         else
-                l2x0_init(l2x0_base, aux_val, 0xc0000fff);
+                l2x0_init(l2x0_base, 0x3e000000, 0xc00f0fff);
 
         return 0;
 }