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authorLee Jones <lee.jones@linaro.org>2013-05-03 10:31:56 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-05-23 15:11:51 -0400
commit26955c07dcf3c36b6427e52fec0f725300ca079e (patch)
treeeb6a3ff98566809292403701019bdf1a42e151f1 /arch/arm/mach-ux500/board-mop500.c
parent4f8fc46c797015dddc1d4c76e1b485b57373683b (diff)
dmaengine: ste_dma40: Amalgamate DMA source and destination channel numbers
Devices which utilise DMA use the same device numbers for transmitting and receiving. In this patch we encode the source and destination information into one single attribute. We can subsequently exploit the direction attribute to see which of the transfer directions are being described. This also lessens the burden on platform data. Cc: Dan Williams <djbw@fb.com> Cc: Per Forlin <per.forlin@stericsson.com> Cc: Rabin Vincent <rabin@rab.in> Acked-by: Vinod Koul <vinod.koul@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500/board-mop500.c')
-rw-r--r--arch/arm/mach-ux500/board-mop500.c33
1 files changed, 11 insertions, 22 deletions
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 3cd555ac6d0a..871e61517fb2 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -425,8 +425,7 @@ void mop500_snowball_ethernet_clock_enable(void)
425static struct cryp_platform_data u8500_cryp1_platform_data = { 425static struct cryp_platform_data u8500_cryp1_platform_data = {
426 .mem_to_engine = { 426 .mem_to_engine = {
427 .dir = STEDMA40_MEM_TO_PERIPH, 427 .dir = STEDMA40_MEM_TO_PERIPH,
428 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 428 .dev_type = DB8500_DMA_DEV48_CAC1,
429 .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
430 .src_info.data_width = STEDMA40_WORD_WIDTH, 429 .src_info.data_width = STEDMA40_WORD_WIDTH,
431 .dst_info.data_width = STEDMA40_WORD_WIDTH, 430 .dst_info.data_width = STEDMA40_WORD_WIDTH,
432 .mode = STEDMA40_MODE_LOGICAL, 431 .mode = STEDMA40_MODE_LOGICAL,
@@ -435,8 +434,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
435 }, 434 },
436 .engine_to_mem = { 435 .engine_to_mem = {
437 .dir = STEDMA40_PERIPH_TO_MEM, 436 .dir = STEDMA40_PERIPH_TO_MEM,
438 .src_dev_type = DB8500_DMA_DEV48_CAC1_RX, 437 .dev_type = DB8500_DMA_DEV48_CAC1,
439 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
440 .src_info.data_width = STEDMA40_WORD_WIDTH, 438 .src_info.data_width = STEDMA40_WORD_WIDTH,
441 .dst_info.data_width = STEDMA40_WORD_WIDTH, 439 .dst_info.data_width = STEDMA40_WORD_WIDTH,
442 .mode = STEDMA40_MODE_LOGICAL, 440 .mode = STEDMA40_MODE_LOGICAL,
@@ -447,8 +445,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
447 445
448static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { 446static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
449 .dir = STEDMA40_MEM_TO_PERIPH, 447 .dir = STEDMA40_MEM_TO_PERIPH,
450 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 448 .dev_type = DB8500_DMA_DEV50_HAC1_TX,
451 .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
452 .src_info.data_width = STEDMA40_WORD_WIDTH, 449 .src_info.data_width = STEDMA40_WORD_WIDTH,
453 .dst_info.data_width = STEDMA40_WORD_WIDTH, 450 .dst_info.data_width = STEDMA40_WORD_WIDTH,
454 .mode = STEDMA40_MODE_LOGICAL, 451 .mode = STEDMA40_MODE_LOGICAL,
@@ -471,8 +468,7 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
471static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { 468static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
472 .mode = STEDMA40_MODE_LOGICAL, 469 .mode = STEDMA40_MODE_LOGICAL,
473 .dir = STEDMA40_PERIPH_TO_MEM, 470 .dir = STEDMA40_PERIPH_TO_MEM,
474 .src_dev_type = DB8500_DMA_DEV8_SSP0_RX, 471 .dev_type = DB8500_DMA_DEV8_SSP0,
475 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
476 .src_info.data_width = STEDMA40_BYTE_WIDTH, 472 .src_info.data_width = STEDMA40_BYTE_WIDTH,
477 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 473 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
478}; 474};
@@ -480,8 +476,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
480static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { 476static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
481 .mode = STEDMA40_MODE_LOGICAL, 477 .mode = STEDMA40_MODE_LOGICAL,
482 .dir = STEDMA40_MEM_TO_PERIPH, 478 .dir = STEDMA40_MEM_TO_PERIPH,
483 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 479 .dev_type = DB8500_DMA_DEV8_SSP0,
484 .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
485 .src_info.data_width = STEDMA40_BYTE_WIDTH, 480 .src_info.data_width = STEDMA40_BYTE_WIDTH,
486 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 481 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
487}; 482};
@@ -512,8 +507,7 @@ static void __init mop500_spi_init(struct device *parent)
512static struct stedma40_chan_cfg uart0_dma_cfg_rx = { 507static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
513 .mode = STEDMA40_MODE_LOGICAL, 508 .mode = STEDMA40_MODE_LOGICAL,
514 .dir = STEDMA40_PERIPH_TO_MEM, 509 .dir = STEDMA40_PERIPH_TO_MEM,
515 .src_dev_type = DB8500_DMA_DEV13_UART0_RX, 510 .dev_type = DB8500_DMA_DEV13_UART0,
516 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
517 .src_info.data_width = STEDMA40_BYTE_WIDTH, 511 .src_info.data_width = STEDMA40_BYTE_WIDTH,
518 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 512 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
519}; 513};
@@ -521,8 +515,7 @@ static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
521static struct stedma40_chan_cfg uart0_dma_cfg_tx = { 515static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
522 .mode = STEDMA40_MODE_LOGICAL, 516 .mode = STEDMA40_MODE_LOGICAL,
523 .dir = STEDMA40_MEM_TO_PERIPH, 517 .dir = STEDMA40_MEM_TO_PERIPH,
524 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 518 .dev_type = DB8500_DMA_DEV13_UART0,
525 .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
526 .src_info.data_width = STEDMA40_BYTE_WIDTH, 519 .src_info.data_width = STEDMA40_BYTE_WIDTH,
527 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 520 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
528}; 521};
@@ -530,8 +523,7 @@ static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
530static struct stedma40_chan_cfg uart1_dma_cfg_rx = { 523static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
531 .mode = STEDMA40_MODE_LOGICAL, 524 .mode = STEDMA40_MODE_LOGICAL,
532 .dir = STEDMA40_PERIPH_TO_MEM, 525 .dir = STEDMA40_PERIPH_TO_MEM,
533 .src_dev_type = DB8500_DMA_DEV12_UART1_RX, 526 .dev_type = DB8500_DMA_DEV12_UART1,
534 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
535 .src_info.data_width = STEDMA40_BYTE_WIDTH, 527 .src_info.data_width = STEDMA40_BYTE_WIDTH,
536 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 528 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
537}; 529};
@@ -539,8 +531,7 @@ static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
539static struct stedma40_chan_cfg uart1_dma_cfg_tx = { 531static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
540 .mode = STEDMA40_MODE_LOGICAL, 532 .mode = STEDMA40_MODE_LOGICAL,
541 .dir = STEDMA40_MEM_TO_PERIPH, 533 .dir = STEDMA40_MEM_TO_PERIPH,
542 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 534 .dev_type = DB8500_DMA_DEV12_UART1,
543 .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
544 .src_info.data_width = STEDMA40_BYTE_WIDTH, 535 .src_info.data_width = STEDMA40_BYTE_WIDTH,
545 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 536 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
546}; 537};
@@ -548,8 +539,7 @@ static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
548static struct stedma40_chan_cfg uart2_dma_cfg_rx = { 539static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
549 .mode = STEDMA40_MODE_LOGICAL, 540 .mode = STEDMA40_MODE_LOGICAL,
550 .dir = STEDMA40_PERIPH_TO_MEM, 541 .dir = STEDMA40_PERIPH_TO_MEM,
551 .src_dev_type = DB8500_DMA_DEV11_UART2_RX, 542 .dev_type = DB8500_DMA_DEV11_UART2,
552 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
553 .src_info.data_width = STEDMA40_BYTE_WIDTH, 543 .src_info.data_width = STEDMA40_BYTE_WIDTH,
554 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 544 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
555}; 545};
@@ -557,8 +547,7 @@ static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
557static struct stedma40_chan_cfg uart2_dma_cfg_tx = { 547static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
558 .mode = STEDMA40_MODE_LOGICAL, 548 .mode = STEDMA40_MODE_LOGICAL,
559 .dir = STEDMA40_MEM_TO_PERIPH, 549 .dir = STEDMA40_MEM_TO_PERIPH,
560 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 550 .dev_type = DB8500_DMA_DEV11_UART2,
561 .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
562 .src_info.data_width = STEDMA40_BYTE_WIDTH, 551 .src_info.data_width = STEDMA40_BYTE_WIDTH,
563 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 552 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
564}; 553};