mach-ux500: config Ux500 PL011 PL022 PL180 for DMA

This will configure the platform data for the PL011, PL022
and PL180 (derivate) PrimeCells found in the Ux500 to use DMA
with the generic DMA engine for DMA40.

Signed-off-by: Per Forlin <per.forlin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 122 insertions, 13 deletions

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 5babce497415..67d9c634c05d 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
+#include <linux/amba/serial.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
 #include <linux/mfd/tc3589x.h>
@@ -29,12 +30,14 @@
 
 #include <plat/pincfg.h>
 #include <plat/i2c.h>
+#include <plat/ste_dma40.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
 
+#include "ste-dma40-db8500.h"
 #include "devices-db8500.h"
 #include "pins-db8500.h"
 #include "board-mop500.h"
@@ -123,16 +126,6 @@ struct platform_device ab8500_device = {
         .resource = ab8500_resources,
 };
 
-static struct pl022_ssp_controller ssp0_platform_data = {
-        .bus_id = 0,
-        /* pl022 not yet supports dma */
-        .enable_dma = 0,
-        /* on this platform, gpio 31,142,144,214 &
-         * 224 are connected as chip selects
-         */
-        .num_chipselect = 5,
-};
-
 /*
  * TC35892
  */
@@ -319,16 +312,132 @@ static struct platform_device *platform_devs[] __initdata = {
         &mop500_gpio_keys_device,
 };
 
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct pl022_ssp_controller ssp0_platform_data = {
+        .bus_id = 0,
+#ifdef CONFIG_STE_DMA40
+        .enable_dma = 1,
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &ssp0_dma_cfg_rx,
+        .dma_tx_param = &ssp0_dma_cfg_tx,
+#else
+        .enable_dma = 0,
+#endif
+        /* on this platform, gpio 31,142,144,214 &
+         * 224 are connected as chip selects
+         */
+        .num_chipselect = 5,
+};
+
 static void __init mop500_spi_init(void)
 {
         db8500_add_ssp0(&ssp0_platform_data);
 }
 
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct amba_pl011_data uart0_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart0_dma_cfg_rx,
+        .dma_tx_param = &uart0_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart1_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart1_dma_cfg_rx,
+        .dma_tx_param = &uart1_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart2_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart2_dma_cfg_rx,
+        .dma_tx_param = &uart2_dma_cfg_tx,
+#endif
+};
+
 static void __init mop500_uart_init(void)
 {
-        db8500_add_uart0();
-        db8500_add_uart1();
-        db8500_add_uart2();
+        db8500_add_uart0(&uart0_plat);
+        db8500_add_uart1(&uart1_plat);
+        db8500_add_uart2(&uart2_plat);
 }
 
 static void __init u8500_init_machine(void)