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authorLinus Walleij <linus.walleij@stericsson.com>2009-12-17 03:46:24 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-01-27 17:00:15 -0500
commit08d1e2e68da977956ff10735148ac1de21c85afd (patch)
tree4d3c59ae89b79c92f390f26274a5b9350c402bc4 /arch/arm/mach-u300
parent74d2e4f8d79ae0c4b6ec027958d5b18058662eea (diff)
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300
This adds platform configuration for the COH 901 318 DMA driver for the U300 series mobile platforms. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-u300')
-rw-r--r--arch/arm/mach-u300/core.c1039
-rw-r--r--arch/arm/mach-u300/include/mach/dma_channels.h69
2 files changed, 1108 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 653e25be3dd8..068526a7ddac 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -19,6 +19,7 @@
19#include <linux/amba/bus.h> 19#include <linux/amba/bus.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <mach/coh901318.h>
22 23
23#include <asm/types.h> 24#include <asm/types.h>
24#include <asm/setup.h> 25#include <asm/setup.h>
@@ -29,6 +30,7 @@
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <mach/syscon.h> 32#include <mach/syscon.h>
33#include <mach/dma_channels.h>
32 34
33#include "clock.h" 35#include "clock.h"
34#include "mmc.h" 36#include "mmc.h"
@@ -372,6 +374,1031 @@ static struct resource ave_resources[] = {
372 }, 374 },
373}; 375};
374 376
377static struct resource dma_resource[] = {
378 {
379 .start = U300_DMAC_BASE,
380 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
381 .flags = IORESOURCE_MEM,
382 },
383 {
384 .start = IRQ_U300_DMA,
385 .end = IRQ_U300_DMA,
386 .flags = IORESOURCE_IRQ,
387 }
388};
389
390#ifdef CONFIG_MACH_U300_BS335
391/* points out all dma slave channels.
392 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
393 * Select all channels from A to B, end of list is marked with -1,-1
394 */
395static int dma_slave_channels[] = {
396 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
397 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
398
399/* points out all dma memcpy channels. */
400static int dma_memcpy_channels[] = {
401 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
402
403#else /* CONFIG_MACH_U300_BS335 */
404
405static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
406static int dma_memcpy_channels[] = {
407 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
408
409#endif
410
411/** register dma for memory access
412 *
413 * active 1 means dma intends to access memory
414 * 0 means dma wont access memory
415 */
416static void coh901318_access_memory_state(struct device *dev, bool active)
417{
418}
419
420#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
421 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
422 COH901318_CX_CFG_LCR_DISABLE | \
423 COH901318_CX_CFG_TC_IRQ_ENABLE | \
424 COH901318_CX_CFG_BE_IRQ_ENABLE)
425#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
426 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
427 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
428 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
429 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
430 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
431 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
432 COH901318_CX_CTRL_TCP_DISABLE | \
433 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
434 COH901318_CX_CTRL_HSP_DISABLE | \
435 COH901318_CX_CTRL_HSS_DISABLE | \
436 COH901318_CX_CTRL_DDMA_LEGACY | \
437 COH901318_CX_CTRL_PRDD_SOURCE)
438#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
443 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
444 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
445 COH901318_CX_CTRL_TCP_DISABLE | \
446 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
447 COH901318_CX_CTRL_HSP_DISABLE | \
448 COH901318_CX_CTRL_HSS_DISABLE | \
449 COH901318_CX_CTRL_DDMA_LEGACY | \
450 COH901318_CX_CTRL_PRDD_SOURCE)
451#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
452 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
453 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
454 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
455 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
456 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
457 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
458 COH901318_CX_CTRL_TCP_DISABLE | \
459 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
460 COH901318_CX_CTRL_HSP_DISABLE | \
461 COH901318_CX_CTRL_HSS_DISABLE | \
462 COH901318_CX_CTRL_DDMA_LEGACY | \
463 COH901318_CX_CTRL_PRDD_SOURCE)
464
465const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
466 {
467 .number = U300_DMA_MSL_TX_0,
468 .name = "MSL TX 0",
469 .priority_high = 0,
470 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
471 },
472 {
473 .number = U300_DMA_MSL_TX_1,
474 .name = "MSL TX 1",
475 .priority_high = 0,
476 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
477 .param.config = COH901318_CX_CFG_CH_DISABLE |
478 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
479 COH901318_CX_CFG_LCR_DISABLE |
480 COH901318_CX_CFG_TC_IRQ_ENABLE |
481 COH901318_CX_CFG_BE_IRQ_ENABLE,
482 .param.ctrl_lli_chained = 0 |
483 COH901318_CX_CTRL_TC_ENABLE |
484 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
485 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
486 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
487 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
488 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
489 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
490 COH901318_CX_CTRL_TCP_DISABLE |
491 COH901318_CX_CTRL_TC_IRQ_DISABLE |
492 COH901318_CX_CTRL_HSP_ENABLE |
493 COH901318_CX_CTRL_HSS_DISABLE |
494 COH901318_CX_CTRL_DDMA_LEGACY |
495 COH901318_CX_CTRL_PRDD_SOURCE,
496 .param.ctrl_lli = 0 |
497 COH901318_CX_CTRL_TC_ENABLE |
498 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
499 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
500 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
501 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
502 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
503 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
504 COH901318_CX_CTRL_TCP_ENABLE |
505 COH901318_CX_CTRL_TC_IRQ_DISABLE |
506 COH901318_CX_CTRL_HSP_ENABLE |
507 COH901318_CX_CTRL_HSS_DISABLE |
508 COH901318_CX_CTRL_DDMA_LEGACY |
509 COH901318_CX_CTRL_PRDD_SOURCE,
510 .param.ctrl_lli_last = 0 |
511 COH901318_CX_CTRL_TC_ENABLE |
512 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
513 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
514 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
515 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
516 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
517 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
518 COH901318_CX_CTRL_TCP_ENABLE |
519 COH901318_CX_CTRL_TC_IRQ_ENABLE |
520 COH901318_CX_CTRL_HSP_ENABLE |
521 COH901318_CX_CTRL_HSS_DISABLE |
522 COH901318_CX_CTRL_DDMA_LEGACY |
523 COH901318_CX_CTRL_PRDD_SOURCE,
524 },
525 {
526 .number = U300_DMA_MSL_TX_2,
527 .name = "MSL TX 2",
528 .priority_high = 0,
529 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
530 .param.config = COH901318_CX_CFG_CH_DISABLE |
531 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
532 COH901318_CX_CFG_LCR_DISABLE |
533 COH901318_CX_CFG_TC_IRQ_ENABLE |
534 COH901318_CX_CFG_BE_IRQ_ENABLE,
535 .param.ctrl_lli_chained = 0 |
536 COH901318_CX_CTRL_TC_ENABLE |
537 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
538 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
539 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
540 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
541 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
542 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
543 COH901318_CX_CTRL_TCP_DISABLE |
544 COH901318_CX_CTRL_TC_IRQ_DISABLE |
545 COH901318_CX_CTRL_HSP_ENABLE |
546 COH901318_CX_CTRL_HSS_DISABLE |
547 COH901318_CX_CTRL_DDMA_LEGACY |
548 COH901318_CX_CTRL_PRDD_SOURCE,
549 .param.ctrl_lli = 0 |
550 COH901318_CX_CTRL_TC_ENABLE |
551 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
552 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
553 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
554 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
555 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
556 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
557 COH901318_CX_CTRL_TCP_ENABLE |
558 COH901318_CX_CTRL_TC_IRQ_DISABLE |
559 COH901318_CX_CTRL_HSP_ENABLE |
560 COH901318_CX_CTRL_HSS_DISABLE |
561 COH901318_CX_CTRL_DDMA_LEGACY |
562 COH901318_CX_CTRL_PRDD_SOURCE,
563 .param.ctrl_lli_last = 0 |
564 COH901318_CX_CTRL_TC_ENABLE |
565 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
566 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
567 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
568 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
569 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
570 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
571 COH901318_CX_CTRL_TCP_ENABLE |
572 COH901318_CX_CTRL_TC_IRQ_ENABLE |
573 COH901318_CX_CTRL_HSP_ENABLE |
574 COH901318_CX_CTRL_HSS_DISABLE |
575 COH901318_CX_CTRL_DDMA_LEGACY |
576 COH901318_CX_CTRL_PRDD_SOURCE,
577 .desc_nbr_max = 10,
578 },
579 {
580 .number = U300_DMA_MSL_TX_3,
581 .name = "MSL TX 3",
582 .priority_high = 0,
583 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
584 .param.config = COH901318_CX_CFG_CH_DISABLE |
585 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
586 COH901318_CX_CFG_LCR_DISABLE |
587 COH901318_CX_CFG_TC_IRQ_ENABLE |
588 COH901318_CX_CFG_BE_IRQ_ENABLE,
589 .param.ctrl_lli_chained = 0 |
590 COH901318_CX_CTRL_TC_ENABLE |
591 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
592 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
593 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
594 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
595 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
596 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
597 COH901318_CX_CTRL_TCP_DISABLE |
598 COH901318_CX_CTRL_TC_IRQ_DISABLE |
599 COH901318_CX_CTRL_HSP_ENABLE |
600 COH901318_CX_CTRL_HSS_DISABLE |
601 COH901318_CX_CTRL_DDMA_LEGACY |
602 COH901318_CX_CTRL_PRDD_SOURCE,
603 .param.ctrl_lli = 0 |
604 COH901318_CX_CTRL_TC_ENABLE |
605 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
606 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
607 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
608 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
609 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
610 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
611 COH901318_CX_CTRL_TCP_ENABLE |
612 COH901318_CX_CTRL_TC_IRQ_DISABLE |
613 COH901318_CX_CTRL_HSP_ENABLE |
614 COH901318_CX_CTRL_HSS_DISABLE |
615 COH901318_CX_CTRL_DDMA_LEGACY |
616 COH901318_CX_CTRL_PRDD_SOURCE,
617 .param.ctrl_lli_last = 0 |
618 COH901318_CX_CTRL_TC_ENABLE |
619 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
620 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
621 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
622 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
623 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
624 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
625 COH901318_CX_CTRL_TCP_ENABLE |
626 COH901318_CX_CTRL_TC_IRQ_ENABLE |
627 COH901318_CX_CTRL_HSP_ENABLE |
628 COH901318_CX_CTRL_HSS_DISABLE |
629 COH901318_CX_CTRL_DDMA_LEGACY |
630 COH901318_CX_CTRL_PRDD_SOURCE,
631 },
632 {
633 .number = U300_DMA_MSL_TX_4,
634 .name = "MSL TX 4",
635 .priority_high = 0,
636 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
637 .param.config = COH901318_CX_CFG_CH_DISABLE |
638 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
639 COH901318_CX_CFG_LCR_DISABLE |
640 COH901318_CX_CFG_TC_IRQ_ENABLE |
641 COH901318_CX_CFG_BE_IRQ_ENABLE,
642 .param.ctrl_lli_chained = 0 |
643 COH901318_CX_CTRL_TC_ENABLE |
644 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
645 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
646 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
647 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
648 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
649 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
650 COH901318_CX_CTRL_TCP_DISABLE |
651 COH901318_CX_CTRL_TC_IRQ_DISABLE |
652 COH901318_CX_CTRL_HSP_ENABLE |
653 COH901318_CX_CTRL_HSS_DISABLE |
654 COH901318_CX_CTRL_DDMA_LEGACY |
655 COH901318_CX_CTRL_PRDD_SOURCE,
656 .param.ctrl_lli = 0 |
657 COH901318_CX_CTRL_TC_ENABLE |
658 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
659 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
661 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
662 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
663 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
664 COH901318_CX_CTRL_TCP_ENABLE |
665 COH901318_CX_CTRL_TC_IRQ_DISABLE |
666 COH901318_CX_CTRL_HSP_ENABLE |
667 COH901318_CX_CTRL_HSS_DISABLE |
668 COH901318_CX_CTRL_DDMA_LEGACY |
669 COH901318_CX_CTRL_PRDD_SOURCE,
670 .param.ctrl_lli_last = 0 |
671 COH901318_CX_CTRL_TC_ENABLE |
672 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
673 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
674 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
675 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
676 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
677 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
678 COH901318_CX_CTRL_TCP_ENABLE |
679 COH901318_CX_CTRL_TC_IRQ_ENABLE |
680 COH901318_CX_CTRL_HSP_ENABLE |
681 COH901318_CX_CTRL_HSS_DISABLE |
682 COH901318_CX_CTRL_DDMA_LEGACY |
683 COH901318_CX_CTRL_PRDD_SOURCE,
684 },
685 {
686 .number = U300_DMA_MSL_TX_5,
687 .name = "MSL TX 5",
688 .priority_high = 0,
689 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
690 },
691 {
692 .number = U300_DMA_MSL_TX_6,
693 .name = "MSL TX 6",
694 .priority_high = 0,
695 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
696 },
697 {
698 .number = U300_DMA_MSL_RX_0,
699 .name = "MSL RX 0",
700 .priority_high = 0,
701 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
702 },
703 {
704 .number = U300_DMA_MSL_RX_1,
705 .name = "MSL RX 1",
706 .priority_high = 0,
707 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
708 .param.config = COH901318_CX_CFG_CH_DISABLE |
709 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
710 COH901318_CX_CFG_LCR_DISABLE |
711 COH901318_CX_CFG_TC_IRQ_ENABLE |
712 COH901318_CX_CFG_BE_IRQ_ENABLE,
713 .param.ctrl_lli_chained = 0 |
714 COH901318_CX_CTRL_TC_ENABLE |
715 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
716 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
717 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
718 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
719 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
720 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
721 COH901318_CX_CTRL_TCP_DISABLE |
722 COH901318_CX_CTRL_TC_IRQ_DISABLE |
723 COH901318_CX_CTRL_HSP_ENABLE |
724 COH901318_CX_CTRL_HSS_DISABLE |
725 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
726 COH901318_CX_CTRL_PRDD_DEST,
727 .param.ctrl_lli = 0,
728 .param.ctrl_lli_last = 0 |
729 COH901318_CX_CTRL_TC_ENABLE |
730 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
731 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
732 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
733 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
734 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
735 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
736 COH901318_CX_CTRL_TCP_DISABLE |
737 COH901318_CX_CTRL_TC_IRQ_ENABLE |
738 COH901318_CX_CTRL_HSP_ENABLE |
739 COH901318_CX_CTRL_HSS_DISABLE |
740 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
741 COH901318_CX_CTRL_PRDD_DEST,
742 },
743 {
744 .number = U300_DMA_MSL_RX_2,
745 .name = "MSL RX 2",
746 .priority_high = 0,
747 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
748 .param.config = COH901318_CX_CFG_CH_DISABLE |
749 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
750 COH901318_CX_CFG_LCR_DISABLE |
751 COH901318_CX_CFG_TC_IRQ_ENABLE |
752 COH901318_CX_CFG_BE_IRQ_ENABLE,
753 .param.ctrl_lli_chained = 0 |
754 COH901318_CX_CTRL_TC_ENABLE |
755 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
756 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
757 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
758 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
759 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
760 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
761 COH901318_CX_CTRL_TCP_DISABLE |
762 COH901318_CX_CTRL_TC_IRQ_DISABLE |
763 COH901318_CX_CTRL_HSP_ENABLE |
764 COH901318_CX_CTRL_HSS_DISABLE |
765 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
766 COH901318_CX_CTRL_PRDD_DEST,
767 .param.ctrl_lli = 0 |
768 COH901318_CX_CTRL_TC_ENABLE |
769 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
770 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
771 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
772 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
773 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
774 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
775 COH901318_CX_CTRL_TCP_DISABLE |
776 COH901318_CX_CTRL_TC_IRQ_ENABLE |
777 COH901318_CX_CTRL_HSP_ENABLE |
778 COH901318_CX_CTRL_HSS_DISABLE |
779 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
780 COH901318_CX_CTRL_PRDD_DEST,
781 .param.ctrl_lli_last = 0 |
782 COH901318_CX_CTRL_TC_ENABLE |
783 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
784 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
785 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
786 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
787 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
788 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
789 COH901318_CX_CTRL_TCP_DISABLE |
790 COH901318_CX_CTRL_TC_IRQ_ENABLE |
791 COH901318_CX_CTRL_HSP_ENABLE |
792 COH901318_CX_CTRL_HSS_DISABLE |
793 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
794 COH901318_CX_CTRL_PRDD_DEST,
795 },
796 {
797 .number = U300_DMA_MSL_RX_3,
798 .name = "MSL RX 3",
799 .priority_high = 0,
800 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
801 .param.config = COH901318_CX_CFG_CH_DISABLE |
802 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
803 COH901318_CX_CFG_LCR_DISABLE |
804 COH901318_CX_CFG_TC_IRQ_ENABLE |
805 COH901318_CX_CFG_BE_IRQ_ENABLE,
806 .param.ctrl_lli_chained = 0 |
807 COH901318_CX_CTRL_TC_ENABLE |
808 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
809 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
810 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
811 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
812 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
813 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
814 COH901318_CX_CTRL_TCP_DISABLE |
815 COH901318_CX_CTRL_TC_IRQ_DISABLE |
816 COH901318_CX_CTRL_HSP_ENABLE |
817 COH901318_CX_CTRL_HSS_DISABLE |
818 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
819 COH901318_CX_CTRL_PRDD_DEST,
820 .param.ctrl_lli = 0 |
821 COH901318_CX_CTRL_TC_ENABLE |
822 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
823 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
824 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
825 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
826 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
827 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
828 COH901318_CX_CTRL_TCP_DISABLE |
829 COH901318_CX_CTRL_TC_IRQ_ENABLE |
830 COH901318_CX_CTRL_HSP_ENABLE |
831 COH901318_CX_CTRL_HSS_DISABLE |
832 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
833 COH901318_CX_CTRL_PRDD_DEST,
834 .param.ctrl_lli_last = 0 |
835 COH901318_CX_CTRL_TC_ENABLE |
836 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
837 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
838 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
839 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
840 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
841 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
842 COH901318_CX_CTRL_TCP_DISABLE |
843 COH901318_CX_CTRL_TC_IRQ_ENABLE |
844 COH901318_CX_CTRL_HSP_ENABLE |
845 COH901318_CX_CTRL_HSS_DISABLE |
846 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
847 COH901318_CX_CTRL_PRDD_DEST,
848 },
849 {
850 .number = U300_DMA_MSL_RX_4,
851 .name = "MSL RX 4",
852 .priority_high = 0,
853 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
854 .param.config = COH901318_CX_CFG_CH_DISABLE |
855 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
856 COH901318_CX_CFG_LCR_DISABLE |
857 COH901318_CX_CFG_TC_IRQ_ENABLE |
858 COH901318_CX_CFG_BE_IRQ_ENABLE,
859 .param.ctrl_lli_chained = 0 |
860 COH901318_CX_CTRL_TC_ENABLE |
861 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
862 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
863 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
864 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
865 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
866 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
867 COH901318_CX_CTRL_TCP_DISABLE |
868 COH901318_CX_CTRL_TC_IRQ_DISABLE |
869 COH901318_CX_CTRL_HSP_ENABLE |
870 COH901318_CX_CTRL_HSS_DISABLE |
871 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
872 COH901318_CX_CTRL_PRDD_DEST,
873 .param.ctrl_lli = 0 |
874 COH901318_CX_CTRL_TC_ENABLE |
875 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
876 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
877 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
878 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
879 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
880 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
881 COH901318_CX_CTRL_TCP_DISABLE |
882 COH901318_CX_CTRL_TC_IRQ_ENABLE |
883 COH901318_CX_CTRL_HSP_ENABLE |
884 COH901318_CX_CTRL_HSS_DISABLE |
885 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
886 COH901318_CX_CTRL_PRDD_DEST,
887 .param.ctrl_lli_last = 0 |
888 COH901318_CX_CTRL_TC_ENABLE |
889 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
890 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
891 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
892 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
893 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
894 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
895 COH901318_CX_CTRL_TCP_DISABLE |
896 COH901318_CX_CTRL_TC_IRQ_ENABLE |
897 COH901318_CX_CTRL_HSP_ENABLE |
898 COH901318_CX_CTRL_HSS_DISABLE |
899 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
900 COH901318_CX_CTRL_PRDD_DEST,
901 },
902 {
903 .number = U300_DMA_MSL_RX_5,
904 .name = "MSL RX 5",
905 .priority_high = 0,
906 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
907 .param.config = COH901318_CX_CFG_CH_DISABLE |
908 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
909 COH901318_CX_CFG_LCR_DISABLE |
910 COH901318_CX_CFG_TC_IRQ_ENABLE |
911 COH901318_CX_CFG_BE_IRQ_ENABLE,
912 .param.ctrl_lli_chained = 0 |
913 COH901318_CX_CTRL_TC_ENABLE |
914 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
915 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
916 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
917 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
918 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
919 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
920 COH901318_CX_CTRL_TCP_DISABLE |
921 COH901318_CX_CTRL_TC_IRQ_DISABLE |
922 COH901318_CX_CTRL_HSP_ENABLE |
923 COH901318_CX_CTRL_HSS_DISABLE |
924 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
925 COH901318_CX_CTRL_PRDD_DEST,
926 .param.ctrl_lli = 0 |
927 COH901318_CX_CTRL_TC_ENABLE |
928 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
929 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
930 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
931 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
932 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
933 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
934 COH901318_CX_CTRL_TCP_DISABLE |
935 COH901318_CX_CTRL_TC_IRQ_ENABLE |
936 COH901318_CX_CTRL_HSP_ENABLE |
937 COH901318_CX_CTRL_HSS_DISABLE |
938 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
939 COH901318_CX_CTRL_PRDD_DEST,
940 .param.ctrl_lli_last = 0 |
941 COH901318_CX_CTRL_TC_ENABLE |
942 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
943 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
944 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
945 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
946 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
947 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
948 COH901318_CX_CTRL_TCP_DISABLE |
949 COH901318_CX_CTRL_TC_IRQ_ENABLE |
950 COH901318_CX_CTRL_HSP_ENABLE |
951 COH901318_CX_CTRL_HSS_DISABLE |
952 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
953 COH901318_CX_CTRL_PRDD_DEST,
954 },
955 {
956 .number = U300_DMA_MSL_RX_6,
957 .name = "MSL RX 6",
958 .priority_high = 0,
959 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
960 },
961 {
962 .number = U300_DMA_MMCSD_RX_TX,
963 .name = "MMCSD RX TX",
964 .priority_high = 0,
965 .dev_addr = U300_MMCSD_BASE + 0x080,
966 .param.config = COH901318_CX_CFG_CH_DISABLE |
967 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
968 COH901318_CX_CFG_LCR_DISABLE |
969 COH901318_CX_CFG_TC_IRQ_ENABLE |
970 COH901318_CX_CFG_BE_IRQ_ENABLE,
971 .param.ctrl_lli_chained = 0 |
972 COH901318_CX_CTRL_TC_ENABLE |
973 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
974 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
975 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
976 COH901318_CX_CTRL_MASTER_MODE_M1RW |
977 COH901318_CX_CTRL_TCP_DISABLE |
978 COH901318_CX_CTRL_TC_IRQ_DISABLE |
979 COH901318_CX_CTRL_HSP_ENABLE |
980 COH901318_CX_CTRL_HSS_DISABLE |
981 COH901318_CX_CTRL_DDMA_LEGACY,
982 .param.ctrl_lli = 0 |
983 COH901318_CX_CTRL_TC_ENABLE |
984 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
985 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
986 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_MASTER_MODE_M1RW |
988 COH901318_CX_CTRL_TCP_ENABLE |
989 COH901318_CX_CTRL_TC_IRQ_DISABLE |
990 COH901318_CX_CTRL_HSP_ENABLE |
991 COH901318_CX_CTRL_HSS_DISABLE |
992 COH901318_CX_CTRL_DDMA_LEGACY,
993 .param.ctrl_lli_last = 0 |
994 COH901318_CX_CTRL_TC_ENABLE |
995 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
996 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
997 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
998 COH901318_CX_CTRL_MASTER_MODE_M1RW |
999 COH901318_CX_CTRL_TCP_ENABLE |
1000 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1001 COH901318_CX_CTRL_HSP_ENABLE |
1002 COH901318_CX_CTRL_HSS_DISABLE |
1003 COH901318_CX_CTRL_DDMA_LEGACY,
1004
1005 },
1006 {
1007 .number = U300_DMA_MSPRO_TX,
1008 .name = "MSPRO TX",
1009 .priority_high = 0,
1010 },
1011 {
1012 .number = U300_DMA_MSPRO_RX,
1013 .name = "MSPRO RX",
1014 .priority_high = 0,
1015 },
1016 {
1017 .number = U300_DMA_UART0_TX,
1018 .name = "UART0 TX",
1019 .priority_high = 0,
1020 },
1021 {
1022 .number = U300_DMA_UART0_RX,
1023 .name = "UART0 RX",
1024 .priority_high = 0,
1025 },
1026 {
1027 .number = U300_DMA_APEX_TX,
1028 .name = "APEX TX",
1029 .priority_high = 0,
1030 },
1031 {
1032 .number = U300_DMA_APEX_RX,
1033 .name = "APEX RX",
1034 .priority_high = 0,
1035 },
1036 {
1037 .number = U300_DMA_PCM_I2S0_TX,
1038 .name = "PCM I2S0 TX",
1039 .priority_high = 1,
1040 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1041 .param.config = COH901318_CX_CFG_CH_DISABLE |
1042 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
1043 COH901318_CX_CFG_LCR_DISABLE |
1044 COH901318_CX_CFG_TC_IRQ_ENABLE |
1045 COH901318_CX_CFG_BE_IRQ_ENABLE,
1046 .param.ctrl_lli_chained = 0 |
1047 COH901318_CX_CTRL_TC_ENABLE |
1048 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1049 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1050 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1051 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1052 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1053 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1054 COH901318_CX_CTRL_TCP_DISABLE |
1055 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1056 COH901318_CX_CTRL_HSP_ENABLE |
1057 COH901318_CX_CTRL_HSS_DISABLE |
1058 COH901318_CX_CTRL_DDMA_LEGACY |
1059 COH901318_CX_CTRL_PRDD_SOURCE,
1060 .param.ctrl_lli = 0 |
1061 COH901318_CX_CTRL_TC_ENABLE |
1062 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1063 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1064 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1065 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1066 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1067 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1068 COH901318_CX_CTRL_TCP_ENABLE |
1069 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1070 COH901318_CX_CTRL_HSP_ENABLE |
1071 COH901318_CX_CTRL_HSS_DISABLE |
1072 COH901318_CX_CTRL_DDMA_LEGACY |
1073 COH901318_CX_CTRL_PRDD_SOURCE,
1074 .param.ctrl_lli_last = 0 |
1075 COH901318_CX_CTRL_TC_ENABLE |
1076 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1077 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1078 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1079 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1080 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_ENABLE |
1083 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY |
1087 COH901318_CX_CTRL_PRDD_SOURCE,
1088 },
1089 {
1090 .number = U300_DMA_PCM_I2S0_RX,
1091 .name = "PCM I2S0 RX",
1092 .priority_high = 1,
1093 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1094 .param.config = COH901318_CX_CFG_CH_DISABLE |
1095 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
1096 COH901318_CX_CFG_LCR_DISABLE |
1097 COH901318_CX_CFG_TC_IRQ_ENABLE |
1098 COH901318_CX_CFG_BE_IRQ_ENABLE,
1099 .param.ctrl_lli_chained = 0 |
1100 COH901318_CX_CTRL_TC_ENABLE |
1101 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1102 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1103 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1104 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1105 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1106 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1107 COH901318_CX_CTRL_TCP_DISABLE |
1108 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1109 COH901318_CX_CTRL_HSP_ENABLE |
1110 COH901318_CX_CTRL_HSS_DISABLE |
1111 COH901318_CX_CTRL_DDMA_LEGACY |
1112 COH901318_CX_CTRL_PRDD_DEST,
1113 .param.ctrl_lli = 0 |
1114 COH901318_CX_CTRL_TC_ENABLE |
1115 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1116 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1117 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1118 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1119 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1120 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1121 COH901318_CX_CTRL_TCP_ENABLE |
1122 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1123 COH901318_CX_CTRL_HSP_ENABLE |
1124 COH901318_CX_CTRL_HSS_DISABLE |
1125 COH901318_CX_CTRL_DDMA_LEGACY |
1126 COH901318_CX_CTRL_PRDD_DEST,
1127 .param.ctrl_lli_last = 0 |
1128 COH901318_CX_CTRL_TC_ENABLE |
1129 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1130 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1131 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1132 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1133 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1134 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135 COH901318_CX_CTRL_TCP_ENABLE |
1136 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1137 COH901318_CX_CTRL_HSP_ENABLE |
1138 COH901318_CX_CTRL_HSS_DISABLE |
1139 COH901318_CX_CTRL_DDMA_LEGACY |
1140 COH901318_CX_CTRL_PRDD_DEST,
1141 },
1142 {
1143 .number = U300_DMA_PCM_I2S1_TX,
1144 .name = "PCM I2S1 TX",
1145 .priority_high = 1,
1146 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1147 .param.config = COH901318_CX_CFG_CH_DISABLE |
1148 COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
1149 COH901318_CX_CFG_LCR_DISABLE |
1150 COH901318_CX_CFG_TC_IRQ_ENABLE |
1151 COH901318_CX_CFG_BE_IRQ_ENABLE,
1152 .param.ctrl_lli_chained = 0 |
1153 COH901318_CX_CTRL_TC_ENABLE |
1154 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1155 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1156 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1157 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1158 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1159 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1160 COH901318_CX_CTRL_TCP_DISABLE |
1161 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1162 COH901318_CX_CTRL_HSP_ENABLE |
1163 COH901318_CX_CTRL_HSS_DISABLE |
1164 COH901318_CX_CTRL_DDMA_LEGACY |
1165 COH901318_CX_CTRL_PRDD_SOURCE,
1166 .param.ctrl_lli = 0 |
1167 COH901318_CX_CTRL_TC_ENABLE |
1168 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1169 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1170 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1171 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1172 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1173 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1174 COH901318_CX_CTRL_TCP_ENABLE |
1175 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1176 COH901318_CX_CTRL_HSP_ENABLE |
1177 COH901318_CX_CTRL_HSS_DISABLE |
1178 COH901318_CX_CTRL_DDMA_LEGACY |
1179 COH901318_CX_CTRL_PRDD_SOURCE,
1180 .param.ctrl_lli_last = 0 |
1181 COH901318_CX_CTRL_TC_ENABLE |
1182 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1183 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1184 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1185 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1186 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1187 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1188 COH901318_CX_CTRL_TCP_ENABLE |
1189 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1190 COH901318_CX_CTRL_HSP_ENABLE |
1191 COH901318_CX_CTRL_HSS_DISABLE |
1192 COH901318_CX_CTRL_DDMA_LEGACY |
1193 COH901318_CX_CTRL_PRDD_SOURCE,
1194 },
1195 {
1196 .number = U300_DMA_PCM_I2S1_RX,
1197 .name = "PCM I2S1 RX",
1198 .priority_high = 1,
1199 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1200 .param.config = COH901318_CX_CFG_CH_DISABLE |
1201 COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
1202 COH901318_CX_CFG_LCR_DISABLE |
1203 COH901318_CX_CFG_TC_IRQ_ENABLE |
1204 COH901318_CX_CFG_BE_IRQ_ENABLE,
1205 .param.ctrl_lli_chained = 0 |
1206 COH901318_CX_CTRL_TC_ENABLE |
1207 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1208 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1209 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1210 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1211 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1212 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1213 COH901318_CX_CTRL_TCP_DISABLE |
1214 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1215 COH901318_CX_CTRL_HSP_ENABLE |
1216 COH901318_CX_CTRL_HSS_DISABLE |
1217 COH901318_CX_CTRL_DDMA_LEGACY |
1218 COH901318_CX_CTRL_PRDD_DEST,
1219 .param.ctrl_lli = 0 |
1220 COH901318_CX_CTRL_TC_ENABLE |
1221 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1222 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1223 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1224 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1225 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1226 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1227 COH901318_CX_CTRL_TCP_ENABLE |
1228 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1229 COH901318_CX_CTRL_HSP_ENABLE |
1230 COH901318_CX_CTRL_HSS_DISABLE |
1231 COH901318_CX_CTRL_DDMA_LEGACY |
1232 COH901318_CX_CTRL_PRDD_DEST,
1233 .param.ctrl_lli_last = 0 |
1234 COH901318_CX_CTRL_TC_ENABLE |
1235 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1236 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1237 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1238 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1239 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1240 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1241 COH901318_CX_CTRL_TCP_ENABLE |
1242 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1243 COH901318_CX_CTRL_HSP_ENABLE |
1244 COH901318_CX_CTRL_HSS_DISABLE |
1245 COH901318_CX_CTRL_DDMA_LEGACY |
1246 COH901318_CX_CTRL_PRDD_DEST,
1247 },
1248 {
1249 .number = U300_DMA_XGAM_CDI,
1250 .name = "XGAM CDI",
1251 .priority_high = 0,
1252 },
1253 {
1254 .number = U300_DMA_XGAM_PDI,
1255 .name = "XGAM PDI",
1256 .priority_high = 0,
1257 },
1258 {
1259 .number = U300_DMA_SPI_TX,
1260 .name = "SPI TX",
1261 .priority_high = 0,
1262 },
1263 {
1264 .number = U300_DMA_SPI_RX,
1265 .name = "SPI RX",
1266 .priority_high = 0,
1267 },
1268 {
1269 .number = U300_DMA_GENERAL_PURPOSE_0,
1270 .name = "GENERAL 00",
1271 .priority_high = 0,
1272
1273 .param.config = flags_memcpy_config,
1274 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1275 .param.ctrl_lli = flags_memcpy_lli,
1276 .param.ctrl_lli_last = flags_memcpy_lli_last,
1277 },
1278 {
1279 .number = U300_DMA_GENERAL_PURPOSE_1,
1280 .name = "GENERAL 01",
1281 .priority_high = 0,
1282
1283 .param.config = flags_memcpy_config,
1284 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1285 .param.ctrl_lli = flags_memcpy_lli,
1286 .param.ctrl_lli_last = flags_memcpy_lli_last,
1287 },
1288 {
1289 .number = U300_DMA_GENERAL_PURPOSE_2,
1290 .name = "GENERAL 02",
1291 .priority_high = 0,
1292
1293 .param.config = flags_memcpy_config,
1294 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1295 .param.ctrl_lli = flags_memcpy_lli,
1296 .param.ctrl_lli_last = flags_memcpy_lli_last,
1297 },
1298 {
1299 .number = U300_DMA_GENERAL_PURPOSE_3,
1300 .name = "GENERAL 03",
1301 .priority_high = 0,
1302
1303 .param.config = flags_memcpy_config,
1304 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1305 .param.ctrl_lli = flags_memcpy_lli,
1306 .param.ctrl_lli_last = flags_memcpy_lli_last,
1307 },
1308 {
1309 .number = U300_DMA_GENERAL_PURPOSE_4,
1310 .name = "GENERAL 04",
1311 .priority_high = 0,
1312
1313 .param.config = flags_memcpy_config,
1314 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1315 .param.ctrl_lli = flags_memcpy_lli,
1316 .param.ctrl_lli_last = flags_memcpy_lli_last,
1317 },
1318 {
1319 .number = U300_DMA_GENERAL_PURPOSE_5,
1320 .name = "GENERAL 05",
1321 .priority_high = 0,
1322
1323 .param.config = flags_memcpy_config,
1324 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1325 .param.ctrl_lli = flags_memcpy_lli,
1326 .param.ctrl_lli_last = flags_memcpy_lli_last,
1327 },
1328 {
1329 .number = U300_DMA_GENERAL_PURPOSE_6,
1330 .name = "GENERAL 06",
1331 .priority_high = 0,
1332
1333 .param.config = flags_memcpy_config,
1334 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1335 .param.ctrl_lli = flags_memcpy_lli,
1336 .param.ctrl_lli_last = flags_memcpy_lli_last,
1337 },
1338 {
1339 .number = U300_DMA_GENERAL_PURPOSE_7,
1340 .name = "GENERAL 07",
1341 .priority_high = 0,
1342
1343 .param.config = flags_memcpy_config,
1344 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1345 .param.ctrl_lli = flags_memcpy_lli,
1346 .param.ctrl_lli_last = flags_memcpy_lli_last,
1347 },
1348 {
1349 .number = U300_DMA_GENERAL_PURPOSE_8,
1350 .name = "GENERAL 08",
1351 .priority_high = 0,
1352
1353 .param.config = flags_memcpy_config,
1354 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1355 .param.ctrl_lli = flags_memcpy_lli,
1356 .param.ctrl_lli_last = flags_memcpy_lli_last,
1357 },
1358#ifdef CONFIG_MACH_U300_BS335
1359 {
1360 .number = U300_DMA_UART1_TX,
1361 .name = "UART1 TX",
1362 .priority_high = 0,
1363 },
1364 {
1365 .number = U300_DMA_UART1_RX,
1366 .name = "UART1 RX",
1367 .priority_high = 0,
1368 }
1369#else
1370 {
1371 .number = U300_DMA_GENERAL_PURPOSE_9,
1372 .name = "GENERAL 09",
1373 .priority_high = 0,
1374
1375 .param.config = flags_memcpy_config,
1376 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1377 .param.ctrl_lli = flags_memcpy_lli,
1378 .param.ctrl_lli_last = flags_memcpy_lli_last,
1379 },
1380 {
1381 .number = U300_DMA_GENERAL_PURPOSE_10,
1382 .name = "GENERAL 10",
1383 .priority_high = 0,
1384
1385 .param.config = flags_memcpy_config,
1386 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1387 .param.ctrl_lli = flags_memcpy_lli,
1388 .param.ctrl_lli_last = flags_memcpy_lli_last,
1389 }
1390#endif
1391};
1392
1393
1394static struct coh901318_platform coh901318_platform = {
1395 .chans_slave = dma_slave_channels,
1396 .chans_memcpy = dma_memcpy_channels,
1397 .access_memory_state = coh901318_access_memory_state,
1398 .chan_conf = chan_config,
1399 .max_channels = U300_DMA_CHANNELS,
1400};
1401
375static struct platform_device wdog_device = { 1402static struct platform_device wdog_device = {
376 .name = "wdog", 1403 .name = "wdog",
377 .id = -1, 1404 .id = -1,
@@ -428,11 +1455,23 @@ static struct platform_device ave_device = {
428 .resource = ave_resources, 1455 .resource = ave_resources,
429}; 1456};
430 1457
1458static struct platform_device dma_device = {
1459 .name = "coh901318",
1460 .id = -1,
1461 .resource = dma_resource,
1462 .num_resources = ARRAY_SIZE(dma_resource),
1463 .dev = {
1464 .platform_data = &coh901318_platform,
1465 .coherent_dma_mask = ~0,
1466 },
1467};
1468
431/* 1469/*
432 * Notice that AMBA devices are initialized before platform devices. 1470 * Notice that AMBA devices are initialized before platform devices.
433 * 1471 *
434 */ 1472 */
435static struct platform_device *platform_devs[] __initdata = { 1473static struct platform_device *platform_devs[] __initdata = {
1474 &dma_device,
436 &i2c0_device, 1475 &i2c0_device,
437 &i2c1_device, 1476 &i2c1_device,
438 &keypad_device, 1477 &keypad_device,
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
new file mode 100644
index 000000000000..b239149ba0d0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -0,0 +1,69 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/dma_channels.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * Map file for the U300 dma driver.
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef DMA_CHANNELS_H
13#define DMA_CHANNELS_H
14
15#define U300_DMA_MSL_TX_0 0
16#define U300_DMA_MSL_TX_1 1
17#define U300_DMA_MSL_TX_2 2
18#define U300_DMA_MSL_TX_3 3
19#define U300_DMA_MSL_TX_4 4
20#define U300_DMA_MSL_TX_5 5
21#define U300_DMA_MSL_TX_6 6
22#define U300_DMA_MSL_RX_0 7
23#define U300_DMA_MSL_RX_1 8
24#define U300_DMA_MSL_RX_2 9
25#define U300_DMA_MSL_RX_3 10
26#define U300_DMA_MSL_RX_4 11
27#define U300_DMA_MSL_RX_5 12
28#define U300_DMA_MSL_RX_6 13
29#define U300_DMA_MMCSD_RX_TX 14
30#define U300_DMA_MSPRO_TX 15
31#define U300_DMA_MSPRO_RX 16
32#define U300_DMA_UART0_TX 17
33#define U300_DMA_UART0_RX 18
34#define U300_DMA_APEX_TX 19
35#define U300_DMA_APEX_RX 20
36#define U300_DMA_PCM_I2S0_TX 21
37#define U300_DMA_PCM_I2S0_RX 22
38#define U300_DMA_PCM_I2S1_TX 23
39#define U300_DMA_PCM_I2S1_RX 24
40#define U300_DMA_XGAM_CDI 25
41#define U300_DMA_XGAM_PDI 26
42#define U300_DMA_SPI_TX 27
43#define U300_DMA_SPI_RX 28
44#define U300_DMA_GENERAL_PURPOSE_0 29
45#define U300_DMA_GENERAL_PURPOSE_1 30
46#define U300_DMA_GENERAL_PURPOSE_2 31
47#define U300_DMA_GENERAL_PURPOSE_3 32
48#define U300_DMA_GENERAL_PURPOSE_4 33
49#define U300_DMA_GENERAL_PURPOSE_5 34
50#define U300_DMA_GENERAL_PURPOSE_6 35
51#define U300_DMA_GENERAL_PURPOSE_7 36
52#define U300_DMA_GENERAL_PURPOSE_8 37
53#ifdef CONFIG_MACH_U300_BS335
54#define U300_DMA_UART1_TX 38
55#define U300_DMA_UART1_RX 39
56#else
57#define U300_DMA_GENERAL_PURPOSE_9 38
58#define U300_DMA_GENERAL_PURPOSE_10 39
59#endif
60
61#ifdef CONFIG_MACH_U300_BS335
62#define U300_DMA_DEVICE_CHANNELS 32
63#else
64#define U300_DMA_DEVICE_CHANNELS 30
65#endif
66#define U300_DMA_CHANNELS 40
67
68
69#endif /* DMA_CHANNELS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 05:41:35 -0500