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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-03-08 15:21:04 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-03-08 15:21:04 -0500
commit988addf82e4c03739375279de73929580a2d4a6a (patch)
tree989ae1cd4e264bbad80c65f04480486246e7b9f3 /arch/arm/mach-u300
parent004c1c7096659d352b83047a7593e91d8a30e3c5 (diff)
parent25cf84cf377c0aae5dbcf937ea89bc7893db5176 (diff)
Merge branch 'origin' into devel-stable
Conflicts: arch/arm/mach-mx2/devices.c arch/arm/mach-mx2/devices.h sound/soc/pxa/pxa-ssp.c
Diffstat (limited to 'arch/arm/mach-u300')
-rw-r--r--arch/arm/mach-u300/clock.c29
-rw-r--r--arch/arm/mach-u300/core.c1029
-rw-r--r--arch/arm/mach-u300/gpio.c2
-rw-r--r--arch/arm/mach-u300/include/mach/coh901318.h2
-rw-r--r--arch/arm/mach-u300/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-u300/include/mach/dma_channels.h69
-rw-r--r--arch/arm/mach-u300/include/mach/vmalloc.h2
7 files changed, 1113 insertions, 22 deletions
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 111f7ea32b38..5af71d5ba665 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -610,34 +610,34 @@ EXPORT_SYMBOL(clk_get_rate);
610 610
611static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate) 611static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
612{ 612{
613 if (rate >= 18900000) 613 if (rate <= 18900000)
614 return 18900000; 614 return 18900000;
615 if (rate >= 20800000) 615 if (rate <= 20800000)
616 return 20800000; 616 return 20800000;
617 if (rate >= 23100000) 617 if (rate <= 23100000)
618 return 23100000; 618 return 23100000;
619 if (rate >= 26000000) 619 if (rate <= 26000000)
620 return 26000000; 620 return 26000000;
621 if (rate >= 29700000) 621 if (rate <= 29700000)
622 return 29700000; 622 return 29700000;
623 if (rate >= 34700000) 623 if (rate <= 34700000)
624 return 34700000; 624 return 34700000;
625 if (rate >= 41600000) 625 if (rate <= 41600000)
626 return 41600000; 626 return 41600000;
627 if (rate >= 52000000) 627 if (rate <= 52000000)
628 return 52000000; 628 return 52000000;
629 return -EINVAL; 629 return -EINVAL;
630} 630}
631 631
632static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) 632static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
633{ 633{
634 if (rate >= 13000000) 634 if (rate <= 13000000)
635 return 13000000; 635 return 13000000;
636 if (rate >= 52000000) 636 if (rate <= 52000000)
637 return 52000000; 637 return 52000000;
638 if (rate >= 104000000) 638 if (rate <= 104000000)
639 return 104000000; 639 return 104000000;
640 if (rate >= 208000000) 640 if (rate <= 208000000)
641 return 208000000; 641 return 208000000;
642 return -EINVAL; 642 return -EINVAL;
643} 643}
@@ -1276,11 +1276,8 @@ static struct clk_lookup lookups[] = {
1276 1276
1277static void __init clk_register(void) 1277static void __init clk_register(void)
1278{ 1278{
1279 int i;
1280
1281 /* Register the lookups */ 1279 /* Register the lookups */
1282 for (i = 0; i < ARRAY_SIZE(lookups); i++) 1280 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1283 clkdev_add(&lookups[i]);
1284} 1281}
1285 1282
1286/* 1283/*
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 653e25be3dd8..01b50313914c 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
3 * arch/arm/mach-u300/core.c 3 * arch/arm/mach-u300/core.c
4 * 4 *
5 * 5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB 6 * Copyright (C) 2007-2010 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2 7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions. 8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -19,6 +19,7 @@
19#include <linux/amba/bus.h> 19#include <linux/amba/bus.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <mach/coh901318.h>
22 23
23#include <asm/types.h> 24#include <asm/types.h>
24#include <asm/setup.h> 25#include <asm/setup.h>
@@ -29,6 +30,7 @@
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <mach/syscon.h> 32#include <mach/syscon.h>
33#include <mach/dma_channels.h>
32 34
33#include "clock.h" 35#include "clock.h"
34#include "mmc.h" 36#include "mmc.h"
@@ -372,8 +374,1019 @@ static struct resource ave_resources[] = {
372 }, 374 },
373}; 375};
374 376
377static struct resource dma_resource[] = {
378 {
379 .start = U300_DMAC_BASE,
380 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
381 .flags = IORESOURCE_MEM,
382 },
383 {
384 .start = IRQ_U300_DMA,
385 .end = IRQ_U300_DMA,
386 .flags = IORESOURCE_IRQ,
387 }
388};
389
390#ifdef CONFIG_MACH_U300_BS335
391/* points out all dma slave channels.
392 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
393 * Select all channels from A to B, end of list is marked with -1,-1
394 */
395static int dma_slave_channels[] = {
396 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
397 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
398
399/* points out all dma memcpy channels. */
400static int dma_memcpy_channels[] = {
401 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
402
403#else /* CONFIG_MACH_U300_BS335 */
404
405static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
406static int dma_memcpy_channels[] = {
407 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
408
409#endif
410
411/** register dma for memory access
412 *
413 * active 1 means dma intends to access memory
414 * 0 means dma wont access memory
415 */
416static void coh901318_access_memory_state(struct device *dev, bool active)
417{
418}
419
420#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
421 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
422 COH901318_CX_CFG_LCR_DISABLE | \
423 COH901318_CX_CFG_TC_IRQ_ENABLE | \
424 COH901318_CX_CFG_BE_IRQ_ENABLE)
425#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
426 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
427 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
428 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
429 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
430 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
431 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
432 COH901318_CX_CTRL_TCP_DISABLE | \
433 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
434 COH901318_CX_CTRL_HSP_DISABLE | \
435 COH901318_CX_CTRL_HSS_DISABLE | \
436 COH901318_CX_CTRL_DDMA_LEGACY | \
437 COH901318_CX_CTRL_PRDD_SOURCE)
438#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
443 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
444 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
445 COH901318_CX_CTRL_TCP_DISABLE | \
446 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
447 COH901318_CX_CTRL_HSP_DISABLE | \
448 COH901318_CX_CTRL_HSS_DISABLE | \
449 COH901318_CX_CTRL_DDMA_LEGACY | \
450 COH901318_CX_CTRL_PRDD_SOURCE)
451#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
452 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
453 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
454 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
455 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
456 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
457 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
458 COH901318_CX_CTRL_TCP_DISABLE | \
459 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
460 COH901318_CX_CTRL_HSP_DISABLE | \
461 COH901318_CX_CTRL_HSS_DISABLE | \
462 COH901318_CX_CTRL_DDMA_LEGACY | \
463 COH901318_CX_CTRL_PRDD_SOURCE)
464
465const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
466 {
467 .number = U300_DMA_MSL_TX_0,
468 .name = "MSL TX 0",
469 .priority_high = 0,
470 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
471 },
472 {
473 .number = U300_DMA_MSL_TX_1,
474 .name = "MSL TX 1",
475 .priority_high = 0,
476 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
477 .param.config = COH901318_CX_CFG_CH_DISABLE |
478 COH901318_CX_CFG_LCR_DISABLE |
479 COH901318_CX_CFG_TC_IRQ_ENABLE |
480 COH901318_CX_CFG_BE_IRQ_ENABLE,
481 .param.ctrl_lli_chained = 0 |
482 COH901318_CX_CTRL_TC_ENABLE |
483 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
484 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
485 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
486 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
487 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
488 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
489 COH901318_CX_CTRL_TCP_DISABLE |
490 COH901318_CX_CTRL_TC_IRQ_DISABLE |
491 COH901318_CX_CTRL_HSP_ENABLE |
492 COH901318_CX_CTRL_HSS_DISABLE |
493 COH901318_CX_CTRL_DDMA_LEGACY |
494 COH901318_CX_CTRL_PRDD_SOURCE,
495 .param.ctrl_lli = 0 |
496 COH901318_CX_CTRL_TC_ENABLE |
497 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
498 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
499 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
500 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
501 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
502 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
503 COH901318_CX_CTRL_TCP_ENABLE |
504 COH901318_CX_CTRL_TC_IRQ_DISABLE |
505 COH901318_CX_CTRL_HSP_ENABLE |
506 COH901318_CX_CTRL_HSS_DISABLE |
507 COH901318_CX_CTRL_DDMA_LEGACY |
508 COH901318_CX_CTRL_PRDD_SOURCE,
509 .param.ctrl_lli_last = 0 |
510 COH901318_CX_CTRL_TC_ENABLE |
511 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
512 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
513 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
514 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
515 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
516 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
517 COH901318_CX_CTRL_TCP_ENABLE |
518 COH901318_CX_CTRL_TC_IRQ_ENABLE |
519 COH901318_CX_CTRL_HSP_ENABLE |
520 COH901318_CX_CTRL_HSS_DISABLE |
521 COH901318_CX_CTRL_DDMA_LEGACY |
522 COH901318_CX_CTRL_PRDD_SOURCE,
523 },
524 {
525 .number = U300_DMA_MSL_TX_2,
526 .name = "MSL TX 2",
527 .priority_high = 0,
528 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
529 .param.config = COH901318_CX_CFG_CH_DISABLE |
530 COH901318_CX_CFG_LCR_DISABLE |
531 COH901318_CX_CFG_TC_IRQ_ENABLE |
532 COH901318_CX_CFG_BE_IRQ_ENABLE,
533 .param.ctrl_lli_chained = 0 |
534 COH901318_CX_CTRL_TC_ENABLE |
535 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
536 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
537 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
538 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
539 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
540 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
541 COH901318_CX_CTRL_TCP_DISABLE |
542 COH901318_CX_CTRL_TC_IRQ_DISABLE |
543 COH901318_CX_CTRL_HSP_ENABLE |
544 COH901318_CX_CTRL_HSS_DISABLE |
545 COH901318_CX_CTRL_DDMA_LEGACY |
546 COH901318_CX_CTRL_PRDD_SOURCE,
547 .param.ctrl_lli = 0 |
548 COH901318_CX_CTRL_TC_ENABLE |
549 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
550 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
551 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
552 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
553 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
554 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
555 COH901318_CX_CTRL_TCP_ENABLE |
556 COH901318_CX_CTRL_TC_IRQ_DISABLE |
557 COH901318_CX_CTRL_HSP_ENABLE |
558 COH901318_CX_CTRL_HSS_DISABLE |
559 COH901318_CX_CTRL_DDMA_LEGACY |
560 COH901318_CX_CTRL_PRDD_SOURCE,
561 .param.ctrl_lli_last = 0 |
562 COH901318_CX_CTRL_TC_ENABLE |
563 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
564 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
565 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
566 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
567 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
568 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
569 COH901318_CX_CTRL_TCP_ENABLE |
570 COH901318_CX_CTRL_TC_IRQ_ENABLE |
571 COH901318_CX_CTRL_HSP_ENABLE |
572 COH901318_CX_CTRL_HSS_DISABLE |
573 COH901318_CX_CTRL_DDMA_LEGACY |
574 COH901318_CX_CTRL_PRDD_SOURCE,
575 .desc_nbr_max = 10,
576 },
577 {
578 .number = U300_DMA_MSL_TX_3,
579 .name = "MSL TX 3",
580 .priority_high = 0,
581 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
582 .param.config = COH901318_CX_CFG_CH_DISABLE |
583 COH901318_CX_CFG_LCR_DISABLE |
584 COH901318_CX_CFG_TC_IRQ_ENABLE |
585 COH901318_CX_CFG_BE_IRQ_ENABLE,
586 .param.ctrl_lli_chained = 0 |
587 COH901318_CX_CTRL_TC_ENABLE |
588 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
589 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
590 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
591 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
592 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
593 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
594 COH901318_CX_CTRL_TCP_DISABLE |
595 COH901318_CX_CTRL_TC_IRQ_DISABLE |
596 COH901318_CX_CTRL_HSP_ENABLE |
597 COH901318_CX_CTRL_HSS_DISABLE |
598 COH901318_CX_CTRL_DDMA_LEGACY |
599 COH901318_CX_CTRL_PRDD_SOURCE,
600 .param.ctrl_lli = 0 |
601 COH901318_CX_CTRL_TC_ENABLE |
602 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
603 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
604 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
605 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
606 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
607 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
608 COH901318_CX_CTRL_TCP_ENABLE |
609 COH901318_CX_CTRL_TC_IRQ_DISABLE |
610 COH901318_CX_CTRL_HSP_ENABLE |
611 COH901318_CX_CTRL_HSS_DISABLE |
612 COH901318_CX_CTRL_DDMA_LEGACY |
613 COH901318_CX_CTRL_PRDD_SOURCE,
614 .param.ctrl_lli_last = 0 |
615 COH901318_CX_CTRL_TC_ENABLE |
616 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
617 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
618 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
619 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
620 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
621 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
622 COH901318_CX_CTRL_TCP_ENABLE |
623 COH901318_CX_CTRL_TC_IRQ_ENABLE |
624 COH901318_CX_CTRL_HSP_ENABLE |
625 COH901318_CX_CTRL_HSS_DISABLE |
626 COH901318_CX_CTRL_DDMA_LEGACY |
627 COH901318_CX_CTRL_PRDD_SOURCE,
628 },
629 {
630 .number = U300_DMA_MSL_TX_4,
631 .name = "MSL TX 4",
632 .priority_high = 0,
633 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
634 .param.config = COH901318_CX_CFG_CH_DISABLE |
635 COH901318_CX_CFG_LCR_DISABLE |
636 COH901318_CX_CFG_TC_IRQ_ENABLE |
637 COH901318_CX_CFG_BE_IRQ_ENABLE,
638 .param.ctrl_lli_chained = 0 |
639 COH901318_CX_CTRL_TC_ENABLE |
640 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
641 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
642 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
643 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
644 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
645 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
646 COH901318_CX_CTRL_TCP_DISABLE |
647 COH901318_CX_CTRL_TC_IRQ_DISABLE |
648 COH901318_CX_CTRL_HSP_ENABLE |
649 COH901318_CX_CTRL_HSS_DISABLE |
650 COH901318_CX_CTRL_DDMA_LEGACY |
651 COH901318_CX_CTRL_PRDD_SOURCE,
652 .param.ctrl_lli = 0 |
653 COH901318_CX_CTRL_TC_ENABLE |
654 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
655 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
656 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
657 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
658 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
659 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
660 COH901318_CX_CTRL_TCP_ENABLE |
661 COH901318_CX_CTRL_TC_IRQ_DISABLE |
662 COH901318_CX_CTRL_HSP_ENABLE |
663 COH901318_CX_CTRL_HSS_DISABLE |
664 COH901318_CX_CTRL_DDMA_LEGACY |
665 COH901318_CX_CTRL_PRDD_SOURCE,
666 .param.ctrl_lli_last = 0 |
667 COH901318_CX_CTRL_TC_ENABLE |
668 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
669 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
670 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
671 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
672 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
673 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
674 COH901318_CX_CTRL_TCP_ENABLE |
675 COH901318_CX_CTRL_TC_IRQ_ENABLE |
676 COH901318_CX_CTRL_HSP_ENABLE |
677 COH901318_CX_CTRL_HSS_DISABLE |
678 COH901318_CX_CTRL_DDMA_LEGACY |
679 COH901318_CX_CTRL_PRDD_SOURCE,
680 },
681 {
682 .number = U300_DMA_MSL_TX_5,
683 .name = "MSL TX 5",
684 .priority_high = 0,
685 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
686 },
687 {
688 .number = U300_DMA_MSL_TX_6,
689 .name = "MSL TX 6",
690 .priority_high = 0,
691 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
692 },
693 {
694 .number = U300_DMA_MSL_RX_0,
695 .name = "MSL RX 0",
696 .priority_high = 0,
697 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
698 },
699 {
700 .number = U300_DMA_MSL_RX_1,
701 .name = "MSL RX 1",
702 .priority_high = 0,
703 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
704 .param.config = COH901318_CX_CFG_CH_DISABLE |
705 COH901318_CX_CFG_LCR_DISABLE |
706 COH901318_CX_CFG_TC_IRQ_ENABLE |
707 COH901318_CX_CFG_BE_IRQ_ENABLE,
708 .param.ctrl_lli_chained = 0 |
709 COH901318_CX_CTRL_TC_ENABLE |
710 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
711 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
713 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
714 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
715 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
716 COH901318_CX_CTRL_TCP_DISABLE |
717 COH901318_CX_CTRL_TC_IRQ_DISABLE |
718 COH901318_CX_CTRL_HSP_ENABLE |
719 COH901318_CX_CTRL_HSS_DISABLE |
720 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
721 COH901318_CX_CTRL_PRDD_DEST,
722 .param.ctrl_lli = 0,
723 .param.ctrl_lli_last = 0 |
724 COH901318_CX_CTRL_TC_ENABLE |
725 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
726 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
727 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
728 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
729 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
730 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
731 COH901318_CX_CTRL_TCP_DISABLE |
732 COH901318_CX_CTRL_TC_IRQ_ENABLE |
733 COH901318_CX_CTRL_HSP_ENABLE |
734 COH901318_CX_CTRL_HSS_DISABLE |
735 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
736 COH901318_CX_CTRL_PRDD_DEST,
737 },
738 {
739 .number = U300_DMA_MSL_RX_2,
740 .name = "MSL RX 2",
741 .priority_high = 0,
742 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
743 .param.config = COH901318_CX_CFG_CH_DISABLE |
744 COH901318_CX_CFG_LCR_DISABLE |
745 COH901318_CX_CFG_TC_IRQ_ENABLE |
746 COH901318_CX_CFG_BE_IRQ_ENABLE,
747 .param.ctrl_lli_chained = 0 |
748 COH901318_CX_CTRL_TC_ENABLE |
749 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
750 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
751 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
752 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
753 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
754 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
755 COH901318_CX_CTRL_TCP_DISABLE |
756 COH901318_CX_CTRL_TC_IRQ_DISABLE |
757 COH901318_CX_CTRL_HSP_ENABLE |
758 COH901318_CX_CTRL_HSS_DISABLE |
759 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
760 COH901318_CX_CTRL_PRDD_DEST,
761 .param.ctrl_lli = 0 |
762 COH901318_CX_CTRL_TC_ENABLE |
763 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
764 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
765 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
766 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
767 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
768 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
769 COH901318_CX_CTRL_TCP_DISABLE |
770 COH901318_CX_CTRL_TC_IRQ_ENABLE |
771 COH901318_CX_CTRL_HSP_ENABLE |
772 COH901318_CX_CTRL_HSS_DISABLE |
773 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
774 COH901318_CX_CTRL_PRDD_DEST,
775 .param.ctrl_lli_last = 0 |
776 COH901318_CX_CTRL_TC_ENABLE |
777 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
778 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
779 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
780 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
781 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
782 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
783 COH901318_CX_CTRL_TCP_DISABLE |
784 COH901318_CX_CTRL_TC_IRQ_ENABLE |
785 COH901318_CX_CTRL_HSP_ENABLE |
786 COH901318_CX_CTRL_HSS_DISABLE |
787 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
788 COH901318_CX_CTRL_PRDD_DEST,
789 },
790 {
791 .number = U300_DMA_MSL_RX_3,
792 .name = "MSL RX 3",
793 .priority_high = 0,
794 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
795 .param.config = COH901318_CX_CFG_CH_DISABLE |
796 COH901318_CX_CFG_LCR_DISABLE |
797 COH901318_CX_CFG_TC_IRQ_ENABLE |
798 COH901318_CX_CFG_BE_IRQ_ENABLE,
799 .param.ctrl_lli_chained = 0 |
800 COH901318_CX_CTRL_TC_ENABLE |
801 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
802 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
803 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
804 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
805 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
806 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
807 COH901318_CX_CTRL_TCP_DISABLE |
808 COH901318_CX_CTRL_TC_IRQ_DISABLE |
809 COH901318_CX_CTRL_HSP_ENABLE |
810 COH901318_CX_CTRL_HSS_DISABLE |
811 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
812 COH901318_CX_CTRL_PRDD_DEST,
813 .param.ctrl_lli = 0 |
814 COH901318_CX_CTRL_TC_ENABLE |
815 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
816 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
817 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
818 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
819 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
820 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
821 COH901318_CX_CTRL_TCP_DISABLE |
822 COH901318_CX_CTRL_TC_IRQ_ENABLE |
823 COH901318_CX_CTRL_HSP_ENABLE |
824 COH901318_CX_CTRL_HSS_DISABLE |
825 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
826 COH901318_CX_CTRL_PRDD_DEST,
827 .param.ctrl_lli_last = 0 |
828 COH901318_CX_CTRL_TC_ENABLE |
829 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
830 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
831 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
832 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
833 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
834 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
835 COH901318_CX_CTRL_TCP_DISABLE |
836 COH901318_CX_CTRL_TC_IRQ_ENABLE |
837 COH901318_CX_CTRL_HSP_ENABLE |
838 COH901318_CX_CTRL_HSS_DISABLE |
839 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
840 COH901318_CX_CTRL_PRDD_DEST,
841 },
842 {
843 .number = U300_DMA_MSL_RX_4,
844 .name = "MSL RX 4",
845 .priority_high = 0,
846 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
847 .param.config = COH901318_CX_CFG_CH_DISABLE |
848 COH901318_CX_CFG_LCR_DISABLE |
849 COH901318_CX_CFG_TC_IRQ_ENABLE |
850 COH901318_CX_CFG_BE_IRQ_ENABLE,
851 .param.ctrl_lli_chained = 0 |
852 COH901318_CX_CTRL_TC_ENABLE |
853 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
854 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
855 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
856 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
857 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
858 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
859 COH901318_CX_CTRL_TCP_DISABLE |
860 COH901318_CX_CTRL_TC_IRQ_DISABLE |
861 COH901318_CX_CTRL_HSP_ENABLE |
862 COH901318_CX_CTRL_HSS_DISABLE |
863 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
864 COH901318_CX_CTRL_PRDD_DEST,
865 .param.ctrl_lli = 0 |
866 COH901318_CX_CTRL_TC_ENABLE |
867 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
868 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
869 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
870 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
871 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
872 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
873 COH901318_CX_CTRL_TCP_DISABLE |
874 COH901318_CX_CTRL_TC_IRQ_ENABLE |
875 COH901318_CX_CTRL_HSP_ENABLE |
876 COH901318_CX_CTRL_HSS_DISABLE |
877 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
878 COH901318_CX_CTRL_PRDD_DEST,
879 .param.ctrl_lli_last = 0 |
880 COH901318_CX_CTRL_TC_ENABLE |
881 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
882 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
883 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
884 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
885 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
886 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
887 COH901318_CX_CTRL_TCP_DISABLE |
888 COH901318_CX_CTRL_TC_IRQ_ENABLE |
889 COH901318_CX_CTRL_HSP_ENABLE |
890 COH901318_CX_CTRL_HSS_DISABLE |
891 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
892 COH901318_CX_CTRL_PRDD_DEST,
893 },
894 {
895 .number = U300_DMA_MSL_RX_5,
896 .name = "MSL RX 5",
897 .priority_high = 0,
898 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
899 .param.config = COH901318_CX_CFG_CH_DISABLE |
900 COH901318_CX_CFG_LCR_DISABLE |
901 COH901318_CX_CFG_TC_IRQ_ENABLE |
902 COH901318_CX_CFG_BE_IRQ_ENABLE,
903 .param.ctrl_lli_chained = 0 |
904 COH901318_CX_CTRL_TC_ENABLE |
905 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
906 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
907 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
908 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
909 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
910 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
911 COH901318_CX_CTRL_TCP_DISABLE |
912 COH901318_CX_CTRL_TC_IRQ_DISABLE |
913 COH901318_CX_CTRL_HSP_ENABLE |
914 COH901318_CX_CTRL_HSS_DISABLE |
915 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
916 COH901318_CX_CTRL_PRDD_DEST,
917 .param.ctrl_lli = 0 |
918 COH901318_CX_CTRL_TC_ENABLE |
919 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
920 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
921 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
922 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
923 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
924 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
925 COH901318_CX_CTRL_TCP_DISABLE |
926 COH901318_CX_CTRL_TC_IRQ_ENABLE |
927 COH901318_CX_CTRL_HSP_ENABLE |
928 COH901318_CX_CTRL_HSS_DISABLE |
929 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
930 COH901318_CX_CTRL_PRDD_DEST,
931 .param.ctrl_lli_last = 0 |
932 COH901318_CX_CTRL_TC_ENABLE |
933 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
934 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
935 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
936 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
937 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
938 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
939 COH901318_CX_CTRL_TCP_DISABLE |
940 COH901318_CX_CTRL_TC_IRQ_ENABLE |
941 COH901318_CX_CTRL_HSP_ENABLE |
942 COH901318_CX_CTRL_HSS_DISABLE |
943 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
944 COH901318_CX_CTRL_PRDD_DEST,
945 },
946 {
947 .number = U300_DMA_MSL_RX_6,
948 .name = "MSL RX 6",
949 .priority_high = 0,
950 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
951 },
952 {
953 .number = U300_DMA_MMCSD_RX_TX,
954 .name = "MMCSD RX TX",
955 .priority_high = 0,
956 .dev_addr = U300_MMCSD_BASE + 0x080,
957 .param.config = COH901318_CX_CFG_CH_DISABLE |
958 COH901318_CX_CFG_LCR_DISABLE |
959 COH901318_CX_CFG_TC_IRQ_ENABLE |
960 COH901318_CX_CFG_BE_IRQ_ENABLE,
961 .param.ctrl_lli_chained = 0 |
962 COH901318_CX_CTRL_TC_ENABLE |
963 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
964 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
965 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
966 COH901318_CX_CTRL_MASTER_MODE_M1RW |
967 COH901318_CX_CTRL_TCP_ENABLE |
968 COH901318_CX_CTRL_TC_IRQ_ENABLE |
969 COH901318_CX_CTRL_HSP_ENABLE |
970 COH901318_CX_CTRL_HSS_DISABLE |
971 COH901318_CX_CTRL_DDMA_LEGACY,
972 .param.ctrl_lli = 0 |
973 COH901318_CX_CTRL_TC_ENABLE |
974 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
975 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
976 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
977 COH901318_CX_CTRL_MASTER_MODE_M1RW |
978 COH901318_CX_CTRL_TCP_ENABLE |
979 COH901318_CX_CTRL_TC_IRQ_ENABLE |
980 COH901318_CX_CTRL_HSP_ENABLE |
981 COH901318_CX_CTRL_HSS_DISABLE |
982 COH901318_CX_CTRL_DDMA_LEGACY,
983 .param.ctrl_lli_last = 0 |
984 COH901318_CX_CTRL_TC_ENABLE |
985 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
986 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_DISABLE |
990 COH901318_CX_CTRL_TC_IRQ_ENABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY,
994
995 },
996 {
997 .number = U300_DMA_MSPRO_TX,
998 .name = "MSPRO TX",
999 .priority_high = 0,
1000 },
1001 {
1002 .number = U300_DMA_MSPRO_RX,
1003 .name = "MSPRO RX",
1004 .priority_high = 0,
1005 },
1006 {
1007 .number = U300_DMA_UART0_TX,
1008 .name = "UART0 TX",
1009 .priority_high = 0,
1010 },
1011 {
1012 .number = U300_DMA_UART0_RX,
1013 .name = "UART0 RX",
1014 .priority_high = 0,
1015 },
1016 {
1017 .number = U300_DMA_APEX_TX,
1018 .name = "APEX TX",
1019 .priority_high = 0,
1020 },
1021 {
1022 .number = U300_DMA_APEX_RX,
1023 .name = "APEX RX",
1024 .priority_high = 0,
1025 },
1026 {
1027 .number = U300_DMA_PCM_I2S0_TX,
1028 .name = "PCM I2S0 TX",
1029 .priority_high = 1,
1030 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1031 .param.config = COH901318_CX_CFG_CH_DISABLE |
1032 COH901318_CX_CFG_LCR_DISABLE |
1033 COH901318_CX_CFG_TC_IRQ_ENABLE |
1034 COH901318_CX_CFG_BE_IRQ_ENABLE,
1035 .param.ctrl_lli_chained = 0 |
1036 COH901318_CX_CTRL_TC_ENABLE |
1037 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1038 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1039 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1040 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1041 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1042 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1043 COH901318_CX_CTRL_TCP_DISABLE |
1044 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1045 COH901318_CX_CTRL_HSP_ENABLE |
1046 COH901318_CX_CTRL_HSS_DISABLE |
1047 COH901318_CX_CTRL_DDMA_LEGACY |
1048 COH901318_CX_CTRL_PRDD_SOURCE,
1049 .param.ctrl_lli = 0 |
1050 COH901318_CX_CTRL_TC_ENABLE |
1051 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1052 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1053 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1054 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1055 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1056 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1057 COH901318_CX_CTRL_TCP_ENABLE |
1058 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1059 COH901318_CX_CTRL_HSP_ENABLE |
1060 COH901318_CX_CTRL_HSS_DISABLE |
1061 COH901318_CX_CTRL_DDMA_LEGACY |
1062 COH901318_CX_CTRL_PRDD_SOURCE,
1063 .param.ctrl_lli_last = 0 |
1064 COH901318_CX_CTRL_TC_ENABLE |
1065 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1066 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1067 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1068 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1069 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1070 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1071 COH901318_CX_CTRL_TCP_ENABLE |
1072 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1073 COH901318_CX_CTRL_HSP_ENABLE |
1074 COH901318_CX_CTRL_HSS_DISABLE |
1075 COH901318_CX_CTRL_DDMA_LEGACY |
1076 COH901318_CX_CTRL_PRDD_SOURCE,
1077 },
1078 {
1079 .number = U300_DMA_PCM_I2S0_RX,
1080 .name = "PCM I2S0 RX",
1081 .priority_high = 1,
1082 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1083 .param.config = COH901318_CX_CFG_CH_DISABLE |
1084 COH901318_CX_CFG_LCR_DISABLE |
1085 COH901318_CX_CFG_TC_IRQ_ENABLE |
1086 COH901318_CX_CFG_BE_IRQ_ENABLE,
1087 .param.ctrl_lli_chained = 0 |
1088 COH901318_CX_CTRL_TC_ENABLE |
1089 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1090 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1091 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1092 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1093 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1094 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1095 COH901318_CX_CTRL_TCP_DISABLE |
1096 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1097 COH901318_CX_CTRL_HSP_ENABLE |
1098 COH901318_CX_CTRL_HSS_DISABLE |
1099 COH901318_CX_CTRL_DDMA_LEGACY |
1100 COH901318_CX_CTRL_PRDD_DEST,
1101 .param.ctrl_lli = 0 |
1102 COH901318_CX_CTRL_TC_ENABLE |
1103 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1104 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1105 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1106 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1107 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1108 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1109 COH901318_CX_CTRL_TCP_ENABLE |
1110 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1111 COH901318_CX_CTRL_HSP_ENABLE |
1112 COH901318_CX_CTRL_HSS_DISABLE |
1113 COH901318_CX_CTRL_DDMA_LEGACY |
1114 COH901318_CX_CTRL_PRDD_DEST,
1115 .param.ctrl_lli_last = 0 |
1116 COH901318_CX_CTRL_TC_ENABLE |
1117 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1118 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1119 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1120 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1121 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1122 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1123 COH901318_CX_CTRL_TCP_ENABLE |
1124 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1125 COH901318_CX_CTRL_HSP_ENABLE |
1126 COH901318_CX_CTRL_HSS_DISABLE |
1127 COH901318_CX_CTRL_DDMA_LEGACY |
1128 COH901318_CX_CTRL_PRDD_DEST,
1129 },
1130 {
1131 .number = U300_DMA_PCM_I2S1_TX,
1132 .name = "PCM I2S1 TX",
1133 .priority_high = 1,
1134 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1135 .param.config = COH901318_CX_CFG_CH_DISABLE |
1136 COH901318_CX_CFG_LCR_DISABLE |
1137 COH901318_CX_CFG_TC_IRQ_ENABLE |
1138 COH901318_CX_CFG_BE_IRQ_ENABLE,
1139 .param.ctrl_lli_chained = 0 |
1140 COH901318_CX_CTRL_TC_ENABLE |
1141 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1142 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1143 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1144 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1145 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1146 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1147 COH901318_CX_CTRL_TCP_DISABLE |
1148 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1149 COH901318_CX_CTRL_HSP_ENABLE |
1150 COH901318_CX_CTRL_HSS_DISABLE |
1151 COH901318_CX_CTRL_DDMA_LEGACY |
1152 COH901318_CX_CTRL_PRDD_SOURCE,
1153 .param.ctrl_lli = 0 |
1154 COH901318_CX_CTRL_TC_ENABLE |
1155 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1156 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1157 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1158 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1159 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1160 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1161 COH901318_CX_CTRL_TCP_ENABLE |
1162 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1163 COH901318_CX_CTRL_HSP_ENABLE |
1164 COH901318_CX_CTRL_HSS_DISABLE |
1165 COH901318_CX_CTRL_DDMA_LEGACY |
1166 COH901318_CX_CTRL_PRDD_SOURCE,
1167 .param.ctrl_lli_last = 0 |
1168 COH901318_CX_CTRL_TC_ENABLE |
1169 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1170 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1171 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1172 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1173 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1174 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1175 COH901318_CX_CTRL_TCP_ENABLE |
1176 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1177 COH901318_CX_CTRL_HSP_ENABLE |
1178 COH901318_CX_CTRL_HSS_DISABLE |
1179 COH901318_CX_CTRL_DDMA_LEGACY |
1180 COH901318_CX_CTRL_PRDD_SOURCE,
1181 },
1182 {
1183 .number = U300_DMA_PCM_I2S1_RX,
1184 .name = "PCM I2S1 RX",
1185 .priority_high = 1,
1186 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1187 .param.config = COH901318_CX_CFG_CH_DISABLE |
1188 COH901318_CX_CFG_LCR_DISABLE |
1189 COH901318_CX_CFG_TC_IRQ_ENABLE |
1190 COH901318_CX_CFG_BE_IRQ_ENABLE,
1191 .param.ctrl_lli_chained = 0 |
1192 COH901318_CX_CTRL_TC_ENABLE |
1193 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1194 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1195 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1196 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1197 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1198 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1199 COH901318_CX_CTRL_TCP_DISABLE |
1200 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1201 COH901318_CX_CTRL_HSP_ENABLE |
1202 COH901318_CX_CTRL_HSS_DISABLE |
1203 COH901318_CX_CTRL_DDMA_LEGACY |
1204 COH901318_CX_CTRL_PRDD_DEST,
1205 .param.ctrl_lli = 0 |
1206 COH901318_CX_CTRL_TC_ENABLE |
1207 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1208 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1209 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1210 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1211 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1212 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1213 COH901318_CX_CTRL_TCP_ENABLE |
1214 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1215 COH901318_CX_CTRL_HSP_ENABLE |
1216 COH901318_CX_CTRL_HSS_DISABLE |
1217 COH901318_CX_CTRL_DDMA_LEGACY |
1218 COH901318_CX_CTRL_PRDD_DEST,
1219 .param.ctrl_lli_last = 0 |
1220 COH901318_CX_CTRL_TC_ENABLE |
1221 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1222 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1223 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1224 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1225 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1226 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1227 COH901318_CX_CTRL_TCP_ENABLE |
1228 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1229 COH901318_CX_CTRL_HSP_ENABLE |
1230 COH901318_CX_CTRL_HSS_DISABLE |
1231 COH901318_CX_CTRL_DDMA_LEGACY |
1232 COH901318_CX_CTRL_PRDD_DEST,
1233 },
1234 {
1235 .number = U300_DMA_XGAM_CDI,
1236 .name = "XGAM CDI",
1237 .priority_high = 0,
1238 },
1239 {
1240 .number = U300_DMA_XGAM_PDI,
1241 .name = "XGAM PDI",
1242 .priority_high = 0,
1243 },
1244 {
1245 .number = U300_DMA_SPI_TX,
1246 .name = "SPI TX",
1247 .priority_high = 0,
1248 },
1249 {
1250 .number = U300_DMA_SPI_RX,
1251 .name = "SPI RX",
1252 .priority_high = 0,
1253 },
1254 {
1255 .number = U300_DMA_GENERAL_PURPOSE_0,
1256 .name = "GENERAL 00",
1257 .priority_high = 0,
1258
1259 .param.config = flags_memcpy_config,
1260 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1261 .param.ctrl_lli = flags_memcpy_lli,
1262 .param.ctrl_lli_last = flags_memcpy_lli_last,
1263 },
1264 {
1265 .number = U300_DMA_GENERAL_PURPOSE_1,
1266 .name = "GENERAL 01",
1267 .priority_high = 0,
1268
1269 .param.config = flags_memcpy_config,
1270 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1271 .param.ctrl_lli = flags_memcpy_lli,
1272 .param.ctrl_lli_last = flags_memcpy_lli_last,
1273 },
1274 {
1275 .number = U300_DMA_GENERAL_PURPOSE_2,
1276 .name = "GENERAL 02",
1277 .priority_high = 0,
1278
1279 .param.config = flags_memcpy_config,
1280 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1281 .param.ctrl_lli = flags_memcpy_lli,
1282 .param.ctrl_lli_last = flags_memcpy_lli_last,
1283 },
1284 {
1285 .number = U300_DMA_GENERAL_PURPOSE_3,
1286 .name = "GENERAL 03",
1287 .priority_high = 0,
1288
1289 .param.config = flags_memcpy_config,
1290 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1291 .param.ctrl_lli = flags_memcpy_lli,
1292 .param.ctrl_lli_last = flags_memcpy_lli_last,
1293 },
1294 {
1295 .number = U300_DMA_GENERAL_PURPOSE_4,
1296 .name = "GENERAL 04",
1297 .priority_high = 0,
1298
1299 .param.config = flags_memcpy_config,
1300 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1301 .param.ctrl_lli = flags_memcpy_lli,
1302 .param.ctrl_lli_last = flags_memcpy_lli_last,
1303 },
1304 {
1305 .number = U300_DMA_GENERAL_PURPOSE_5,
1306 .name = "GENERAL 05",
1307 .priority_high = 0,
1308
1309 .param.config = flags_memcpy_config,
1310 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1311 .param.ctrl_lli = flags_memcpy_lli,
1312 .param.ctrl_lli_last = flags_memcpy_lli_last,
1313 },
1314 {
1315 .number = U300_DMA_GENERAL_PURPOSE_6,
1316 .name = "GENERAL 06",
1317 .priority_high = 0,
1318
1319 .param.config = flags_memcpy_config,
1320 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1321 .param.ctrl_lli = flags_memcpy_lli,
1322 .param.ctrl_lli_last = flags_memcpy_lli_last,
1323 },
1324 {
1325 .number = U300_DMA_GENERAL_PURPOSE_7,
1326 .name = "GENERAL 07",
1327 .priority_high = 0,
1328
1329 .param.config = flags_memcpy_config,
1330 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1331 .param.ctrl_lli = flags_memcpy_lli,
1332 .param.ctrl_lli_last = flags_memcpy_lli_last,
1333 },
1334 {
1335 .number = U300_DMA_GENERAL_PURPOSE_8,
1336 .name = "GENERAL 08",
1337 .priority_high = 0,
1338
1339 .param.config = flags_memcpy_config,
1340 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1341 .param.ctrl_lli = flags_memcpy_lli,
1342 .param.ctrl_lli_last = flags_memcpy_lli_last,
1343 },
1344#ifdef CONFIG_MACH_U300_BS335
1345 {
1346 .number = U300_DMA_UART1_TX,
1347 .name = "UART1 TX",
1348 .priority_high = 0,
1349 },
1350 {
1351 .number = U300_DMA_UART1_RX,
1352 .name = "UART1 RX",
1353 .priority_high = 0,
1354 }
1355#else
1356 {
1357 .number = U300_DMA_GENERAL_PURPOSE_9,
1358 .name = "GENERAL 09",
1359 .priority_high = 0,
1360
1361 .param.config = flags_memcpy_config,
1362 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1363 .param.ctrl_lli = flags_memcpy_lli,
1364 .param.ctrl_lli_last = flags_memcpy_lli_last,
1365 },
1366 {
1367 .number = U300_DMA_GENERAL_PURPOSE_10,
1368 .name = "GENERAL 10",
1369 .priority_high = 0,
1370
1371 .param.config = flags_memcpy_config,
1372 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1373 .param.ctrl_lli = flags_memcpy_lli,
1374 .param.ctrl_lli_last = flags_memcpy_lli_last,
1375 }
1376#endif
1377};
1378
1379
1380static struct coh901318_platform coh901318_platform = {
1381 .chans_slave = dma_slave_channels,
1382 .chans_memcpy = dma_memcpy_channels,
1383 .access_memory_state = coh901318_access_memory_state,
1384 .chan_conf = chan_config,
1385 .max_channels = U300_DMA_CHANNELS,
1386};
1387
375static struct platform_device wdog_device = { 1388static struct platform_device wdog_device = {
376 .name = "wdog", 1389 .name = "coh901327_wdog",
377 .id = -1, 1390 .id = -1,
378 .num_resources = ARRAY_SIZE(wdog_resources), 1391 .num_resources = ARRAY_SIZE(wdog_resources),
379 .resource = wdog_resources, 1392 .resource = wdog_resources,
@@ -428,11 +1441,23 @@ static struct platform_device ave_device = {
428 .resource = ave_resources, 1441 .resource = ave_resources,
429}; 1442};
430 1443
1444static struct platform_device dma_device = {
1445 .name = "coh901318",
1446 .id = -1,
1447 .resource = dma_resource,
1448 .num_resources = ARRAY_SIZE(dma_resource),
1449 .dev = {
1450 .platform_data = &coh901318_platform,
1451 .coherent_dma_mask = ~0,
1452 },
1453};
1454
431/* 1455/*
432 * Notice that AMBA devices are initialized before platform devices. 1456 * Notice that AMBA devices are initialized before platform devices.
433 * 1457 *
434 */ 1458 */
435static struct platform_device *platform_devs[] __initdata = { 1459static struct platform_device *platform_devs[] __initdata = {
1460 &dma_device,
436 &i2c0_device, 1461 &i2c0_device,
437 &i2c1_device, 1462 &i2c1_device,
438 &keypad_device, 1463 &keypad_device,
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
index 0b35826b7d1d..5f61fd45a0c8 100644
--- a/arch/arm/mach-u300/gpio.c
+++ b/arch/arm/mach-u300/gpio.c
@@ -546,7 +546,7 @@ static void gpio_set_initial_values(void)
546 for (i = 0; i < U300_GPIO_MAX; i++) { 546 for (i = 0; i < U300_GPIO_MAX; i++) {
547 val = 0; 547 val = 0;
548 for (j = 0; j < 8; j++) 548 for (j = 0; j < 8; j++)
549 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j; 549 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
550 local_irq_save(flags); 550 local_irq_save(flags);
551 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); 551 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
552 local_irq_restore(flags); 552 local_irq_restore(flags);
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
index f4cfee9c7d28..b8155b4e5ffa 100644
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ b/arch/arm/mach-u300/include/mach/coh901318.h
@@ -53,7 +53,7 @@ struct coh901318_params {
53 * struct coh_dma_channel - dma channel base 53 * struct coh_dma_channel - dma channel base
54 * @name: ascii name of dma channel 54 * @name: ascii name of dma channel
55 * @number: channel id number 55 * @number: channel id number
56 * @desc_nbr_max: number of preallocated descriptortors 56 * @desc_nbr_max: number of preallocated descriptors
57 * @priority_high: prio of channel, 0 low otherwise high. 57 * @priority_high: prio of channel, 0 low otherwise high.
58 * @param: configuration parameters 58 * @param: configuration parameters
59 * @dev_addr: physical address of periphal connected to channel 59 * @dev_addr: physical address of periphal connected to channel
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
index f3a1cbbeeab3..ca4a028c2661 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <mach/hardware.h> 11#include <mach/hardware.h>
12 12
13 .macro addruart,rx 13 .macro addruart, rx, tmp
14 /* If we move the adress using MMU, use this. */ 14 /* If we move the adress using MMU, use this. */
15 mrc p15, 0, \rx, c1, c0 15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled? 16 tst \rx, #1 @ MMU enabled?
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
new file mode 100644
index 000000000000..b239149ba0d0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -0,0 +1,69 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/dma_channels.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * Map file for the U300 dma driver.
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef DMA_CHANNELS_H
13#define DMA_CHANNELS_H
14
15#define U300_DMA_MSL_TX_0 0
16#define U300_DMA_MSL_TX_1 1
17#define U300_DMA_MSL_TX_2 2
18#define U300_DMA_MSL_TX_3 3
19#define U300_DMA_MSL_TX_4 4
20#define U300_DMA_MSL_TX_5 5
21#define U300_DMA_MSL_TX_6 6
22#define U300_DMA_MSL_RX_0 7
23#define U300_DMA_MSL_RX_1 8
24#define U300_DMA_MSL_RX_2 9
25#define U300_DMA_MSL_RX_3 10
26#define U300_DMA_MSL_RX_4 11
27#define U300_DMA_MSL_RX_5 12
28#define U300_DMA_MSL_RX_6 13
29#define U300_DMA_MMCSD_RX_TX 14
30#define U300_DMA_MSPRO_TX 15
31#define U300_DMA_MSPRO_RX 16
32#define U300_DMA_UART0_TX 17
33#define U300_DMA_UART0_RX 18
34#define U300_DMA_APEX_TX 19
35#define U300_DMA_APEX_RX 20
36#define U300_DMA_PCM_I2S0_TX 21
37#define U300_DMA_PCM_I2S0_RX 22
38#define U300_DMA_PCM_I2S1_TX 23
39#define U300_DMA_PCM_I2S1_RX 24
40#define U300_DMA_XGAM_CDI 25
41#define U300_DMA_XGAM_PDI 26
42#define U300_DMA_SPI_TX 27
43#define U300_DMA_SPI_RX 28
44#define U300_DMA_GENERAL_PURPOSE_0 29
45#define U300_DMA_GENERAL_PURPOSE_1 30
46#define U300_DMA_GENERAL_PURPOSE_2 31
47#define U300_DMA_GENERAL_PURPOSE_3 32
48#define U300_DMA_GENERAL_PURPOSE_4 33
49#define U300_DMA_GENERAL_PURPOSE_5 34
50#define U300_DMA_GENERAL_PURPOSE_6 35
51#define U300_DMA_GENERAL_PURPOSE_7 36
52#define U300_DMA_GENERAL_PURPOSE_8 37
53#ifdef CONFIG_MACH_U300_BS335
54#define U300_DMA_UART1_TX 38
55#define U300_DMA_UART1_RX 39
56#else
57#define U300_DMA_GENERAL_PURPOSE_9 38
58#define U300_DMA_GENERAL_PURPOSE_10 39
59#endif
60
61#ifdef CONFIG_MACH_U300_BS335
62#define U300_DMA_DEVICE_CHANNELS 32
63#else
64#define U300_DMA_DEVICE_CHANNELS 30
65#endif
66#define U300_DMA_CHANNELS 40
67
68
69#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
index b00c51a66fbe..ec423b92b81d 100644
--- a/arch/arm/mach-u300/include/mach/vmalloc.h
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -9,4 +9,4 @@
9 * End must be above the I/O registers and on an even 2MiB boundary. 9 * End must be above the I/O registers and on an even 2MiB boundary.
10 * Author: Linus Walleij <linus.walleij@stericsson.com> 10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */ 11 */
12#define VMALLOC_END 0xfe800000 12#define VMALLOC_END 0xfe800000UL
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 18:44:02 -0500