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authorLinus Walleij <linus.walleij@linaro.org>2013-01-04 07:56:16 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-01-07 11:36:28 -0500
commit2b9277ad77e2b14a6bb113cc6c0da5101abc5261 (patch)
tree92aa8ba39d7723a71457d3009f1ec7290eb48af5 /arch/arm/mach-u300
parent9aab4d6f087a042d702b6e16346378731eeaf48e (diff)
dma: coh901318: push header down into the DMA subsystem
The defines in U300's <mach/coh901318.h> are now only used by the DMA engine driver itself, so move the header down into the DMA subsystem. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-u300')
-rw-r--r--arch/arm/mach-u300/core.c1
-rw-r--r--arch/arm/mach-u300/include/mach/coh901318.h249
-rw-r--r--arch/arm/mach-u300/spi.c1
3 files changed, 0 insertions, 251 deletions
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 834d0bd2aa0f..19f5c5311f47 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -41,7 +41,6 @@
41#include <asm/mach-types.h> 41#include <asm/mach-types.h>
42#include <asm/mach/arch.h> 42#include <asm/mach/arch.h>
43 43
44#include <mach/coh901318.h>
45#include <mach/hardware.h> 44#include <mach/hardware.h>
46#include <mach/syscon.h> 45#include <mach/syscon.h>
47#include <mach/irqs.h> 46#include <mach/irqs.h>
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
deleted file mode 100644
index 185fc59fd729..000000000000
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 *
3 * include/linux/coh901318.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * DMA driver for COH 901 318
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef COH901318_H
13#define COH901318_H
14
15#include <linux/device.h>
16#include <linux/dmaengine.h>
17
18#define MAX_DMA_PACKET_SIZE_SHIFT 11
19#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
20
21/**
22 * struct coh901318_lli - linked list item for DMAC
23 * @control: control settings for DMAC
24 * @src_addr: transfer source address
25 * @dst_addr: transfer destination address
26 * @link_addr: physical address to next lli
27 * @virt_link_addr: virtual address of next lli (only used by pool_free)
28 * @phy_this: physical address of current lli (only used by pool_free)
29 */
30struct coh901318_lli {
31 u32 control;
32 dma_addr_t src_addr;
33 dma_addr_t dst_addr;
34 dma_addr_t link_addr;
35
36 void *virt_link_addr;
37 dma_addr_t phy_this;
38};
39/**
40 * struct coh901318_params - parameters for DMAC configuration
41 * @config: DMA config register
42 * @ctrl_lli_last: DMA control register for the last lli in the list
43 * @ctrl_lli: DMA control register for an lli
44 * @ctrl_lli_chained: DMA control register for a chained lli
45 */
46struct coh901318_params {
47 u32 config;
48 u32 ctrl_lli_last;
49 u32 ctrl_lli;
50 u32 ctrl_lli_chained;
51};
52/**
53 * struct coh_dma_channel - dma channel base
54 * @name: ascii name of dma channel
55 * @number: channel id number
56 * @desc_nbr_max: number of preallocated descriptors
57 * @priority_high: prio of channel, 0 low otherwise high.
58 * @param: configuration parameters
59 */
60struct coh_dma_channel {
61 const char name[32];
62 const int number;
63 const int desc_nbr_max;
64 const int priority_high;
65 const struct coh901318_params param;
66};
67
68/**
69 * dma_access_memory_state_t - register dma for memory access
70 *
71 * @dev: The dma device
72 * @active: 1 means dma intends to access memory
73 * 0 means dma wont access memory
74 */
75typedef void (*dma_access_memory_state_t)(struct device *dev,
76 bool active);
77
78/**
79 * struct powersave - DMA power save structure
80 * @lock: lock protecting data in this struct
81 * @started_channels: bit mask indicating active dma channels
82 */
83struct powersave {
84 spinlock_t lock;
85 u64 started_channels;
86};
87/**
88 * struct coh901318_platform - platform arch structure
89 * @chans_slave: specifying dma slave channels
90 * @chans_memcpy: specifying dma memcpy channels
91 * @access_memory_state: requesting DMA memory access (on / off)
92 * @chan_conf: dma channel configurations
93 * @max_channels: max number of dma chanenls
94 */
95struct coh901318_platform {
96 const int *chans_slave;
97 const int *chans_memcpy;
98 const dma_access_memory_state_t access_memory_state;
99 const struct coh_dma_channel *chan_conf;
100 const int max_channels;
101};
102
103/*
104 * DMA Controller - this access the static mappings of the coh901318 dma.
105 *
106 */
107
108#define COH901318_MOD32_MASK (0x1F)
109#define COH901318_WORD_MASK (0xFFFFFFFF)
110/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
111#define COH901318_INT_STATUS1 (0x0000)
112#define COH901318_INT_STATUS2 (0x0004)
113/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
114#define COH901318_TC_INT_STATUS1 (0x0008)
115#define COH901318_TC_INT_STATUS2 (0x000C)
116/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
117#define COH901318_TC_INT_CLEAR1 (0x0010)
118#define COH901318_TC_INT_CLEAR2 (0x0014)
119/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
120#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
121#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
122/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
123#define COH901318_BE_INT_STATUS1 (0x0020)
124#define COH901318_BE_INT_STATUS2 (0x0024)
125/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
126#define COH901318_BE_INT_CLEAR1 (0x0028)
127#define COH901318_BE_INT_CLEAR2 (0x002C)
128/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
129#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
130#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
131
132/*
133 * CX_CFG - Channel Configuration Registers 32bit (R/W)
134 */
135#define COH901318_CX_CFG (0x0100)
136#define COH901318_CX_CFG_SPACING (0x04)
137/* Channel enable activates tha dma job */
138#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
139#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
140/* Request Mode */
141#define COH901318_CX_CFG_RM_MASK (0x00000006)
142#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
143#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
144#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
145#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
146#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
147/* Linked channel request field. RM must == 11 */
148#define COH901318_CX_CFG_LCRF_SHIFT 3
149#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
150#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
151/* Terminal Counter Interrupt Request Mask */
152#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
153#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
154/* Bus Error interrupt Mask */
155#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
156#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
157
158/*
159 * CX_STAT - Channel Status Registers 32bit (R/-)
160 */
161#define COH901318_CX_STAT (0x0200)
162#define COH901318_CX_STAT_SPACING (0x04)
163#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
164#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
165#define COH901318_CX_STAT_ACTIVE (0x00000002)
166#define COH901318_CX_STAT_ENABLED (0x00000001)
167
168/*
169 * CX_CTRL - Channel Control Registers 32bit (R/W)
170 */
171#define COH901318_CX_CTRL (0x0400)
172#define COH901318_CX_CTRL_SPACING (0x10)
173/* Transfer Count Enable */
174#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
175#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
176/* Transfer Count Value 0 - 4095 */
177#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
178/* Burst count */
179#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
180#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
181#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
182#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
183#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
184#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
185#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
186#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
187#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
188/* Source bus size */
189#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
190#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
191#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
192#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
193/* Source address increment */
194#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
195#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
196/* Destination Bus Size */
197#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
198#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
199#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
200#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
201/* Destination address increment */
202#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
203#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
204/* Master Mode (Master2 is only connected to MSL) */
205#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
206#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
207#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
208#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
209#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
210/* Terminal Count flag to PER enable */
211#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
212#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
213/* Terminal Count flags to CPU enable */
214#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
215#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
216/* Hand shake to peripheral */
217#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
218#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
219#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
220#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
221/* DMA mode */
222#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
223#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
224#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
225#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
226/* Primary Request Data Destination */
227#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
228#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
229#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
230
231/*
232 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
233 */
234#define COH901318_CX_SRC_ADDR (0x0404)
235#define COH901318_CX_SRC_ADDR_SPACING (0x10)
236
237/*
238 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
239 */
240#define COH901318_CX_DST_ADDR (0x0408)
241#define COH901318_CX_DST_ADDR_SPACING (0x10)
242
243/*
244 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
245 */
246#define COH901318_CX_LNK_ADDR (0x040C)
247#define COH901318_CX_LNK_ADDR_SPACING (0x10)
248#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
249#endif /* COH901318_H */
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index b34567f944ca..910698293d64 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,6 @@
12#include <linux/amba/pl022.h> 12#include <linux/amba/pl022.h>
13#include <linux/platform_data/dma-coh901318.h> 13#include <linux/platform_data/dma-coh901318.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <mach/coh901318.h>
16 15
17/* 16/*
18 * The following is for the actual devices on the SSP/SPI bus 17 * The following is for the actual devices on the SSP/SPI bus
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 12:19:47 -0500