aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-u300/include
diff options
context:
space:
mode:
authorLinus Walleij <linus.walleij@linaro.org>2011-09-08 04:04:51 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-09-08 05:03:56 -0400
commitcc890cd78acd7ab03442907d354b6af34e973cb3 (patch)
tree67cf73ea730969ffc26c3a5c55de8d96bb8b6299 /arch/arm/mach-u300/include
parent526a0dc771a5cac3224e26abd1f018976b967516 (diff)
ARM: 7083/1: rewrite U300 GPIO to use gpiolib
This rewrites the U300 GPIO so as to use gpiolib and struct gpio_chip instead of just generic GPIO, hiding all the platform specifics and passing in GPIO chip variant as platform data at runtime instead of the compiletime kludges. As a result <mach/gpio.h> is now empty for U300 and using just defaults. Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Debian kernel maintainers <debian-kernel@lists.debian.org> Cc: Arnaud Patard <arnaud.patard@rtp-net.org> Reported-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-u300/include')
-rw-r--r--arch/arm/mach-u300/include/mach/gpio-u300.h149
-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h47
-rw-r--r--arch/arm/mach-u300/include/mach/irqs.h25
3 files changed, 40 insertions, 181 deletions
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
index a6119062add9..0c2b2021951a 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/arch/arm/mach-u300/include/mach/gpio-u300.h
@@ -9,132 +9,6 @@
9#ifndef __MACH_U300_GPIO_U300_H 9#ifndef __MACH_U300_GPIO_U300_H
10#define __MACH_U300_GPIO_U300_H 10#define __MACH_U300_GPIO_U300_H
11 11
12#include <linux/kernel.h>
13#include <linux/io.h>
14#include <mach/hardware.h>
15#include <asm/irq.h>
16
17/* Switch type depending on platform/chip variant */
18#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
19#define U300_COH901335
20#endif
21#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
22#define U300_COH901571_3
23#endif
24
25/* Get base address for regs here */
26#include "u300-regs.h"
27/* IRQ numbers */
28#include "irqs.h"
29
30/*
31 * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
32 * used for anything, and often is. The event/enable etc figures are for
33 * the lowermost pin (pin 0 on each port), shift this left to match your
34 * pin if you're gonna use these values.
35 */
36#ifdef U300_COH901335
37#define U300_GPIO_PORTX_SPACING (0x1C)
38/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
39#define U300_GPIO_PXPDIR (0x00)
40#define U300_GPIO_PXPDOR (0x00)
41/* Port X Pin Config Register 32bit (R/W) */
42#define U300_GPIO_PXPCR (0x04)
43#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
44#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
45#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
46#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
47#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
48#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
49#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
50/* Port X Interrupt Event Register 32bit (R/W) */
51#define U300_GPIO_PXIEV (0x08)
52#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
53#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
54/* Port X Interrupt Enable Register 32bit (R/W) */
55#define U300_GPIO_PXIEN (0x0C)
56#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
57#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
58/* Port X Interrupt Force Register 32bit (R/W) */
59#define U300_GPIO_PXIFR (0x10)
60#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
61#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
62/* Port X Interrupt Config Register 32bit (R/W) */
63#define U300_GPIO_PXICR (0x14)
64#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
65#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
66#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
67#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
68/* Port X Pull-up Enable Register 32bit (R/W) */
69#define U300_GPIO_PXPER (0x18)
70#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
71#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
72/* Control Register 32bit (R/W) */
73#define U300_GPIO_CR (0x54)
74#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
75/* three ports of 8 bits each = GPIO pins 0..23 */
76#define U300_GPIO_NUM_PORTS 3
77#define U300_GPIO_PINS_PER_PORT 8
78#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
79#endif
80
81#ifdef U300_COH901571_3
82/*
83 * Control Register 32bit (R/W)
84 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
85 * gives the number of GPIO pins.
86 * bit 8-2 (mask 0x000001FC) contains the core version ID.
87 */
88#define U300_GPIO_CR (0x00)
89#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
90#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
91#define U300_GPIO_PORTX_SPACING (0x30)
92/* Port X Pin Data INPUT Register 32bit (R/W) */
93#define U300_GPIO_PXPDIR (0x04)
94/* Port X Pin Data OUTPUT Register 32bit (R/W) */
95#define U300_GPIO_PXPDOR (0x08)
96/* Port X Pin Config Register 32bit (R/W) */
97#define U300_GPIO_PXPCR (0x0C)
98#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
99#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
100#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
101#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
102#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
103#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
104#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
105/* Port X Pull-up Enable Register 32bit (R/W) */
106#define U300_GPIO_PXPER (0x10)
107#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
108#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
109/* Port X Interrupt Event Register 32bit (R/W) */
110#define U300_GPIO_PXIEV (0x14)
111#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
112#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
113/* Port X Interrupt Enable Register 32bit (R/W) */
114#define U300_GPIO_PXIEN (0x18)
115#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
116#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
117/* Port X Interrupt Force Register 32bit (R/W) */
118#define U300_GPIO_PXIFR (0x1C)
119#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
120#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
121/* Port X Interrupt Config Register 32bit (R/W) */
122#define U300_GPIO_PXICR (0x20)
123#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
124#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
125#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
126#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
127#ifdef CONFIG_MACH_U300_BS335
128/* seven ports of 8 bits each = GPIO pins 0..55 */
129#define U300_GPIO_NUM_PORTS 7
130#else
131/* five ports of 8 bits each = GPIO pins 0..39 */
132#define U300_GPIO_NUM_PORTS 5
133#endif
134#define U300_GPIO_PINS_PER_PORT 8
135#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
136#endif
137
138/* 12/*
139 * Individual pin assignments for the B26/S26. Notice that the 13 * Individual pin assignments for the B26/S26. Notice that the
140 * actual usage of these pins depends on the PAD MUX settings, that 14 * actual usage of these pins depends on the PAD MUX settings, that
@@ -250,4 +124,27 @@
250 124
251#endif 125#endif
252 126
127/**
128 * enum u300_gpio_variant - the type of U300 GPIO employed
129 */
130enum u300_gpio_variant {
131 U300_GPIO_COH901335,
132 U300_GPIO_COH901571_3_BS335,
133 U300_GPIO_COH901571_3_BS365,
134};
135
136/**
137 * struct u300_gpio_platform - U300 GPIO platform data
138 * @variant: IP block variant
139 * @ports: number of GPIO block ports
140 * @gpio_base: first GPIO number for this block (use a free range)
141 * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
142 */
143struct u300_gpio_platform {
144 enum u300_gpio_variant variant;
145 u8 ports;
146 int gpio_base;
147 int gpio_irq_base;
148};
149
253#endif /* __MACH_U300_GPIO_U300_H */ 150#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
index 430a0544baff..e69de29bb2d1 100644
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -1,47 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/gpio.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * GPIO block resgister definitions and inline macros for
9 * U300 GPIO COH 901 335 or COH 901 571/3
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_GPIO_H
14#define __MACH_U300_GPIO_H
15
16#define __ARM_GPIOLIB_COMPLEX
17
18/* These can be found in arch/arm/mach-u300/gpio.c */
19extern int gpio_is_valid(int number);
20extern int gpio_request(unsigned gpio, const char *label);
21extern void gpio_free(unsigned gpio);
22extern int gpio_direction_input(unsigned gpio);
23extern int gpio_direction_output(unsigned gpio, int value);
24extern int gpio_register_callback(unsigned gpio,
25 int (*func)(void *arg),
26 void *);
27extern int gpio_unregister_callback(unsigned gpio);
28extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
29extern void disable_irq_on_gpio_pin(unsigned gpio);
30extern void gpio_pullup(unsigned gpio, int value);
31extern int gpio_get_value(unsigned gpio);
32extern void gpio_set_value(unsigned gpio, int value);
33
34#define gpio_get_value_cansleep gpio_get_value
35#define gpio_set_value_cansleep gpio_set_value
36
37/* translates a pin number to a port number */
38#define PIN_TO_PORT(val) (val >> 3)
39
40/* wrappers to sleep-enable the previous two functions */
41static inline unsigned gpio_to_irq(unsigned gpio)
42{
43 return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
44}
45#define gpio_to_irq gpio_to_irq
46
47#endif /* __MACH_U300_GPIO_H */
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index 09b1b28fa8fd..d270fea32926 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -72,7 +72,7 @@
72 72
73/* DB3150 and DB3200 have only 45 IRQs */ 73/* DB3150 and DB3200 have only 45 IRQs */
74#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) 74#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
75#define U300_NR_IRQS 45 75#define U300_VIC_IRQS_END 45
76#endif 76#endif
77 77
78/* The DB3350-specific interrupt lines */ 78/* The DB3350-specific interrupt lines */
@@ -88,7 +88,7 @@
88#define IRQ_U300_GPIO_PORT4 53 88#define IRQ_U300_GPIO_PORT4 53
89#define IRQ_U300_GPIO_PORT5 54 89#define IRQ_U300_GPIO_PORT5 54
90#define IRQ_U300_GPIO_PORT6 55 90#define IRQ_U300_GPIO_PORT6 55
91#define U300_NR_IRQS 56 91#define U300_VIC_IRQS_END 56
92#endif 92#endif
93 93
94/* The DB3210-specific interrupt lines */ 94/* The DB3210-specific interrupt lines */
@@ -106,16 +106,25 @@
106#define IRQ_U300_NFIF 45 106#define IRQ_U300_NFIF 45
107#define IRQ_U300_NFIF2 46 107#define IRQ_U300_NFIF2 46
108#define IRQ_U300_SYSCON_PLL_LOCK 47 108#define IRQ_U300_SYSCON_PLL_LOCK 47
109#define U300_NR_IRQS 48 109#define U300_VIC_IRQS_END 48
110#endif 110#endif
111 111
112#ifdef CONFIG_AB3550_CORE 112/* Maximum 8*7 GPIO lines */
113#define IRQ_AB3550_BASE (U300_NR_IRQS) 113#ifdef CONFIG_GPIO_U300
114#define IRQ_AB3550_END (IRQ_AB3550_BASE + 37) 114#define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END)
115#define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56)
116#else
117#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
118#endif
115 119
116#define NR_IRQS (IRQ_AB3550_END + 1) 120/* Optional AB3550 mixsig chip */
121#ifdef CONFIG_AB3550_CORE
122#define IRQ_AB3550_BASE (IRQ_U300_GPIO_END)
123#define IRQ_AB3550_END (IRQ_AB3550_BASE + 38)
117#else 124#else
118#define NR_IRQS U300_NR_IRQS 125#define IRQ_AB3550_END (IRQ_U300_GPIO_END)
119#endif 126#endif
120 127
128#define NR_IRQS (IRQ_AB3550_END)
129
121#endif 130#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 07:40:42 -0500