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authorLinus Walleij <linus.walleij@stericsson.com>2010-08-05 02:59:54 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-08-10 17:10:56 -0400
commit3af8a8dad07527b25055b8b4c2a2b0d69362e7fb (patch)
tree1c2847dcddbeed9217c1fee8b92b16758426bb63 /arch/arm/mach-u300/clock.c
parentb7276b236dcf400003179e77f5b4b4c05e1fb29c (diff)
ARM: 6297/1: move U300 timer to dynamic clock lookup
This moves the U300 timer code to look up its clock rate from the clock framework as is apropriate and also switches it over to use the generic code for *calc_mult_shift() on clock source and clock event. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-u300/clock.c')
-rw-r--r--arch/arm/mach-u300/clock.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 7a94729caff9..60acf9e708ae 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -1204,10 +1204,14 @@ static struct clk timer_clk = {
1204 .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock), 1204 .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
1205}; 1205};
1206 1206
1207/*
1208 * There is a binary divider in the hardware that divides
1209 * the 13MHz PLL by 13 down to 1 MHz.
1210 */
1207static struct clk app_timer_clk = { 1211static struct clk app_timer_clk = {
1208 .name = "TIMER_APP", 1212 .name = "TIMER_APP",
1209 .parent = &slow_clk, 1213 .parent = &slow_clk,
1210 .rate = 13000000, 1214 .rate = 1000000,
1211 .hw_ctrld = true, 1215 .hw_ctrld = true,
1212 .reset = true, 1216 .reset = true,
1213 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, 1217 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,