diff options
author | Linus Walleij <linus.walleij@stericsson.com> | 2009-07-01 19:27:57 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-07-02 12:24:39 -0400 |
commit | 4ebfc3dba59fb84b315ebb0059347dc9342a32f1 (patch) | |
tree | 352f72b50e788a3846f5a6e408315457d3485706 /arch/arm/mach-u300/clock.c | |
parent | 9be4b17c4c900f634ab9be3d13e116aa31edb7cb (diff) |
[ARM] 5581/1: U300 clock updates
This adds a few default locks to the clocks (the clocks were used
before the locks were initialized by code), then renames the clocks
a bit to fit with the latest driver names (some changed during
review). Lastly it moves the initialization of the clock debugfs
entry to module_init() initcall level since the debugfs isn't up
in core_initcall().
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-u300/clock.c')
-rw-r--r-- | arch/arm/mach-u300/clock.c | 121 |
1 files changed, 80 insertions, 41 deletions
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index 5cd04d6751b3..111f7ea32b38 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
25 | #include <linux/timer.h> | 25 | #include <linux/timer.h> |
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <linux/seq_file.h> | ||
27 | 28 | ||
28 | #include <asm/clkdev.h> | 29 | #include <asm/clkdev.h> |
29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
@@ -702,6 +703,7 @@ static struct clk amba_clk = { | |||
702 | .rate = 52000000, /* this varies! */ | 703 | .rate = 52000000, /* this varies! */ |
703 | .hw_ctrld = true, | 704 | .hw_ctrld = true, |
704 | .reset = false, | 705 | .reset = false, |
706 | .lock = __SPIN_LOCK_UNLOCKED(amba_clk.lock), | ||
705 | }; | 707 | }; |
706 | 708 | ||
707 | /* | 709 | /* |
@@ -720,6 +722,7 @@ static struct clk cpu_clk = { | |||
720 | .set_rate = clk_set_rate_cpuclk, | 722 | .set_rate = clk_set_rate_cpuclk, |
721 | .get_rate = clk_get_rate_cpuclk, | 723 | .get_rate = clk_get_rate_cpuclk, |
722 | .round_rate = clk_round_rate_cpuclk, | 724 | .round_rate = clk_round_rate_cpuclk, |
725 | .lock = __SPIN_LOCK_UNLOCKED(cpu_clk.lock), | ||
723 | }; | 726 | }; |
724 | 727 | ||
725 | static struct clk nandif_clk = { | 728 | static struct clk nandif_clk = { |
@@ -732,6 +735,7 @@ static struct clk nandif_clk = { | |||
732 | .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, | 735 | .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, |
733 | .enable = syscon_clk_enable, | 736 | .enable = syscon_clk_enable, |
734 | .disable = syscon_clk_disable, | 737 | .disable = syscon_clk_disable, |
738 | .lock = __SPIN_LOCK_UNLOCKED(nandif_clk.lock), | ||
735 | }; | 739 | }; |
736 | 740 | ||
737 | static struct clk semi_clk = { | 741 | static struct clk semi_clk = { |
@@ -744,6 +748,7 @@ static struct clk semi_clk = { | |||
744 | .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, | 748 | .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, |
745 | .enable = syscon_clk_enable, | 749 | .enable = syscon_clk_enable, |
746 | .disable = syscon_clk_disable, | 750 | .disable = syscon_clk_disable, |
751 | .lock = __SPIN_LOCK_UNLOCKED(semi_clk.lock), | ||
747 | }; | 752 | }; |
748 | 753 | ||
749 | #ifdef CONFIG_MACH_U300_BS335 | 754 | #ifdef CONFIG_MACH_U300_BS335 |
@@ -758,6 +763,7 @@ static struct clk isp_clk = { | |||
758 | .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN, | 763 | .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN, |
759 | .enable = syscon_clk_enable, | 764 | .enable = syscon_clk_enable, |
760 | .disable = syscon_clk_disable, | 765 | .disable = syscon_clk_disable, |
766 | .lock = __SPIN_LOCK_UNLOCKED(isp_clk.lock), | ||
761 | }; | 767 | }; |
762 | 768 | ||
763 | static struct clk cds_clk = { | 769 | static struct clk cds_clk = { |
@@ -771,6 +777,7 @@ static struct clk cds_clk = { | |||
771 | .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN, | 777 | .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN, |
772 | .enable = syscon_clk_enable, | 778 | .enable = syscon_clk_enable, |
773 | .disable = syscon_clk_disable, | 779 | .disable = syscon_clk_disable, |
780 | .lock = __SPIN_LOCK_UNLOCKED(cds_clk.lock), | ||
774 | }; | 781 | }; |
775 | #endif | 782 | #endif |
776 | 783 | ||
@@ -785,6 +792,7 @@ static struct clk dma_clk = { | |||
785 | .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, | 792 | .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, |
786 | .enable = syscon_clk_enable, | 793 | .enable = syscon_clk_enable, |
787 | .disable = syscon_clk_disable, | 794 | .disable = syscon_clk_disable, |
795 | .lock = __SPIN_LOCK_UNLOCKED(dma_clk.lock), | ||
788 | }; | 796 | }; |
789 | 797 | ||
790 | static struct clk aaif_clk = { | 798 | static struct clk aaif_clk = { |
@@ -798,6 +806,7 @@ static struct clk aaif_clk = { | |||
798 | .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN, | 806 | .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN, |
799 | .enable = syscon_clk_enable, | 807 | .enable = syscon_clk_enable, |
800 | .disable = syscon_clk_disable, | 808 | .disable = syscon_clk_disable, |
809 | .lock = __SPIN_LOCK_UNLOCKED(aaif_clk.lock), | ||
801 | }; | 810 | }; |
802 | 811 | ||
803 | static struct clk apex_clk = { | 812 | static struct clk apex_clk = { |
@@ -811,6 +820,7 @@ static struct clk apex_clk = { | |||
811 | .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN, | 820 | .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN, |
812 | .enable = syscon_clk_enable, | 821 | .enable = syscon_clk_enable, |
813 | .disable = syscon_clk_disable, | 822 | .disable = syscon_clk_disable, |
823 | .lock = __SPIN_LOCK_UNLOCKED(apex_clk.lock), | ||
814 | }; | 824 | }; |
815 | 825 | ||
816 | static struct clk video_enc_clk = { | 826 | static struct clk video_enc_clk = { |
@@ -825,6 +835,7 @@ static struct clk video_enc_clk = { | |||
825 | .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN, | 835 | .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN, |
826 | .enable = syscon_clk_enable, | 836 | .enable = syscon_clk_enable, |
827 | .disable = syscon_clk_disable, | 837 | .disable = syscon_clk_disable, |
838 | .lock = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock), | ||
828 | }; | 839 | }; |
829 | 840 | ||
830 | static struct clk xgam_clk = { | 841 | static struct clk xgam_clk = { |
@@ -839,6 +850,7 @@ static struct clk xgam_clk = { | |||
839 | .get_rate = clk_get_rate_xgamclk, | 850 | .get_rate = clk_get_rate_xgamclk, |
840 | .enable = syscon_clk_enable, | 851 | .enable = syscon_clk_enable, |
841 | .disable = syscon_clk_disable, | 852 | .disable = syscon_clk_disable, |
853 | .lock = __SPIN_LOCK_UNLOCKED(xgam_clk.lock), | ||
842 | }; | 854 | }; |
843 | 855 | ||
844 | /* This clock is used to activate the video encoder */ | 856 | /* This clock is used to activate the video encoder */ |
@@ -854,6 +866,7 @@ static struct clk ahb_clk = { | |||
854 | .enable = syscon_clk_enable, | 866 | .enable = syscon_clk_enable, |
855 | .disable = syscon_clk_disable, | 867 | .disable = syscon_clk_disable, |
856 | .get_rate = clk_get_rate_ahb_clk, | 868 | .get_rate = clk_get_rate_ahb_clk, |
869 | .lock = __SPIN_LOCK_UNLOCKED(ahb_clk.lock), | ||
857 | }; | 870 | }; |
858 | 871 | ||
859 | 872 | ||
@@ -871,6 +884,7 @@ static struct clk ahb_subsys_clk = { | |||
871 | .enable = syscon_clk_enable, | 884 | .enable = syscon_clk_enable, |
872 | .disable = syscon_clk_disable, | 885 | .disable = syscon_clk_disable, |
873 | .get_rate = clk_get_rate_ahb_clk, | 886 | .get_rate = clk_get_rate_ahb_clk, |
887 | .lock = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock), | ||
874 | }; | 888 | }; |
875 | 889 | ||
876 | static struct clk intcon_clk = { | 890 | static struct clk intcon_clk = { |
@@ -882,6 +896,8 @@ static struct clk intcon_clk = { | |||
882 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, | 896 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, |
883 | .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN, | 897 | .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN, |
884 | /* INTCON can be reset but not clock-gated */ | 898 | /* INTCON can be reset but not clock-gated */ |
899 | .lock = __SPIN_LOCK_UNLOCKED(intcon_clk.lock), | ||
900 | |||
885 | }; | 901 | }; |
886 | 902 | ||
887 | static struct clk mspro_clk = { | 903 | static struct clk mspro_clk = { |
@@ -895,6 +911,7 @@ static struct clk mspro_clk = { | |||
895 | .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN, | 911 | .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN, |
896 | .enable = syscon_clk_enable, | 912 | .enable = syscon_clk_enable, |
897 | .disable = syscon_clk_disable, | 913 | .disable = syscon_clk_disable, |
914 | .lock = __SPIN_LOCK_UNLOCKED(mspro_clk.lock), | ||
898 | }; | 915 | }; |
899 | 916 | ||
900 | static struct clk emif_clk = { | 917 | static struct clk emif_clk = { |
@@ -909,6 +926,7 @@ static struct clk emif_clk = { | |||
909 | .enable = syscon_clk_enable, | 926 | .enable = syscon_clk_enable, |
910 | .disable = syscon_clk_disable, | 927 | .disable = syscon_clk_disable, |
911 | .get_rate = clk_get_rate_emif_clk, | 928 | .get_rate = clk_get_rate_emif_clk, |
929 | .lock = __SPIN_LOCK_UNLOCKED(emif_clk.lock), | ||
912 | }; | 930 | }; |
913 | 931 | ||
914 | 932 | ||
@@ -926,6 +944,7 @@ static struct clk fast_clk = { | |||
926 | .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, | 944 | .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, |
927 | .enable = syscon_clk_enable, | 945 | .enable = syscon_clk_enable, |
928 | .disable = syscon_clk_disable, | 946 | .disable = syscon_clk_disable, |
947 | .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock), | ||
929 | }; | 948 | }; |
930 | 949 | ||
931 | static struct clk mmcsd_clk = { | 950 | static struct clk mmcsd_clk = { |
@@ -942,6 +961,7 @@ static struct clk mmcsd_clk = { | |||
942 | .round_rate = clk_round_rate_mclk, | 961 | .round_rate = clk_round_rate_mclk, |
943 | .disable = syscon_clk_disable, | 962 | .disable = syscon_clk_disable, |
944 | .enable = syscon_clk_enable, | 963 | .enable = syscon_clk_enable, |
964 | .lock = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock), | ||
945 | }; | 965 | }; |
946 | 966 | ||
947 | static struct clk i2s0_clk = { | 967 | static struct clk i2s0_clk = { |
@@ -956,6 +976,7 @@ static struct clk i2s0_clk = { | |||
956 | .enable = syscon_clk_enable, | 976 | .enable = syscon_clk_enable, |
957 | .disable = syscon_clk_disable, | 977 | .disable = syscon_clk_disable, |
958 | .get_rate = clk_get_rate_i2s_i2c_spi, | 978 | .get_rate = clk_get_rate_i2s_i2c_spi, |
979 | .lock = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock), | ||
959 | }; | 980 | }; |
960 | 981 | ||
961 | static struct clk i2s1_clk = { | 982 | static struct clk i2s1_clk = { |
@@ -970,6 +991,7 @@ static struct clk i2s1_clk = { | |||
970 | .enable = syscon_clk_enable, | 991 | .enable = syscon_clk_enable, |
971 | .disable = syscon_clk_disable, | 992 | .disable = syscon_clk_disable, |
972 | .get_rate = clk_get_rate_i2s_i2c_spi, | 993 | .get_rate = clk_get_rate_i2s_i2c_spi, |
994 | .lock = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock), | ||
973 | }; | 995 | }; |
974 | 996 | ||
975 | static struct clk i2c0_clk = { | 997 | static struct clk i2c0_clk = { |
@@ -984,6 +1006,7 @@ static struct clk i2c0_clk = { | |||
984 | .enable = syscon_clk_enable, | 1006 | .enable = syscon_clk_enable, |
985 | .disable = syscon_clk_disable, | 1007 | .disable = syscon_clk_disable, |
986 | .get_rate = clk_get_rate_i2s_i2c_spi, | 1008 | .get_rate = clk_get_rate_i2s_i2c_spi, |
1009 | .lock = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock), | ||
987 | }; | 1010 | }; |
988 | 1011 | ||
989 | static struct clk i2c1_clk = { | 1012 | static struct clk i2c1_clk = { |
@@ -998,6 +1021,7 @@ static struct clk i2c1_clk = { | |||
998 | .enable = syscon_clk_enable, | 1021 | .enable = syscon_clk_enable, |
999 | .disable = syscon_clk_disable, | 1022 | .disable = syscon_clk_disable, |
1000 | .get_rate = clk_get_rate_i2s_i2c_spi, | 1023 | .get_rate = clk_get_rate_i2s_i2c_spi, |
1024 | .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock), | ||
1001 | }; | 1025 | }; |
1002 | 1026 | ||
1003 | static struct clk spi_clk = { | 1027 | static struct clk spi_clk = { |
@@ -1012,6 +1036,7 @@ static struct clk spi_clk = { | |||
1012 | .enable = syscon_clk_enable, | 1036 | .enable = syscon_clk_enable, |
1013 | .disable = syscon_clk_disable, | 1037 | .disable = syscon_clk_disable, |
1014 | .get_rate = clk_get_rate_i2s_i2c_spi, | 1038 | .get_rate = clk_get_rate_i2s_i2c_spi, |
1039 | .lock = __SPIN_LOCK_UNLOCKED(spi_clk.lock), | ||
1015 | }; | 1040 | }; |
1016 | 1041 | ||
1017 | #ifdef CONFIG_MACH_U300_BS335 | 1042 | #ifdef CONFIG_MACH_U300_BS335 |
@@ -1026,6 +1051,7 @@ static struct clk uart1_clk = { | |||
1026 | .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, | 1051 | .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, |
1027 | .enable = syscon_clk_enable, | 1052 | .enable = syscon_clk_enable, |
1028 | .disable = syscon_clk_disable, | 1053 | .disable = syscon_clk_disable, |
1054 | .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock), | ||
1029 | }; | 1055 | }; |
1030 | #endif | 1056 | #endif |
1031 | 1057 | ||
@@ -1044,6 +1070,7 @@ static struct clk slow_clk = { | |||
1044 | .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, | 1070 | .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, |
1045 | .enable = syscon_clk_enable, | 1071 | .enable = syscon_clk_enable, |
1046 | .disable = syscon_clk_disable, | 1072 | .disable = syscon_clk_disable, |
1073 | .lock = __SPIN_LOCK_UNLOCKED(slow_clk.lock), | ||
1047 | }; | 1074 | }; |
1048 | 1075 | ||
1049 | /* TODO: implement SYSCON clock? */ | 1076 | /* TODO: implement SYSCON clock? */ |
@@ -1055,6 +1082,7 @@ static struct clk wdog_clk = { | |||
1055 | .rate = 32768, | 1082 | .rate = 32768, |
1056 | .reset = false, | 1083 | .reset = false, |
1057 | /* This is always on, cannot be enabled/disabled or reset */ | 1084 | /* This is always on, cannot be enabled/disabled or reset */ |
1085 | .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock), | ||
1058 | }; | 1086 | }; |
1059 | 1087 | ||
1060 | /* This one is hardwired to PLL13 */ | 1088 | /* This one is hardwired to PLL13 */ |
@@ -1069,6 +1097,7 @@ static struct clk uart_clk = { | |||
1069 | .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, | 1097 | .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, |
1070 | .enable = syscon_clk_enable, | 1098 | .enable = syscon_clk_enable, |
1071 | .disable = syscon_clk_disable, | 1099 | .disable = syscon_clk_disable, |
1100 | .lock = __SPIN_LOCK_UNLOCKED(uart_clk.lock), | ||
1072 | }; | 1101 | }; |
1073 | 1102 | ||
1074 | static struct clk keypad_clk = { | 1103 | static struct clk keypad_clk = { |
@@ -1082,6 +1111,7 @@ static struct clk keypad_clk = { | |||
1082 | .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN, | 1111 | .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN, |
1083 | .enable = syscon_clk_enable, | 1112 | .enable = syscon_clk_enable, |
1084 | .disable = syscon_clk_disable, | 1113 | .disable = syscon_clk_disable, |
1114 | .lock = __SPIN_LOCK_UNLOCKED(keypad_clk.lock), | ||
1085 | }; | 1115 | }; |
1086 | 1116 | ||
1087 | static struct clk gpio_clk = { | 1117 | static struct clk gpio_clk = { |
@@ -1095,6 +1125,7 @@ static struct clk gpio_clk = { | |||
1095 | .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, | 1125 | .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, |
1096 | .enable = syscon_clk_enable, | 1126 | .enable = syscon_clk_enable, |
1097 | .disable = syscon_clk_disable, | 1127 | .disable = syscon_clk_disable, |
1128 | .lock = __SPIN_LOCK_UNLOCKED(gpio_clk.lock), | ||
1098 | }; | 1129 | }; |
1099 | 1130 | ||
1100 | static struct clk rtc_clk = { | 1131 | static struct clk rtc_clk = { |
@@ -1106,6 +1137,7 @@ static struct clk rtc_clk = { | |||
1106 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, | 1137 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
1107 | .res_mask = U300_SYSCON_RSR_RTC_RESET_EN, | 1138 | .res_mask = U300_SYSCON_RSR_RTC_RESET_EN, |
1108 | /* This clock is always on, cannot be enabled/disabled */ | 1139 | /* This clock is always on, cannot be enabled/disabled */ |
1140 | .lock = __SPIN_LOCK_UNLOCKED(rtc_clk.lock), | ||
1109 | }; | 1141 | }; |
1110 | 1142 | ||
1111 | static struct clk bustr_clk = { | 1143 | static struct clk bustr_clk = { |
@@ -1119,6 +1151,7 @@ static struct clk bustr_clk = { | |||
1119 | .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN, | 1151 | .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN, |
1120 | .enable = syscon_clk_enable, | 1152 | .enable = syscon_clk_enable, |
1121 | .disable = syscon_clk_disable, | 1153 | .disable = syscon_clk_disable, |
1154 | .lock = __SPIN_LOCK_UNLOCKED(bustr_clk.lock), | ||
1122 | }; | 1155 | }; |
1123 | 1156 | ||
1124 | static struct clk evhist_clk = { | 1157 | static struct clk evhist_clk = { |
@@ -1132,6 +1165,7 @@ static struct clk evhist_clk = { | |||
1132 | .clk_val = U300_SYSCON_SBCER_EH_CLK_EN, | 1165 | .clk_val = U300_SYSCON_SBCER_EH_CLK_EN, |
1133 | .enable = syscon_clk_enable, | 1166 | .enable = syscon_clk_enable, |
1134 | .disable = syscon_clk_disable, | 1167 | .disable = syscon_clk_disable, |
1168 | .lock = __SPIN_LOCK_UNLOCKED(evhist_clk.lock), | ||
1135 | }; | 1169 | }; |
1136 | 1170 | ||
1137 | static struct clk timer_clk = { | 1171 | static struct clk timer_clk = { |
@@ -1145,6 +1179,7 @@ static struct clk timer_clk = { | |||
1145 | .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, | 1179 | .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, |
1146 | .enable = syscon_clk_enable, | 1180 | .enable = syscon_clk_enable, |
1147 | .disable = syscon_clk_disable, | 1181 | .disable = syscon_clk_disable, |
1182 | .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock), | ||
1148 | }; | 1183 | }; |
1149 | 1184 | ||
1150 | static struct clk app_timer_clk = { | 1185 | static struct clk app_timer_clk = { |
@@ -1158,6 +1193,7 @@ static struct clk app_timer_clk = { | |||
1158 | .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, | 1193 | .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, |
1159 | .enable = syscon_clk_enable, | 1194 | .enable = syscon_clk_enable, |
1160 | .disable = syscon_clk_disable, | 1195 | .disable = syscon_clk_disable, |
1196 | .lock = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock), | ||
1161 | }; | 1197 | }; |
1162 | 1198 | ||
1163 | #ifdef CONFIG_MACH_U300_BS335 | 1199 | #ifdef CONFIG_MACH_U300_BS335 |
@@ -1172,6 +1208,7 @@ static struct clk ppm_clk = { | |||
1172 | .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN, | 1208 | .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN, |
1173 | .enable = syscon_clk_enable, | 1209 | .enable = syscon_clk_enable, |
1174 | .disable = syscon_clk_disable, | 1210 | .disable = syscon_clk_disable, |
1211 | .lock = __SPIN_LOCK_UNLOCKED(ppm_clk.lock), | ||
1175 | }; | 1212 | }; |
1176 | #endif | 1213 | #endif |
1177 | 1214 | ||
@@ -1187,53 +1224,53 @@ static struct clk ppm_clk = { | |||
1187 | */ | 1224 | */ |
1188 | static struct clk_lookup lookups[] = { | 1225 | static struct clk_lookup lookups[] = { |
1189 | /* Connected directly to the AMBA bus */ | 1226 | /* Connected directly to the AMBA bus */ |
1190 | DEF_LOOKUP("amba", &amba_clk), | 1227 | DEF_LOOKUP("amba", &amba_clk), |
1191 | DEF_LOOKUP("cpu", &cpu_clk), | 1228 | DEF_LOOKUP("cpu", &cpu_clk), |
1192 | DEF_LOOKUP("nandif", &nandif_clk), | 1229 | DEF_LOOKUP("fsmc", &nandif_clk), |
1193 | DEF_LOOKUP("semi", &semi_clk), | 1230 | DEF_LOOKUP("semi", &semi_clk), |
1194 | #ifdef CONFIG_MACH_U300_BS335 | 1231 | #ifdef CONFIG_MACH_U300_BS335 |
1195 | DEF_LOOKUP("isp", &isp_clk), | 1232 | DEF_LOOKUP("isp", &isp_clk), |
1196 | DEF_LOOKUP("cds", &cds_clk), | 1233 | DEF_LOOKUP("cds", &cds_clk), |
1197 | #endif | 1234 | #endif |
1198 | DEF_LOOKUP("dma", &dma_clk), | 1235 | DEF_LOOKUP("dma", &dma_clk), |
1199 | DEF_LOOKUP("aaif", &aaif_clk), | 1236 | DEF_LOOKUP("msl", &aaif_clk), |
1200 | DEF_LOOKUP("apex", &apex_clk), | 1237 | DEF_LOOKUP("apex", &apex_clk), |
1201 | DEF_LOOKUP("video_enc", &video_enc_clk), | 1238 | DEF_LOOKUP("video_enc", &video_enc_clk), |
1202 | DEF_LOOKUP("xgam", &xgam_clk), | 1239 | DEF_LOOKUP("xgam", &xgam_clk), |
1203 | DEF_LOOKUP("ahb", &ahb_clk), | 1240 | DEF_LOOKUP("ahb", &ahb_clk), |
1204 | /* AHB bridge clocks */ | 1241 | /* AHB bridge clocks */ |
1205 | DEF_LOOKUP("ahb", &ahb_subsys_clk), | 1242 | DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk), |
1206 | DEF_LOOKUP("intcon", &intcon_clk), | 1243 | DEF_LOOKUP("intcon", &intcon_clk), |
1207 | DEF_LOOKUP("mspro", &mspro_clk), | 1244 | DEF_LOOKUP("mspro", &mspro_clk), |
1208 | DEF_LOOKUP("pl172", &emif_clk), | 1245 | DEF_LOOKUP("pl172", &emif_clk), |
1209 | /* FAST bridge clocks */ | 1246 | /* FAST bridge clocks */ |
1210 | DEF_LOOKUP("fast", &fast_clk), | 1247 | DEF_LOOKUP("fast", &fast_clk), |
1211 | DEF_LOOKUP("mmci", &mmcsd_clk), | 1248 | DEF_LOOKUP("mmci", &mmcsd_clk), |
1212 | /* | 1249 | /* |
1213 | * The .0 and .1 identifiers on these comes from the platform device | 1250 | * The .0 and .1 identifiers on these comes from the platform device |
1214 | * .id field and are assigned when the platform devices are registered. | 1251 | * .id field and are assigned when the platform devices are registered. |
1215 | */ | 1252 | */ |
1216 | DEF_LOOKUP("i2s.0", &i2s0_clk), | 1253 | DEF_LOOKUP("i2s.0", &i2s0_clk), |
1217 | DEF_LOOKUP("i2s.1", &i2s1_clk), | 1254 | DEF_LOOKUP("i2s.1", &i2s1_clk), |
1218 | DEF_LOOKUP("stddci2c.0", &i2c0_clk), | 1255 | DEF_LOOKUP("stu300.0", &i2c0_clk), |
1219 | DEF_LOOKUP("stddci2c.1", &i2c1_clk), | 1256 | DEF_LOOKUP("stu300.1", &i2c1_clk), |
1220 | DEF_LOOKUP("pl022", &spi_clk), | 1257 | DEF_LOOKUP("pl022", &spi_clk), |
1221 | #ifdef CONFIG_MACH_U300_BS335 | 1258 | #ifdef CONFIG_MACH_U300_BS335 |
1222 | DEF_LOOKUP("uart1", &uart1_clk), | 1259 | DEF_LOOKUP("uart1", &uart1_clk), |
1223 | #endif | 1260 | #endif |
1224 | /* SLOW bridge clocks */ | 1261 | /* SLOW bridge clocks */ |
1225 | DEF_LOOKUP("slow", &slow_clk), | 1262 | DEF_LOOKUP("slow", &slow_clk), |
1226 | DEF_LOOKUP("wdog", &wdog_clk), | 1263 | DEF_LOOKUP("coh901327_wdog", &wdog_clk), |
1227 | DEF_LOOKUP("uart0", &uart_clk), | 1264 | DEF_LOOKUP("uart0", &uart_clk), |
1228 | DEF_LOOKUP("apptimer", &app_timer_clk), | 1265 | DEF_LOOKUP("apptimer", &app_timer_clk), |
1229 | DEF_LOOKUP("keypad", &keypad_clk), | 1266 | DEF_LOOKUP("coh901461-keypad", &keypad_clk), |
1230 | DEF_LOOKUP("u300-gpio", &gpio_clk), | 1267 | DEF_LOOKUP("u300-gpio", &gpio_clk), |
1231 | DEF_LOOKUP("rtc0", &rtc_clk), | 1268 | DEF_LOOKUP("rtc-coh901331", &rtc_clk), |
1232 | DEF_LOOKUP("bustr", &bustr_clk), | 1269 | DEF_LOOKUP("bustr", &bustr_clk), |
1233 | DEF_LOOKUP("evhist", &evhist_clk), | 1270 | DEF_LOOKUP("evhist", &evhist_clk), |
1234 | DEF_LOOKUP("timer", &timer_clk), | 1271 | DEF_LOOKUP("timer", &timer_clk), |
1235 | #ifdef CONFIG_MACH_U300_BS335 | 1272 | #ifdef CONFIG_MACH_U300_BS335 |
1236 | DEF_LOOKUP("ppm", &ppm_clk), | 1273 | DEF_LOOKUP("ppm", &ppm_clk), |
1237 | #endif | 1274 | #endif |
1238 | }; | 1275 | }; |
1239 | 1276 | ||
@@ -1427,16 +1464,20 @@ static const struct file_operations u300_clocks_operations = { | |||
1427 | .release = single_release, | 1464 | .release = single_release, |
1428 | }; | 1465 | }; |
1429 | 1466 | ||
1430 | static void init_clk_read_procfs(void) | 1467 | static int __init init_clk_read_debugfs(void) |
1431 | { | 1468 | { |
1432 | /* Expose a simple debugfs interface to view all clocks */ | 1469 | /* Expose a simple debugfs interface to view all clocks */ |
1433 | (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO, | 1470 | (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO, |
1434 | NULL, NULL, &u300_clocks_operations); | 1471 | NULL, NULL, |
1435 | } | 1472 | &u300_clocks_operations); |
1436 | #else | 1473 | return 0; |
1437 | static inline void init_clk_read_procfs(void) | ||
1438 | { | ||
1439 | } | 1474 | } |
1475 | /* | ||
1476 | * This needs to come in after the core_initcall() for the | ||
1477 | * overall clocks, because debugfs is not available until | ||
1478 | * the subsystems come up. | ||
1479 | */ | ||
1480 | module_init(init_clk_read_debugfs); | ||
1440 | #endif | 1481 | #endif |
1441 | 1482 | ||
1442 | static int __init u300_clock_init(void) | 1483 | static int __init u300_clock_init(void) |
@@ -1462,8 +1503,6 @@ static int __init u300_clock_init(void) | |||
1462 | 1503 | ||
1463 | clk_register(); | 1504 | clk_register(); |
1464 | 1505 | ||
1465 | init_clk_read_procfs(); | ||
1466 | |||
1467 | /* | 1506 | /* |
1468 | * Some of these may be on when we boot the system so make sure they | 1507 | * Some of these may be on when we boot the system so make sure they |
1469 | * are turned OFF. | 1508 | * are turned OFF. |