aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-tegra
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2012-09-21 00:27:41 -0400
committerOlof Johansson <olof@lixom.net>2012-09-21 00:27:41 -0400
commitb612a85792192b70e6497619521772c38ace758e (patch)
tree0405e78c23b600153bee5a0e19a5129ddca832f9 /arch/arm/mach-tegra
parentea832c41dacbc4a5f3888d9ef7c38213914aba2a (diff)
parent3aec092eed5d8d2b19a62b0aeed3acea9471099a (diff)
Merge branch 'next/soc' into next/multiplatform
* next/soc: (50 commits) ARM: OMAP: AM33xx hwmod: fixup SPI after platform_data move MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture ARM: bcm2835: instantiate console UART ARM: bcm2835: add stub clock driver ARM: bcm2835: add system timer ARM: bcm2835: add interrupt controller driver ARM: add infra-structure for BCM2835 and Raspberry Pi ARM: tegra20: add CPU hotplug support ARM: tegra30: add CPU hotplug support ARM: tegra: clean up the common assembly macros into sleep.h ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops ARM: tegra: introduce tegra_cpu_car_ops structures ARM: Tegra: Add smp_twd clock for Tegra20 ARM: AM33XX: clock: Add dcan clock aliases for device-tree ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions ARM: OMAP: omap_device: idle devices with no driver bound ARM: OMAP: omap_device: don't attempt late suspend if no driver bound ARM: OMAP: omap_device: keep track of driver bound status ARM: OMAP3+: hwmod: Add AM33XX HWMOD data ARM: OMAP2+: hwmod: Hook-up am33xx support in omap_hwmod framework ... Change/remove conflict in arch/arm/mach-ux500/clock.c resolved. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Makefile6
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c1
-rw-r--r--arch/arm/mach-tegra/clock.c574
-rw-r--r--arch/arm/mach-tegra/clock.h40
-rw-r--r--arch/arm/mach-tegra/common.c4
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c48
-rw-r--r--arch/arm/mach-tegra/headsmp.S6
-rw-r--r--arch/arm/mach-tegra/hotplug.c118
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h3
-rw-r--r--arch/arm/mach-tegra/platsmp.c29
-rw-r--r--arch/arm/mach-tegra/sleep-t20.S82
-rw-r--r--arch/arm/mach-tegra/sleep-t30.S107
-rw-r--r--arch/arm/mach-tegra/sleep.S33
-rw-r--r--arch/arm/mach-tegra/sleep.h85
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c1625
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.h42
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c1144
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2484
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c2511
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h53
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1372
-rw-r--r--arch/arm/mach-tegra/tegra_cpu_car.h87
22 files changed, 5592 insertions, 4862 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0974ace45558..04eb74e3f601 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,9 +12,13 @@ obj-y += powergate.o
12obj-y += apbio.o 12obj-y += apbio.o
13obj-$(CONFIG_CPU_IDLE) += cpuidle.o 13obj-$(CONFIG_CPU_IDLE) += cpuidle.o
14obj-$(CONFIG_CPU_IDLE) += sleep.o 14obj-$(CONFIG_CPU_IDLE) += sleep.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o
17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
21obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 22obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_SMP) += reset.o 23obj-$(CONFIG_SMP) += reset.o
20obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 24obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 37007d60bc37..5957ffbd4af6 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -70,6 +70,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
70 70
71static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 71static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
72 /* name parent rate enabled */ 72 /* name parent rate enabled */
73 { "uarta", "pll_p", 216000000, true },
73 { "uartd", "pll_p", 216000000, true }, 74 { "uartd", "pll_p", 216000000, true },
74 { "usbd", "clk_m", 12000000, false }, 75 { "usbd", "clk_m", 12000000, false },
75 { "usb2", "clk_m", 12000000, false }, 76 { "usb2", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c0819c..fd82085eca5d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2010 Google, Inc. 3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
4 * 5 *
5 * Author: 6 * Author:
6 * Colin Cross <ccross@google.com> 7 * Colin Cross <ccross@google.com>
@@ -19,8 +20,6 @@
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/clk.h> 21#include <linux/clk.h>
21#include <linux/clkdev.h> 22#include <linux/clkdev.h>
22#include <linux/debugfs.h>
23#include <linux/delay.h>
24#include <linux/init.h> 23#include <linux/init.h>
25#include <linux/list.h> 24#include <linux/list.h>
26#include <linux/module.h> 25#include <linux/module.h>
@@ -32,325 +31,75 @@
32 31
33#include "board.h" 32#include "board.h"
34#include "clock.h" 33#include "clock.h"
34#include "tegra_cpu_car.h"
35
36/* Global data of Tegra CPU CAR ops */
37struct tegra_cpu_car_ops *tegra_cpu_car_ops;
35 38
36/* 39/*
37 * Locking: 40 * Locking:
38 * 41 *
39 * Each struct clk has a spinlock.
40 *
41 * To avoid AB-BA locking problems, locks must always be traversed from child
42 * clock to parent clock. For example, when enabling a clock, the clock's lock
43 * is taken, and then clk_enable is called on the parent, which take's the
44 * parent clock's lock. There is one exceptions to this ordering: When dumping
45 * the clock tree through debugfs. In this case, clk_lock_all is called,
46 * which attemps to iterate through the entire list of clocks and take every
47 * clock lock. If any call to spin_trylock fails, all locked clocks are
48 * unlocked, and the process is retried. When all the locks are held,
49 * the only clock operation that can be called is clk_get_rate_all_locked.
50 *
51 * Within a single clock, no clock operation can call another clock operation
52 * on itself, except for clk_get_rate_locked and clk_set_rate_locked. Any
53 * clock operation can call any other clock operation on any of it's possible
54 * parents.
55 *
56 * An additional mutex, clock_list_lock, is used to protect the list of all 42 * An additional mutex, clock_list_lock, is used to protect the list of all
57 * clocks. 43 * clocks.
58 * 44 *
59 * The clock operations must lock internally to protect against
60 * read-modify-write on registers that are shared by multiple clocks
61 */ 45 */
62static DEFINE_MUTEX(clock_list_lock); 46static DEFINE_MUTEX(clock_list_lock);
63static LIST_HEAD(clocks); 47static LIST_HEAD(clocks);
64 48
65struct clk *tegra_get_clock_by_name(const char *name) 49void tegra_clk_add(struct clk *clk)
66{
67 struct clk *c;
68 struct clk *ret = NULL;
69 mutex_lock(&clock_list_lock);
70 list_for_each_entry(c, &clocks, node) {
71 if (strcmp(c->name, name) == 0) {
72 ret = c;
73 break;
74 }
75 }
76 mutex_unlock(&clock_list_lock);
77 return ret;
78}
79
80/* Must be called with c->spinlock held */
81static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
82{
83 u64 rate;
84
85 rate = clk_get_rate(p);
86
87 if (c->mul != 0 && c->div != 0) {
88 rate *= c->mul;
89 rate += c->div - 1; /* round up */
90 do_div(rate, c->div);
91 }
92
93 return rate;
94}
95
96/* Must be called with c->spinlock held */
97unsigned long clk_get_rate_locked(struct clk *c)
98{
99 unsigned long rate;
100
101 if (c->parent)
102 rate = clk_predict_rate_from_parent(c, c->parent);
103 else
104 rate = c->rate;
105
106 return rate;
107}
108
109unsigned long clk_get_rate(struct clk *c)
110{ 50{
111 unsigned long flags; 51 struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
112 unsigned long rate;
113
114 spin_lock_irqsave(&c->spinlock, flags);
115
116 rate = clk_get_rate_locked(c);
117
118 spin_unlock_irqrestore(&c->spinlock, flags);
119
120 return rate;
121}
122EXPORT_SYMBOL(clk_get_rate);
123
124int clk_reparent(struct clk *c, struct clk *parent)
125{
126 c->parent = parent;
127 return 0;
128}
129
130void clk_init(struct clk *c)
131{
132 spin_lock_init(&c->spinlock);
133
134 if (c->ops && c->ops->init)
135 c->ops->init(c);
136
137 if (!c->ops || !c->ops->enable) {
138 c->refcnt++;
139 c->set = true;
140 if (c->parent)
141 c->state = c->parent->state;
142 else
143 c->state = ON;
144 }
145 52
146 mutex_lock(&clock_list_lock); 53 mutex_lock(&clock_list_lock);
147 list_add(&c->node, &clocks); 54 list_add(&c->node, &clocks);
148 mutex_unlock(&clock_list_lock); 55 mutex_unlock(&clock_list_lock);
149} 56}
150 57
151int clk_enable(struct clk *c) 58struct clk *tegra_get_clock_by_name(const char *name)
152{
153 int ret = 0;
154 unsigned long flags;
155
156 spin_lock_irqsave(&c->spinlock, flags);
157
158 if (c->refcnt == 0) {
159 if (c->parent) {
160 ret = clk_enable(c->parent);
161 if (ret)
162 goto out;
163 }
164
165 if (c->ops && c->ops->enable) {
166 ret = c->ops->enable(c);
167 if (ret) {
168 if (c->parent)
169 clk_disable(c->parent);
170 goto out;
171 }
172 c->state = ON;
173 c->set = true;
174 }
175 }
176 c->refcnt++;
177out:
178 spin_unlock_irqrestore(&c->spinlock, flags);
179 return ret;
180}
181EXPORT_SYMBOL(clk_enable);
182
183void clk_disable(struct clk *c)
184{
185 unsigned long flags;
186
187 spin_lock_irqsave(&c->spinlock, flags);
188
189 if (c->refcnt == 0) {
190 WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
191 spin_unlock_irqrestore(&c->spinlock, flags);
192 return;
193 }
194 if (c->refcnt == 1) {
195 if (c->ops && c->ops->disable)
196 c->ops->disable(c);
197
198 if (c->parent)
199 clk_disable(c->parent);
200
201 c->state = OFF;
202 }
203 c->refcnt--;
204
205 spin_unlock_irqrestore(&c->spinlock, flags);
206}
207EXPORT_SYMBOL(clk_disable);
208
209int clk_set_parent(struct clk *c, struct clk *parent)
210{
211 int ret;
212 unsigned long flags;
213 unsigned long new_rate;
214 unsigned long old_rate;
215
216 spin_lock_irqsave(&c->spinlock, flags);
217
218 if (!c->ops || !c->ops->set_parent) {
219 ret = -ENOSYS;
220 goto out;
221 }
222
223 new_rate = clk_predict_rate_from_parent(c, parent);
224 old_rate = clk_get_rate_locked(c);
225
226 ret = c->ops->set_parent(c, parent);
227 if (ret)
228 goto out;
229
230out:
231 spin_unlock_irqrestore(&c->spinlock, flags);
232 return ret;
233}
234EXPORT_SYMBOL(clk_set_parent);
235
236struct clk *clk_get_parent(struct clk *c)
237{
238 return c->parent;
239}
240EXPORT_SYMBOL(clk_get_parent);
241
242int clk_set_rate_locked(struct clk *c, unsigned long rate)
243{
244 long new_rate;
245
246 if (!c->ops || !c->ops->set_rate)
247 return -ENOSYS;
248
249 if (rate > c->max_rate)
250 rate = c->max_rate;
251
252 if (c->ops && c->ops->round_rate) {
253 new_rate = c->ops->round_rate(c, rate);
254
255 if (new_rate < 0)
256 return new_rate;
257
258 rate = new_rate;
259 }
260
261 return c->ops->set_rate(c, rate);
262}
263
264int clk_set_rate(struct clk *c, unsigned long rate)
265{
266 int ret;
267 unsigned long flags;
268
269 spin_lock_irqsave(&c->spinlock, flags);
270
271 ret = clk_set_rate_locked(c, rate);
272
273 spin_unlock_irqrestore(&c->spinlock, flags);
274
275 return ret;
276}
277EXPORT_SYMBOL(clk_set_rate);
278
279
280/* Must be called with clocks lock and all indvidual clock locks held */
281unsigned long clk_get_rate_all_locked(struct clk *c)
282{ 59{
283 u64 rate; 60 struct clk_tegra *c;
284 int mul = 1; 61 struct clk *ret = NULL;
285 int div = 1; 62 mutex_lock(&clock_list_lock);
286 struct clk *p = c; 63 list_for_each_entry(c, &clocks, node) {
287 64 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
288 while (p) { 65 ret = c->hw.clk;
289 c = p; 66 break;
290 if (c->mul != 0 && c->div != 0) {
291 mul *= c->mul;
292 div *= c->div;
293 } 67 }
294 p = c->parent;
295 }
296
297 rate = c->rate;
298 rate *= mul;
299 do_div(rate, div);
300
301 return rate;
302}
303
304long clk_round_rate(struct clk *c, unsigned long rate)
305{
306 unsigned long flags;
307 long ret;
308
309 spin_lock_irqsave(&c->spinlock, flags);
310
311 if (!c->ops || !c->ops->round_rate) {
312 ret = -ENOSYS;
313 goto out;
314 } 68 }
315 69 mutex_unlock(&clock_list_lock);
316 if (rate > c->max_rate)
317 rate = c->max_rate;
318
319 ret = c->ops->round_rate(c, rate);
320
321out:
322 spin_unlock_irqrestore(&c->spinlock, flags);
323 return ret; 70 return ret;
324} 71}
325EXPORT_SYMBOL(clk_round_rate);
326 72
327static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table) 73static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
328{ 74{
329 struct clk *c; 75 struct clk *c;
330 struct clk *p; 76 struct clk *p;
77 struct clk *parent;
331 78
332 int ret = 0; 79 int ret = 0;
333 80
334 c = tegra_get_clock_by_name(table->name); 81 c = tegra_get_clock_by_name(table->name);
335 82
336 if (!c) { 83 if (!c) {
337 pr_warning("Unable to initialize clock %s\n", 84 pr_warn("Unable to initialize clock %s\n",
338 table->name); 85 table->name);
339 return -ENODEV; 86 return -ENODEV;
340 } 87 }
341 88
89 parent = clk_get_parent(c);
90
342 if (table->parent) { 91 if (table->parent) {
343 p = tegra_get_clock_by_name(table->parent); 92 p = tegra_get_clock_by_name(table->parent);
344 if (!p) { 93 if (!p) {
345 pr_warning("Unable to find parent %s of clock %s\n", 94 pr_warn("Unable to find parent %s of clock %s\n",
346 table->parent, table->name); 95 table->parent, table->name);
347 return -ENODEV; 96 return -ENODEV;
348 } 97 }
349 98
350 if (c->parent != p) { 99 if (parent != p) {
351 ret = clk_set_parent(c, p); 100 ret = clk_set_parent(c, p);
352 if (ret) { 101 if (ret) {
353 pr_warning("Unable to set parent %s of clock %s: %d\n", 102 pr_warn("Unable to set parent %s of clock %s: %d\n",
354 table->parent, table->name, ret); 103 table->parent, table->name, ret);
355 return -EINVAL; 104 return -EINVAL;
356 } 105 }
@@ -360,16 +109,16 @@ static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
360 if (table->rate && table->rate != clk_get_rate(c)) { 109 if (table->rate && table->rate != clk_get_rate(c)) {
361 ret = clk_set_rate(c, table->rate); 110 ret = clk_set_rate(c, table->rate);
362 if (ret) { 111 if (ret) {
363 pr_warning("Unable to set clock %s to rate %lu: %d\n", 112 pr_warn("Unable to set clock %s to rate %lu: %d\n",
364 table->name, table->rate, ret); 113 table->name, table->rate, ret);
365 return -EINVAL; 114 return -EINVAL;
366 } 115 }
367 } 116 }
368 117
369 if (table->enabled) { 118 if (table->enabled) {
370 ret = clk_enable(c); 119 ret = clk_prepare_enable(c);
371 if (ret) { 120 if (ret) {
372 pr_warning("Unable to enable clock %s: %d\n", 121 pr_warn("Unable to enable clock %s: %d\n",
373 table->name, ret); 122 table->name, ret);
374 return -EINVAL; 123 return -EINVAL;
375 } 124 }
@@ -383,19 +132,20 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
383 for (; table->name; table++) 132 for (; table->name; table++)
384 tegra_clk_init_one_from_table(table); 133 tegra_clk_init_one_from_table(table);
385} 134}
386EXPORT_SYMBOL(tegra_clk_init_from_table);
387 135
388void tegra_periph_reset_deassert(struct clk *c) 136void tegra_periph_reset_deassert(struct clk *c)
389{ 137{
390 BUG_ON(!c->ops->reset); 138 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
391 c->ops->reset(c, false); 139 BUG_ON(!clk->reset);
140 clk->reset(__clk_get_hw(c), false);
392} 141}
393EXPORT_SYMBOL(tegra_periph_reset_deassert); 142EXPORT_SYMBOL(tegra_periph_reset_deassert);
394 143
395void tegra_periph_reset_assert(struct clk *c) 144void tegra_periph_reset_assert(struct clk *c)
396{ 145{
397 BUG_ON(!c->ops->reset); 146 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
398 c->ops->reset(c, true); 147 BUG_ON(!clk->reset);
148 clk->reset(__clk_get_hw(c), true);
399} 149}
400EXPORT_SYMBOL(tegra_periph_reset_assert); 150EXPORT_SYMBOL(tegra_periph_reset_assert);
401 151
@@ -405,268 +155,14 @@ EXPORT_SYMBOL(tegra_periph_reset_assert);
405int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 155int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
406{ 156{
407 int ret = 0; 157 int ret = 0;
408 unsigned long flags; 158 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
409 159
410 spin_lock_irqsave(&c->spinlock, flags); 160 if (!clk->clk_cfg_ex) {
411
412 if (!c->ops || !c->ops->clk_cfg_ex) {
413 ret = -ENOSYS; 161 ret = -ENOSYS;
414 goto out; 162 goto out;
415 } 163 }
416 ret = c->ops->clk_cfg_ex(c, p, setting); 164 ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
417 165
418out: 166out:
419 spin_unlock_irqrestore(&c->spinlock, flags);
420
421 return ret; 167 return ret;
422} 168}
423
424#ifdef CONFIG_DEBUG_FS
425
426static int __clk_lock_all_spinlocks(void)
427{
428 struct clk *c;
429
430 list_for_each_entry(c, &clocks, node)
431 if (!spin_trylock(&c->spinlock))
432 goto unlock_spinlocks;
433
434 return 0;
435
436unlock_spinlocks:
437 list_for_each_entry_continue_reverse(c, &clocks, node)
438 spin_unlock(&c->spinlock);
439
440 return -EAGAIN;
441}
442
443static void __clk_unlock_all_spinlocks(void)
444{
445 struct clk *c;
446
447 list_for_each_entry_reverse(c, &clocks, node)
448 spin_unlock(&c->spinlock);
449}
450
451/*
452 * This function retries until it can take all locks, and may take
453 * an arbitrarily long time to complete.
454 * Must be called with irqs enabled, returns with irqs disabled
455 * Must be called with clock_list_lock held
456 */
457static void clk_lock_all(void)
458{
459 int ret;
460retry:
461 local_irq_disable();
462
463 ret = __clk_lock_all_spinlocks();
464 if (ret)
465 goto failed_spinlocks;
466
467 /* All locks taken successfully, return */
468 return;
469
470failed_spinlocks:
471 local_irq_enable();
472 yield();
473 goto retry;
474}
475
476/*
477 * Unlocks all clocks after a clk_lock_all
478 * Must be called with irqs disabled, returns with irqs enabled
479 * Must be called with clock_list_lock held
480 */
481static void clk_unlock_all(void)
482{
483 __clk_unlock_all_spinlocks();
484
485 local_irq_enable();
486}
487
488static struct dentry *clk_debugfs_root;
489
490
491static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
492{
493 struct clk *child;
494 const char *state = "uninit";
495 char div[8] = {0};
496
497 if (c->state == ON)
498 state = "on";
499 else if (c->state == OFF)
500 state = "off";
501
502 if (c->mul != 0 && c->div != 0) {
503 if (c->mul > c->div) {
504 int mul = c->mul / c->div;
505 int mul2 = (c->mul * 10 / c->div) % 10;
506 int mul3 = (c->mul * 10) % c->div;
507 if (mul2 == 0 && mul3 == 0)
508 snprintf(div, sizeof(div), "x%d", mul);
509 else if (mul3 == 0)
510 snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
511 else
512 snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
513 } else {
514 snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
515 (c->div % c->mul) ? ".5" : "");
516 }
517 }
518
519 seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
520 level * 3 + 1, "",
521 c->rate > c->max_rate ? '!' : ' ',
522 !c->set ? '*' : ' ',
523 30 - level * 3, c->name,
524 state, c->refcnt, div, clk_get_rate_all_locked(c));
525
526 list_for_each_entry(child, &clocks, node) {
527 if (child->parent != c)
528 continue;
529
530 clock_tree_show_one(s, child, level + 1);
531 }
532}
533
534static int clock_tree_show(struct seq_file *s, void *data)
535{
536 struct clk *c;
537 seq_printf(s, " clock state ref div rate\n");
538 seq_printf(s, "--------------------------------------------------------------\n");
539
540 mutex_lock(&clock_list_lock);
541
542 clk_lock_all();
543
544 list_for_each_entry(c, &clocks, node)
545 if (c->parent == NULL)
546 clock_tree_show_one(s, c, 0);
547
548 clk_unlock_all();
549
550 mutex_unlock(&clock_list_lock);
551 return 0;
552}
553
554static int clock_tree_open(struct inode *inode, struct file *file)
555{
556 return single_open(file, clock_tree_show, inode->i_private);
557}
558
559static const struct file_operations clock_tree_fops = {
560 .open = clock_tree_open,
561 .read = seq_read,
562 .llseek = seq_lseek,
563 .release = single_release,
564};
565
566static int possible_parents_show(struct seq_file *s, void *data)
567{
568 struct clk *c = s->private;
569 int i;
570
571 for (i = 0; c->inputs[i].input; i++) {
572 char *first = (i == 0) ? "" : " ";
573 seq_printf(s, "%s%s", first, c->inputs[i].input->name);
574 }
575 seq_printf(s, "\n");
576 return 0;
577}
578
579static int possible_parents_open(struct inode *inode, struct file *file)
580{
581 return single_open(file, possible_parents_show, inode->i_private);
582}
583
584static const struct file_operations possible_parents_fops = {
585 .open = possible_parents_open,
586 .read = seq_read,
587 .llseek = seq_lseek,
588 .release = single_release,
589};
590
591static int clk_debugfs_register_one(struct clk *c)
592{
593 struct dentry *d;
594
595 d = debugfs_create_dir(c->name, clk_debugfs_root);
596 if (!d)
597 return -ENOMEM;
598 c->dent = d;
599
600 d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
601 if (!d)
602 goto err_out;
603
604 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
605 if (!d)
606 goto err_out;
607
608 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
609 if (!d)
610 goto err_out;
611
612 if (c->inputs) {
613 d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
614 c, &possible_parents_fops);
615 if (!d)
616 goto err_out;
617 }
618
619 return 0;
620
621err_out:
622 debugfs_remove_recursive(c->dent);
623 return -ENOMEM;
624}
625
626static int clk_debugfs_register(struct clk *c)
627{
628 int err;
629 struct clk *pa = c->parent;
630
631 if (pa && !pa->dent) {
632 err = clk_debugfs_register(pa);
633 if (err)
634 return err;
635 }
636
637 if (!c->dent) {
638 err = clk_debugfs_register_one(c);
639 if (err)
640 return err;
641 }
642 return 0;
643}
644
645int __init tegra_clk_debugfs_init(void)
646{
647 struct clk *c;
648 struct dentry *d;
649 int err = -ENOMEM;
650
651 d = debugfs_create_dir("clock", NULL);
652 if (!d)
653 return -ENOMEM;
654 clk_debugfs_root = d;
655
656 d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
657 &clock_tree_fops);
658 if (!d)
659 goto err_out;
660
661 list_for_each_entry(c, &clocks, node) {
662 err = clk_debugfs_register(c);
663 if (err)
664 goto err_out;
665 }
666 return 0;
667err_out:
668 debugfs_remove_recursive(clk_debugfs_root);
669 return err;
670}
671
672#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc300657deba..2aa37f5c44c0 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/include/mach/clock.h 2 * arch/arm/mach-tegra/include/mach/clock.h
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * Author: 7 * Author:
7 * Colin Cross <ccross@google.com> 8 * Colin Cross <ccross@google.com>
@@ -20,9 +21,9 @@
20#ifndef __MACH_TEGRA_CLOCK_H 21#ifndef __MACH_TEGRA_CLOCK_H
21#define __MACH_TEGRA_CLOCK_H 22#define __MACH_TEGRA_CLOCK_H
22 23
24#include <linux/clk-provider.h>
23#include <linux/clkdev.h> 25#include <linux/clkdev.h>
24#include <linux/list.h> 26#include <linux/list.h>
25#include <linux/spinlock.h>
26 27
27#include <mach/clk.h> 28#include <mach/clk.h>
28 29
@@ -52,7 +53,8 @@
52#define ENABLE_ON_INIT (1 << 28) 53#define ENABLE_ON_INIT (1 << 28)
53#define PERIPH_ON_APB (1 << 29) 54#define PERIPH_ON_APB (1 << 29)
54 55
55struct clk; 56struct clk_tegra;
57#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
56 58
57struct clk_mux_sel { 59struct clk_mux_sel {
58 struct clk *input; 60 struct clk *input;
@@ -68,47 +70,29 @@ struct clk_pll_freq_table {
68 u8 cpcon; 70 u8 cpcon;
69}; 71};
70 72
71struct clk_ops {
72 void (*init)(struct clk *);
73 int (*enable)(struct clk *);
74 void (*disable)(struct clk *);
75 int (*set_parent)(struct clk *, struct clk *);
76 int (*set_rate)(struct clk *, unsigned long);
77 long (*round_rate)(struct clk *, unsigned long);
78 void (*reset)(struct clk *, bool);
79 int (*clk_cfg_ex)(struct clk *,
80 enum tegra_clk_ex_param, u32);
81};
82
83enum clk_state { 73enum clk_state {
84 UNINITIALIZED = 0, 74 UNINITIALIZED = 0,
85 ON, 75 ON,
86 OFF, 76 OFF,
87}; 77};
88 78
89struct clk { 79struct clk_tegra {
90 /* node for master clocks list */ 80 /* node for master clocks list */
91 struct list_head node; /* node for list of all clocks */ 81 struct list_head node; /* node for list of all clocks */
92 struct clk_lookup lookup; 82 struct clk_lookup lookup;
83 struct clk_hw hw;
93 84
94#ifdef CONFIG_DEBUG_FS
95 struct dentry *dent;
96#endif
97 bool set; 85 bool set;
98 struct clk_ops *ops; 86 unsigned long fixed_rate;
99 unsigned long rate;
100 unsigned long max_rate; 87 unsigned long max_rate;
101 unsigned long min_rate; 88 unsigned long min_rate;
102 u32 flags; 89 u32 flags;
103 const char *name; 90 const char *name;
104 91
105 u32 refcnt;
106 enum clk_state state; 92 enum clk_state state;
107 struct clk *parent;
108 u32 div; 93 u32 div;
109 u32 mul; 94 u32 mul;
110 95
111 const struct clk_mux_sel *inputs;
112 u32 reg; 96 u32 reg;
113 u32 reg_shift; 97 u32 reg_shift;
114 98
@@ -144,7 +128,8 @@ struct clk {
144 } shared_bus_user; 128 } shared_bus_user;
145 } u; 129 } u;
146 130
147 spinlock_t spinlock; 131 void (*reset)(struct clk_hw *, bool);
132 int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
148}; 133};
149 134
150struct clk_duplicate { 135struct clk_duplicate {
@@ -159,13 +144,10 @@ struct tegra_clk_init_table {
159 bool enabled; 144 bool enabled;
160}; 145};
161 146
147void tegra_clk_add(struct clk *c);
162void tegra2_init_clocks(void); 148void tegra2_init_clocks(void);
163void tegra30_init_clocks(void); 149void tegra30_init_clocks(void);
164void clk_init(struct clk *clk);
165struct clk *tegra_get_clock_by_name(const char *name); 150struct clk *tegra_get_clock_by_name(const char *name);
166int clk_reparent(struct clk *c, struct clk *parent);
167void tegra_clk_init_from_table(struct tegra_clk_init_table *table); 151void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
168unsigned long clk_get_rate_locked(struct clk *c);
169int clk_set_rate_locked(struct clk *c, unsigned long rate);
170 152
171#endif 153#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6bcc651..0560538bf598 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -34,6 +34,7 @@
34#include "fuse.h" 34#include "fuse.h"
35#include "pmc.h" 35#include "pmc.h"
36#include "apbio.h" 36#include "apbio.h"
37#include "sleep.h"
37 38
38/* 39/*
39 * Storage for debug-macro.S's state. 40 * Storage for debug-macro.S's state.
@@ -135,6 +136,7 @@ void __init tegra20_init_early(void)
135 tegra_init_cache(0x331, 0x441); 136 tegra_init_cache(0x331, 0x441);
136 tegra_pmc_init(); 137 tegra_pmc_init();
137 tegra_powergate_init(); 138 tegra_powergate_init();
139 tegra20_hotplug_init();
138} 140}
139#endif 141#endif
140#ifdef CONFIG_ARCH_TEGRA_3x_SOC 142#ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -147,11 +149,11 @@ void __init tegra30_init_early(void)
147 tegra_init_cache(0x441, 0x551); 149 tegra_init_cache(0x441, 0x551);
148 tegra_pmc_init(); 150 tegra_pmc_init();
149 tegra_powergate_init(); 151 tegra_powergate_init();
152 tegra30_hotplug_init();
150} 153}
151#endif 154#endif
152 155
153void __init tegra_init_late(void) 156void __init tegra_init_late(void)
154{ 157{
155 tegra_clk_debugfs_init();
156 tegra_powergate_debugfs_init(); 158 tegra_powergate_debugfs_init();
157} 159}
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ceb52db1e2f1..627bf0f4262e 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -49,6 +49,8 @@ static struct cpufreq_frequency_table freq_table[] = {
49#define NUM_CPUS 2 49#define NUM_CPUS 2
50 50
51static struct clk *cpu_clk; 51static struct clk *cpu_clk;
52static struct clk *pll_x_clk;
53static struct clk *pll_p_clk;
52static struct clk *emc_clk; 54static struct clk *emc_clk;
53 55
54static unsigned long target_cpu_speed[NUM_CPUS]; 56static unsigned long target_cpu_speed[NUM_CPUS];
@@ -71,6 +73,42 @@ static unsigned int tegra_getspeed(unsigned int cpu)
71 return rate; 73 return rate;
72} 74}
73 75
76static int tegra_cpu_clk_set_rate(unsigned long rate)
77{
78 int ret;
79
80 /*
81 * Take an extra reference to the main pll so it doesn't turn
82 * off when we move the cpu off of it
83 */
84 clk_prepare_enable(pll_x_clk);
85
86 ret = clk_set_parent(cpu_clk, pll_p_clk);
87 if (ret) {
88 pr_err("Failed to switch cpu to clock pll_p\n");
89 goto out;
90 }
91
92 if (rate == clk_get_rate(pll_p_clk))
93 goto out;
94
95 ret = clk_set_rate(pll_x_clk, rate);
96 if (ret) {
97 pr_err("Failed to change pll_x to %lu\n", rate);
98 goto out;
99 }
100
101 ret = clk_set_parent(cpu_clk, pll_x_clk);
102 if (ret) {
103 pr_err("Failed to switch cpu to clock pll_x\n");
104 goto out;
105 }
106
107out:
108 clk_disable_unprepare(pll_x_clk);
109 return ret;
110}
111
74static int tegra_update_cpu_speed(unsigned long rate) 112static int tegra_update_cpu_speed(unsigned long rate)
75{ 113{
76 int ret = 0; 114 int ret = 0;
@@ -101,7 +139,7 @@ static int tegra_update_cpu_speed(unsigned long rate)
101 freqs.old, freqs.new); 139 freqs.old, freqs.new);
102#endif 140#endif
103 141
104 ret = clk_set_rate(cpu_clk, freqs.new * 1000); 142 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
105 if (ret) { 143 if (ret) {
106 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n", 144 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
107 freqs.new); 145 freqs.new);
@@ -183,6 +221,14 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
183 if (IS_ERR(cpu_clk)) 221 if (IS_ERR(cpu_clk))
184 return PTR_ERR(cpu_clk); 222 return PTR_ERR(cpu_clk);
185 223
224 pll_x_clk = clk_get_sys(NULL, "pll_x");
225 if (IS_ERR(pll_x_clk))
226 return PTR_ERR(pll_x_clk);
227
228 pll_p_clk = clk_get_sys(NULL, "pll_p");
229 if (IS_ERR(pll_p_clk))
230 return PTR_ERR(pll_p_clk);
231
186 emc_clk = clk_get_sys("cpu", "emc"); 232 emc_clk = clk_get_sys("cpu", "emc");
187 if (IS_ERR(emc_clk)) { 233 if (IS_ERR(emc_clk)) {
188 clk_put(cpu_clk); 234 clk_put(cpu_clk);
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c51370..6addc78cb6b2 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
7 7
8#include "flowctrl.h" 8#include "flowctrl.h"
9#include "reset.h" 9#include "reset.h"
10#include "sleep.h"
10 11
11#define APB_MISC_GP_HIDREV 0x804 12#define APB_MISC_GP_HIDREV 0x804
12#define PMC_SCRATCH41 0x140 13#define PMC_SCRATCH41 0x140
13 14
14#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) 15#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
15 16
16 .macro mov32, reg, val
17 movw \reg, #:lower16:\val
18 movt \reg, #:upper16:\val
19 .endm
20
21 .section ".text.head", "ax" 17 .section ".text.head", "ax"
22 __CPUINIT 18 __CPUINIT
23 19
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9ddd6d18..d02a35476135 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,91 +1,23 @@
1/* 1/*
2 * linux/arch/arm/mach-realview/hotplug.c
3 * 2 *
4 * Copyright (C) 2002 ARM Ltd. 3 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved 4 * All Rights Reserved
5 * Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/smp.h> 12#include <linux/smp.h>
14 13
15#include <asm/cacheflush.h> 14#include <asm/cacheflush.h>
16#include <asm/cp15.h> 15#include <asm/smp_plat.h>
17 16
18static inline void cpu_enter_lowpower(void) 17#include "sleep.h"
19{ 18#include "tegra_cpu_car.h"
20 unsigned int v;
21
22 flush_cache_all();
23 asm volatile(
24 " mcr p15, 0, %1, c7, c5, 0\n"
25 " mcr p15, 0, %1, c7, c10, 4\n"
26 /*
27 * Turn off coherency
28 */
29 " mrc p15, 0, %0, c1, c0, 1\n"
30 " bic %0, %0, #0x20\n"
31 " mcr p15, 0, %0, c1, c0, 1\n"
32 " mrc p15, 0, %0, c1, c0, 0\n"
33 " bic %0, %0, %2\n"
34 " mcr p15, 0, %0, c1, c0, 0\n"
35 : "=&r" (v)
36 : "r" (0), "Ir" (CR_C)
37 : "cc");
38}
39
40static inline void cpu_leave_lowpower(void)
41{
42 unsigned int v;
43
44 asm volatile(
45 "mrc p15, 0, %0, c1, c0, 0\n"
46 " orr %0, %0, %1\n"
47 " mcr p15, 0, %0, c1, c0, 0\n"
48 " mrc p15, 0, %0, c1, c0, 1\n"
49 " orr %0, %0, #0x20\n"
50 " mcr p15, 0, %0, c1, c0, 1\n"
51 : "=&r" (v)
52 : "Ir" (CR_C)
53 : "cc");
54}
55
56static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
57{
58 /*
59 * there is no power-control hardware on this platform, so all
60 * we can do is put the core into WFI; this is safe as the calling
61 * code will have already disabled interrupts
62 */
63 for (;;) {
64 /*
65 * here's the WFI
66 */
67 asm(".word 0xe320f003\n"
68 :
69 :
70 : "memory", "cc");
71 19
72 /*if (pen_release == cpu) {*/ 20static void (*tegra_hotplug_shutdown)(void);
73 /*
74 * OK, proper wakeup, we're done
75 */
76 break;
77 /*}*/
78
79 /*
80 * Getting here, means that we have come out of WFI without
81 * having been woken up - this shouldn't happen
82 *
83 * Just note it happening - when we're woken, we can report
84 * its occurrence.
85 */
86 (*spurious)++;
87 }
88}
89 21
90int platform_cpu_kill(unsigned int cpu) 22int platform_cpu_kill(unsigned int cpu)
91{ 23{
@@ -99,22 +31,20 @@ int platform_cpu_kill(unsigned int cpu)
99 */ 31 */
100void platform_cpu_die(unsigned int cpu) 32void platform_cpu_die(unsigned int cpu)
101{ 33{
102 int spurious = 0; 34 cpu = cpu_logical_map(cpu);
103 35
104 /* 36 /* Flush the L1 data cache. */
105 * we're ready for shutdown now, so do it 37 flush_cache_all();
106 */
107 cpu_enter_lowpower();
108 platform_do_lowpower(cpu, &spurious);
109 38
110 /* 39 /* Shut down the current CPU. */
111 * bring this CPU back into the world of cache 40 tegra_hotplug_shutdown();
112 * coherency, and then restore interrupts
113 */
114 cpu_leave_lowpower();
115 41
116 if (spurious) 42 /* Clock gate the CPU */
117 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); 43 tegra_wait_cpu_in_reset(cpu);
44 tegra_disable_cpu_clock(cpu);
45
46 /* Should never return here. */
47 BUG();
118} 48}
119 49
120int platform_cpu_disable(unsigned int cpu) 50int platform_cpu_disable(unsigned int cpu)
@@ -125,3 +55,19 @@ int platform_cpu_disable(unsigned int cpu)
125 */ 55 */
126 return cpu == 0 ? -EPERM : 0; 56 return cpu == 0 ? -EPERM : 0;
127} 57}
58
59#ifdef CONFIG_ARCH_TEGRA_2x_SOC
60extern void tegra20_hotplug_shutdown(void);
61void __init tegra20_hotplug_init(void)
62{
63 tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
64}
65#endif
66
67#ifdef CONFIG_ARCH_TEGRA_3x_SOC
68extern void tegra30_hotplug_shutdown(void);
69void __init tegra30_hotplug_init(void)
70{
71 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
72}
73#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403303a0..95f3a547c770 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
34void tegra_periph_reset_deassert(struct clk *c); 34void tegra_periph_reset_deassert(struct clk *c);
35void tegra_periph_reset_assert(struct clk *c); 35void tegra_periph_reset_assert(struct clk *c);
36 36
37#ifndef CONFIG_COMMON_CLK
37unsigned long clk_get_rate_all_locked(struct clk *c); 38unsigned long clk_get_rate_all_locked(struct clk *c);
39#endif
40
38void tegra2_sdmmc_tap_delay(struct clk *c, int delay); 41void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
39int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting); 42int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
40 43
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208dbf682f..96ed1718eef0 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,7 @@
31#include "fuse.h" 31#include "fuse.h"
32#include "flowctrl.h" 32#include "flowctrl.h"
33#include "reset.h" 33#include "reset.h"
34#include "tegra_cpu_car.h"
34 35
35extern void tegra_secondary_startup(void); 36extern void tegra_secondary_startup(void);
36 37
@@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
38 39
39#define EVP_CPU_RESET_VECTOR \ 40#define EVP_CPU_RESET_VECTOR \
40 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) 41 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
41#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
42 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
43#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
44 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
45#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
46 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
47#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
48 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
49
50#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
51#define CPU_RESET(cpu) (0x1111ul<<(cpu))
52 42
53void __cpuinit platform_secondary_init(unsigned int cpu) 43void __cpuinit platform_secondary_init(unsigned int cpu)
54{ 44{
@@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
63 53
64static int tegra20_power_up_cpu(unsigned int cpu) 54static int tegra20_power_up_cpu(unsigned int cpu)
65{ 55{
66 u32 reg;
67
68 /* Enable the CPU clock. */ 56 /* Enable the CPU clock. */
69 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 57 tegra_enable_cpu_clock(cpu);
70 writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
71 barrier();
72 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
73 58
74 /* Clear flow controller CSR. */ 59 /* Clear flow controller CSR. */
75 flowctrl_write_cpu_csr(cpu, 0); 60 flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
79 64
80static int tegra30_power_up_cpu(unsigned int cpu) 65static int tegra30_power_up_cpu(unsigned int cpu)
81{ 66{
82 u32 reg;
83 int ret, pwrgateid; 67 int ret, pwrgateid;
84 unsigned long timeout; 68 unsigned long timeout;
85 69
@@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
103 } 87 }
104 88
105 /* CPU partition is powered. Enable the CPU clock. */ 89 /* CPU partition is powered. Enable the CPU clock. */
106 writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 90 tegra_enable_cpu_clock(cpu);
107 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
108 udelay(10); 91 udelay(10);
109 92
110 /* Remove I/O clamps. */ 93 /* Remove I/O clamps. */
@@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
128 * via the flow controller). This will have no effect on first boot 111 * via the flow controller). This will have no effect on first boot
129 * of the CPU since it should already be in reset. 112 * of the CPU since it should already be in reset.
130 */ 113 */
131 writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 114 tegra_put_cpu_in_reset(cpu);
132 dmb();
133 115
134 /* 116 /*
135 * Unhalt the CPU. If the flow controller was used to power-gate the 117 * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
155 goto done; 137 goto done;
156 138
157 /* Take the CPU out of reset. */ 139 /* Take the CPU out of reset. */
158 writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 140 tegra_cpu_out_of_reset(cpu);
159 wmb();
160done: 141done:
161 return status; 142 return status;
162} 143}
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 000000000000..a36ae413e2b8
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
1/*
2 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
3 * Copyright (c) 2011, Google, Inc.
4 *
5 * Author: Colin Cross <ccross@android.com>
6 * Gary King <gking@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/linkage.h>
22
23#include <asm/assembler.h>
24
25#include <mach/iomap.h>
26
27#include "sleep.h"
28#include "flowctrl.h"
29
30#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
31/*
32 * tegra20_hotplug_shutdown(void)
33 *
34 * puts the current cpu in reset
35 * should never return
36 */
37ENTRY(tegra20_hotplug_shutdown)
38 /* Turn off SMP coherency */
39 exit_smp r4, r5
40
41 /* Put this CPU down */
42 cpu_id r0
43 bl tegra20_cpu_shutdown
44 mov pc, lr @ should never get here
45ENDPROC(tegra20_hotplug_shutdown)
46
47/*
48 * tegra20_cpu_shutdown(int cpu)
49 *
50 * r0 is cpu to reset
51 *
52 * puts the specified CPU in wait-for-event mode on the flow controller
53 * and puts the CPU in reset
54 * can be called on the current cpu or another cpu
55 * if called on the current cpu, does not return
56 * MUST NOT BE CALLED FOR CPU 0.
57 *
58 * corrupts r0-r3, r12
59 */
60ENTRY(tegra20_cpu_shutdown)
61 cmp r0, #0
62 moveq pc, lr @ must not be called for CPU 0
63
64 cpu_to_halt_reg r1, r0
65 ldr r3, =TEGRA_FLOW_CTRL_VIRT
66 mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
67 str r2, [r3, r1] @ put flow controller in wait event mode
68 ldr r2, [r3, r1]
69 isb
70 dsb
71 movw r1, 0x1011
72 mov r1, r1, lsl r0
73 ldr r3, =TEGRA_CLK_RESET_VIRT
74 str r1, [r3, #0x340] @ put slave CPU in reset
75 isb
76 dsb
77 cpu_id r3
78 cmp r3, r0
79 beq .
80 mov pc, lr
81ENDPROC(tegra20_cpu_shutdown)
82#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 000000000000..777d9cee8b90
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
1/*
2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/linkage.h>
18
19#include <asm/assembler.h>
20
21#include <mach/iomap.h>
22
23#include "sleep.h"
24#include "flowctrl.h"
25
26#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
27
28#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
29/*
30 * tegra30_hotplug_shutdown(void)
31 *
32 * Powergates the current CPU.
33 * Should never return.
34 */
35ENTRY(tegra30_hotplug_shutdown)
36 /* Turn off SMP coherency */
37 exit_smp r4, r5
38
39 /* Powergate this CPU */
40 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
41 bl tegra30_cpu_shutdown
42 mov pc, lr @ should never get here
43ENDPROC(tegra30_hotplug_shutdown)
44
45/*
46 * tegra30_cpu_shutdown(unsigned long flags)
47 *
48 * Puts the current CPU in wait-for-event mode on the flow controller
49 * and powergates it -- flags (in R0) indicate the request type.
50 * Must never be called for CPU 0.
51 *
52 * corrupts r0-r4, r12
53 */
54ENTRY(tegra30_cpu_shutdown)
55 cpu_id r3
56 cmp r3, #0
57 moveq pc, lr @ Must never be called for CPU 0
58
59 ldr r12, =TEGRA_FLOW_CTRL_VIRT
60 cpu_to_csr_reg r1, r3
61 add r1, r1, r12 @ virtual CSR address for this CPU
62 cpu_to_halt_reg r2, r3
63 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
64
65 /*
66 * Clear this CPU's "event" and "interrupt" flags and power gate
67 * it when halting but not before it is in the "WFE" state.
68 */
69 movw r12, \
70 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
71 FLOW_CTRL_CSR_ENABLE
72 mov r4, #(1 << 4)
73 orr r12, r12, r4, lsl r3
74 str r12, [r1]
75
76 /* Halt this CPU. */
77 mov r3, #0x400
78delay_1:
79 subs r3, r3, #1 @ delay as a part of wfe war.
80 bge delay_1;
81 cpsid a @ disable imprecise aborts.
82 ldr r3, [r1] @ read CSR
83 str r3, [r1] @ clear CSR
84 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
85 movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
86 str r3, [r2]
87 ldr r0, [r2]
88 b wfe_war
89
90__cpu_reset_again:
91 dsb
92 .align 5
93 wfe @ CPU should be power gated here
94wfe_war:
95 b __cpu_reset_again
96
97 /*
98 * 38 nop's, which fills reset of wfe cache line and
99 * 4 more cachelines with nop
100 */
101 .rept 38
102 nop
103 .endr
104 b . @ should never get here
105
106ENDPROC(tegra30_cpu_shutdown)
107#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156a8011..ea81554c4833 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
29#include <mach/iomap.h> 29#include <mach/iomap.h>
30 30
31#include "flowctrl.h" 31#include "flowctrl.h"
32#include "sleep.h"
32 33
33#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
34 + IO_PPSB_VIRT)
35
36/* returns the offset of the flow controller halt register for a cpu */
37.macro cpu_to_halt_reg rd, rcpu
38 cmp \rcpu, #0
39 subne \rd, \rcpu, #1
40 movne \rd, \rd, lsl #3
41 addne \rd, \rd, #0x14
42 moveq \rd, #0
43.endm
44
45/* returns the offset of the flow controller csr register for a cpu */
46.macro cpu_to_csr_reg rd, rcpu
47 cmp \rcpu, #0
48 subne \rd, \rcpu, #1
49 movne \rd, \rd, lsl #3
50 addne \rd, \rd, #0x18
51 moveq \rd, #8
52.endm
53
54/* returns the ID of the current processor */
55.macro cpu_id, rd
56 mrc p15, 0, \rd, c0, c0, 5
57 and \rd, \rd, #0xF
58.endm
59
60/* loads a 32-bit value into a register without a data access */
61.macro mov32, reg, val
62 movw \reg, #:lower16:\val
63 movt \reg, #:upper16:\val
64.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 000000000000..e25a7cd703d9
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA_SLEEP_H
18#define __MACH_TEGRA_SLEEP_H
19
20#include <mach/iomap.h>
21
22#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
23 + IO_CPU_VIRT)
24#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
25 + IO_PPSB_VIRT)
26#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
27 + IO_PPSB_VIRT)
28
29#ifdef __ASSEMBLY__
30/* returns the offset of the flow controller halt register for a cpu */
31.macro cpu_to_halt_reg rd, rcpu
32 cmp \rcpu, #0
33 subne \rd, \rcpu, #1
34 movne \rd, \rd, lsl #3
35 addne \rd, \rd, #0x14
36 moveq \rd, #0
37.endm
38
39/* returns the offset of the flow controller csr register for a cpu */
40.macro cpu_to_csr_reg rd, rcpu
41 cmp \rcpu, #0
42 subne \rd, \rcpu, #1
43 movne \rd, \rd, lsl #3
44 addne \rd, \rd, #0x18
45 moveq \rd, #8
46.endm
47
48/* returns the ID of the current processor */
49.macro cpu_id, rd
50 mrc p15, 0, \rd, c0, c0, 5
51 and \rd, \rd, #0xF
52.endm
53
54/* loads a 32-bit value into a register without a data access */
55.macro mov32, reg, val
56 movw \reg, #:lower16:\val
57 movt \reg, #:upper16:\val
58.endm
59
60/* Macro to exit SMP coherency. */
61.macro exit_smp, tmp1, tmp2
62 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
63 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
64 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
65 isb
66 cpu_id \tmp1
67 mov \tmp1, \tmp1, lsl #2
68 mov \tmp2, #0xf
69 mov \tmp2, \tmp2, lsl \tmp1
70 mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
71 str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
72 dsb
73.endm
74#else
75
76#ifdef CONFIG_HOTPLUG_CPU
77void tegra20_hotplug_init(void);
78void tegra30_hotplug_init(void);
79#else
80static inline void tegra20_hotplug_init(void) {}
81static inline void tegra30_hotplug_init(void) {}
82#endif
83
84#endif
85#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
new file mode 100644
index 000000000000..9273b0dffc66
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -0,0 +1,1625 @@
1/*
2 * arch/arm/mach-tegra/tegra20_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clkdev.h>
28#include <linux/clk.h>
29
30#include <mach/iomap.h>
31#include <mach/suspend.h>
32
33#include "clock.h"
34#include "fuse.h"
35#include "tegra2_emc.h"
36#include "tegra_cpu_car.h"
37
38#define RST_DEVICES 0x004
39#define RST_DEVICES_SET 0x300
40#define RST_DEVICES_CLR 0x304
41#define RST_DEVICES_NUM 3
42
43#define CLK_OUT_ENB 0x010
44#define CLK_OUT_ENB_SET 0x320
45#define CLK_OUT_ENB_CLR 0x324
46#define CLK_OUT_ENB_NUM 3
47
48#define CLK_MASK_ARM 0x44
49#define MISC_CLK_ENB 0x48
50
51#define OSC_CTRL 0x50
52#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
53#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
54#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
55#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
56#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
57#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
58
59#define OSC_FREQ_DET 0x58
60#define OSC_FREQ_DET_TRIG (1<<31)
61
62#define OSC_FREQ_DET_STATUS 0x5C
63#define OSC_FREQ_DET_BUSY (1<<31)
64#define OSC_FREQ_DET_CNT_MASK 0xFFFF
65
66#define PERIPH_CLK_SOURCE_I2S1 0x100
67#define PERIPH_CLK_SOURCE_EMC 0x19c
68#define PERIPH_CLK_SOURCE_OSC 0x1fc
69#define PERIPH_CLK_SOURCE_NUM \
70 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
71
72#define PERIPH_CLK_SOURCE_MASK (3<<30)
73#define PERIPH_CLK_SOURCE_SHIFT 30
74#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
75#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
76#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
77#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
78#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
79#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
80
81#define SDMMC_CLK_INT_FB_SEL (1 << 23)
82#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
83#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
84
85#define PLL_BASE 0x0
86#define PLL_BASE_BYPASS (1<<31)
87#define PLL_BASE_ENABLE (1<<30)
88#define PLL_BASE_REF_ENABLE (1<<29)
89#define PLL_BASE_OVERRIDE (1<<28)
90#define PLL_BASE_DIVP_MASK (0x7<<20)
91#define PLL_BASE_DIVP_SHIFT 20
92#define PLL_BASE_DIVN_MASK (0x3FF<<8)
93#define PLL_BASE_DIVN_SHIFT 8
94#define PLL_BASE_DIVM_MASK (0x1F)
95#define PLL_BASE_DIVM_SHIFT 0
96
97#define PLL_OUT_RATIO_MASK (0xFF<<8)
98#define PLL_OUT_RATIO_SHIFT 8
99#define PLL_OUT_OVERRIDE (1<<2)
100#define PLL_OUT_CLKEN (1<<1)
101#define PLL_OUT_RESET_DISABLE (1<<0)
102
103#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
104
105#define PLL_MISC_DCCON_SHIFT 20
106#define PLL_MISC_CPCON_SHIFT 8
107#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
108#define PLL_MISC_LFCON_SHIFT 4
109#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
110#define PLL_MISC_VCOCON_SHIFT 0
111#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
112
113#define PLLU_BASE_POST_DIV (1<<20)
114
115#define PLLD_MISC_CLKENABLE (1<<30)
116#define PLLD_MISC_DIV_RST (1<<23)
117#define PLLD_MISC_DCCON_SHIFT 12
118
119#define PLLE_MISC_READY (1 << 15)
120
121#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
122#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
123#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
124
125#define SUPER_CLK_MUX 0x00
126#define SUPER_STATE_SHIFT 28
127#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
128#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
129#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
130#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
131#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
132#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
133#define SUPER_SOURCE_MASK 0xF
134#define SUPER_FIQ_SOURCE_SHIFT 12
135#define SUPER_IRQ_SOURCE_SHIFT 8
136#define SUPER_RUN_SOURCE_SHIFT 4
137#define SUPER_IDLE_SOURCE_SHIFT 0
138
139#define SUPER_CLK_DIVIDER 0x04
140
141#define BUS_CLK_DISABLE (1<<3)
142#define BUS_CLK_DIV_MASK 0x3
143
144#define PMC_CTRL 0x0
145 #define PMC_CTRL_BLINK_ENB (1 << 7)
146
147#define PMC_DPD_PADS_ORIDE 0x1c
148 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
149
150#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
151#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
152#define PMC_BLINK_TIMER_ENB (1 << 15)
153#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
154#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
155
156/* Tegra CPU clock and reset control regs */
157#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
158#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
159#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
160
161#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
162#define CPU_RESET(cpu) (0x1111ul << (cpu))
163
164static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
165static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
166
167/*
168 * Some clocks share a register with other clocks. Any clock op that
169 * non-atomically modifies a register used by another clock must lock
170 * clock_register_lock first.
171 */
172static DEFINE_SPINLOCK(clock_register_lock);
173
174/*
175 * Some peripheral clocks share an enable bit, so refcount the enable bits
176 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
177 */
178static int tegra_periph_clk_enable_refcount[3 * 32];
179
180#define clk_writel(value, reg) \
181 __raw_writel(value, reg_clk_base + (reg))
182#define clk_readl(reg) \
183 __raw_readl(reg_clk_base + (reg))
184#define pmc_writel(value, reg) \
185 __raw_writel(value, reg_pmc_base + (reg))
186#define pmc_readl(reg) \
187 __raw_readl(reg_pmc_base + (reg))
188
189static unsigned long clk_measure_input_freq(void)
190{
191 u32 clock_autodetect;
192 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
193 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
194 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
195 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
196 return 12000000;
197 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
198 return 13000000;
199 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
200 return 19200000;
201 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
202 return 26000000;
203 } else {
204 pr_err("%s: Unexpected clock autodetect value %d",
205 __func__, clock_autodetect);
206 BUG();
207 return 0;
208 }
209}
210
211static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
212{
213 s64 divider_u71 = parent_rate * 2;
214 divider_u71 += rate - 1;
215 do_div(divider_u71, rate);
216
217 if (divider_u71 - 2 < 0)
218 return 0;
219
220 if (divider_u71 - 2 > 255)
221 return -EINVAL;
222
223 return divider_u71 - 2;
224}
225
226static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
227{
228 s64 divider_u16;
229
230 divider_u16 = parent_rate;
231 divider_u16 += rate - 1;
232 do_div(divider_u16, rate);
233
234 if (divider_u16 - 1 < 0)
235 return 0;
236
237 if (divider_u16 - 1 > 0xFFFF)
238 return -EINVAL;
239
240 return divider_u16 - 1;
241}
242
243static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
244 unsigned long parent_rate)
245{
246 return to_clk_tegra(hw)->fixed_rate;
247}
248
249struct clk_ops tegra_clk_32k_ops = {
250 .recalc_rate = tegra_clk_fixed_recalc_rate,
251};
252
253/* clk_m functions */
254static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
255 unsigned long prate)
256{
257 if (!to_clk_tegra(hw)->fixed_rate)
258 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
259 return to_clk_tegra(hw)->fixed_rate;
260}
261
262static void tegra20_clk_m_init(struct clk_hw *hw)
263{
264 struct clk_tegra *c = to_clk_tegra(hw);
265 u32 osc_ctrl = clk_readl(OSC_CTRL);
266 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
267
268 switch (c->fixed_rate) {
269 case 12000000:
270 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
271 break;
272 case 13000000:
273 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
274 break;
275 case 19200000:
276 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
277 break;
278 case 26000000:
279 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
280 break;
281 default:
282 BUG();
283 }
284 clk_writel(auto_clock_control, OSC_CTRL);
285}
286
287struct clk_ops tegra_clk_m_ops = {
288 .init = tegra20_clk_m_init,
289 .recalc_rate = tegra20_clk_m_recalc_rate,
290};
291
292/* super clock functions */
293/* "super clocks" on tegra have two-stage muxes and a clock skipping
294 * super divider. We will ignore the clock skipping divider, since we
295 * can't lower the voltage when using the clock skip, but we can if we
296 * lower the PLL frequency.
297 */
298static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
299{
300 struct clk_tegra *c = to_clk_tegra(hw);
301 u32 val;
302
303 val = clk_readl(c->reg + SUPER_CLK_MUX);
304 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
305 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
306 c->state = ON;
307 return c->state;
308}
309
310static int tegra20_super_clk_enable(struct clk_hw *hw)
311{
312 struct clk_tegra *c = to_clk_tegra(hw);
313 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
314 return 0;
315}
316
317static void tegra20_super_clk_disable(struct clk_hw *hw)
318{
319 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
320
321 /* oops - don't disable the CPU clock! */
322 BUG();
323}
324
325static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
326{
327 struct clk_tegra *c = to_clk_tegra(hw);
328 int val = clk_readl(c->reg + SUPER_CLK_MUX);
329 int source;
330 int shift;
331
332 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
333 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
334 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
335 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
336 source = (val >> shift) & SUPER_SOURCE_MASK;
337 return source;
338}
339
340static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
341{
342 struct clk_tegra *c = to_clk_tegra(hw);
343 u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
344 int shift;
345
346 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
347 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
348 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
349 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
350 val &= ~(SUPER_SOURCE_MASK << shift);
351 val |= index << shift;
352
353 clk_writel(val, c->reg);
354
355 return 0;
356}
357
358/* FIX ME: Need to switch parents to change the source PLL rate */
359static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
360 unsigned long prate)
361{
362 return prate;
363}
364
365static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
366 unsigned long *prate)
367{
368 return *prate;
369}
370
371static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
372 unsigned long parent_rate)
373{
374 return 0;
375}
376
377struct clk_ops tegra_super_ops = {
378 .is_enabled = tegra20_super_clk_is_enabled,
379 .enable = tegra20_super_clk_enable,
380 .disable = tegra20_super_clk_disable,
381 .set_parent = tegra20_super_clk_set_parent,
382 .get_parent = tegra20_super_clk_get_parent,
383 .set_rate = tegra20_super_clk_set_rate,
384 .round_rate = tegra20_super_clk_round_rate,
385 .recalc_rate = tegra20_super_clk_recalc_rate,
386};
387
388static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
389 unsigned long parent_rate)
390{
391 struct clk_tegra *c = to_clk_tegra(hw);
392 u64 rate = parent_rate;
393
394 if (c->mul != 0 && c->div != 0) {
395 rate *= c->mul;
396 rate += c->div - 1; /* round up */
397 do_div(rate, c->div);
398 }
399
400 return rate;
401}
402
403struct clk_ops tegra_twd_ops = {
404 .recalc_rate = tegra20_twd_clk_recalc_rate,
405};
406
407static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
408{
409 return 0;
410}
411
412struct clk_ops tegra_cop_ops = {
413 .get_parent = tegra20_cop_clk_get_parent,
414};
415
416/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
417 * reset the COP block (i.e. AVP) */
418void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
419{
420 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
421
422 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
423 clk_writel(1 << 1, reg);
424}
425
426/* bus clock functions */
427static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
428{
429 struct clk_tegra *c = to_clk_tegra(hw);
430 u32 val = clk_readl(c->reg);
431
432 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
433 return c->state;
434}
435
436static int tegra20_bus_clk_enable(struct clk_hw *hw)
437{
438 struct clk_tegra *c = to_clk_tegra(hw);
439 unsigned long flags;
440 u32 val;
441
442 spin_lock_irqsave(&clock_register_lock, flags);
443
444 val = clk_readl(c->reg);
445 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
446 clk_writel(val, c->reg);
447
448 spin_unlock_irqrestore(&clock_register_lock, flags);
449
450 return 0;
451}
452
453static void tegra20_bus_clk_disable(struct clk_hw *hw)
454{
455 struct clk_tegra *c = to_clk_tegra(hw);
456 unsigned long flags;
457 u32 val;
458
459 spin_lock_irqsave(&clock_register_lock, flags);
460
461 val = clk_readl(c->reg);
462 val |= BUS_CLK_DISABLE << c->reg_shift;
463 clk_writel(val, c->reg);
464
465 spin_unlock_irqrestore(&clock_register_lock, flags);
466}
467
468static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
469 unsigned long prate)
470{
471 struct clk_tegra *c = to_clk_tegra(hw);
472 u32 val = clk_readl(c->reg);
473 u64 rate = prate;
474
475 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
476 c->mul = 1;
477
478 if (c->mul != 0 && c->div != 0) {
479 rate *= c->mul;
480 rate += c->div - 1; /* round up */
481 do_div(rate, c->div);
482 }
483 return rate;
484}
485
486static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
487 unsigned long parent_rate)
488{
489 struct clk_tegra *c = to_clk_tegra(hw);
490 int ret = -EINVAL;
491 unsigned long flags;
492 u32 val;
493 int i;
494
495 spin_lock_irqsave(&clock_register_lock, flags);
496
497 val = clk_readl(c->reg);
498 for (i = 1; i <= 4; i++) {
499 if (rate == parent_rate / i) {
500 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
501 val |= (i - 1) << c->reg_shift;
502 clk_writel(val, c->reg);
503 c->div = i;
504 c->mul = 1;
505 ret = 0;
506 break;
507 }
508 }
509
510 spin_unlock_irqrestore(&clock_register_lock, flags);
511
512 return ret;
513}
514
515static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
516 unsigned long *prate)
517{
518 unsigned long parent_rate = *prate;
519 s64 divider;
520
521 if (rate >= parent_rate)
522 return rate;
523
524 divider = parent_rate;
525 divider += rate - 1;
526 do_div(divider, rate);
527
528 if (divider < 0)
529 return divider;
530
531 if (divider > 4)
532 divider = 4;
533 do_div(parent_rate, divider);
534
535 return parent_rate;
536}
537
538struct clk_ops tegra_bus_ops = {
539 .is_enabled = tegra20_bus_clk_is_enabled,
540 .enable = tegra20_bus_clk_enable,
541 .disable = tegra20_bus_clk_disable,
542 .set_rate = tegra20_bus_clk_set_rate,
543 .round_rate = tegra20_bus_clk_round_rate,
544 .recalc_rate = tegra20_bus_clk_recalc_rate,
545};
546
547/* Blink output functions */
548static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
549{
550 struct clk_tegra *c = to_clk_tegra(hw);
551 u32 val;
552
553 val = pmc_readl(PMC_CTRL);
554 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
555 return c->state;
556}
557
558static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
559 unsigned long prate)
560{
561 struct clk_tegra *c = to_clk_tegra(hw);
562 u64 rate = prate;
563 u32 val;
564
565 c->mul = 1;
566 val = pmc_readl(c->reg);
567
568 if (val & PMC_BLINK_TIMER_ENB) {
569 unsigned int on_off;
570
571 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
572 PMC_BLINK_TIMER_DATA_ON_MASK;
573 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
574 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
575 on_off += val;
576 /* each tick in the blink timer is 4 32KHz clocks */
577 c->div = on_off * 4;
578 } else {
579 c->div = 1;
580 }
581
582 if (c->mul != 0 && c->div != 0) {
583 rate *= c->mul;
584 rate += c->div - 1; /* round up */
585 do_div(rate, c->div);
586 }
587 return rate;
588}
589
590static int tegra20_blink_clk_enable(struct clk_hw *hw)
591{
592 u32 val;
593
594 val = pmc_readl(PMC_DPD_PADS_ORIDE);
595 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
596
597 val = pmc_readl(PMC_CTRL);
598 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
599
600 return 0;
601}
602
603static void tegra20_blink_clk_disable(struct clk_hw *hw)
604{
605 u32 val;
606
607 val = pmc_readl(PMC_CTRL);
608 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
609
610 val = pmc_readl(PMC_DPD_PADS_ORIDE);
611 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
612}
613
614static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
615 unsigned long parent_rate)
616{
617 struct clk_tegra *c = to_clk_tegra(hw);
618
619 if (rate >= parent_rate) {
620 c->div = 1;
621 pmc_writel(0, c->reg);
622 } else {
623 unsigned int on_off;
624 u32 val;
625
626 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
627 c->div = on_off * 8;
628
629 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
630 PMC_BLINK_TIMER_DATA_ON_SHIFT;
631 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
632 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
633 val |= on_off;
634 val |= PMC_BLINK_TIMER_ENB;
635 pmc_writel(val, c->reg);
636 }
637
638 return 0;
639}
640
641static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
642 unsigned long *prate)
643{
644 int div;
645 int mul;
646 long round_rate = *prate;
647
648 mul = 1;
649
650 if (rate >= *prate) {
651 div = 1;
652 } else {
653 div = DIV_ROUND_UP(*prate / 8, rate);
654 div *= 8;
655 }
656
657 round_rate *= mul;
658 round_rate += div - 1;
659 do_div(round_rate, div);
660
661 return round_rate;
662}
663
664struct clk_ops tegra_blink_clk_ops = {
665 .is_enabled = tegra20_blink_clk_is_enabled,
666 .enable = tegra20_blink_clk_enable,
667 .disable = tegra20_blink_clk_disable,
668 .set_rate = tegra20_blink_clk_set_rate,
669 .round_rate = tegra20_blink_clk_round_rate,
670 .recalc_rate = tegra20_blink_clk_recalc_rate,
671};
672
673/* PLL Functions */
674static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
675{
676 udelay(c->u.pll.lock_delay);
677 return 0;
678}
679
680static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
681{
682 struct clk_tegra *c = to_clk_tegra(hw);
683 u32 val = clk_readl(c->reg + PLL_BASE);
684
685 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
686 return c->state;
687}
688
689static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
690 unsigned long prate)
691{
692 struct clk_tegra *c = to_clk_tegra(hw);
693 u32 val = clk_readl(c->reg + PLL_BASE);
694 u64 rate = prate;
695
696 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
697 const struct clk_pll_freq_table *sel;
698 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
699 if (sel->input_rate == prate &&
700 sel->output_rate == c->u.pll.fixed_rate) {
701 c->mul = sel->n;
702 c->div = sel->m * sel->p;
703 break;
704 }
705 }
706 pr_err("Clock %s has unknown fixed frequency\n",
707 __clk_get_name(hw->clk));
708 BUG();
709 } else if (val & PLL_BASE_BYPASS) {
710 c->mul = 1;
711 c->div = 1;
712 } else {
713 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
714 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
715 if (c->flags & PLLU)
716 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
717 else
718 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
719 }
720
721 if (c->mul != 0 && c->div != 0) {
722 rate *= c->mul;
723 rate += c->div - 1; /* round up */
724 do_div(rate, c->div);
725 }
726 return rate;
727}
728
729static int tegra20_pll_clk_enable(struct clk_hw *hw)
730{
731 struct clk_tegra *c = to_clk_tegra(hw);
732 u32 val;
733 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
734
735 val = clk_readl(c->reg + PLL_BASE);
736 val &= ~PLL_BASE_BYPASS;
737 val |= PLL_BASE_ENABLE;
738 clk_writel(val, c->reg + PLL_BASE);
739
740 tegra20_pll_clk_wait_for_lock(c);
741
742 return 0;
743}
744
745static void tegra20_pll_clk_disable(struct clk_hw *hw)
746{
747 struct clk_tegra *c = to_clk_tegra(hw);
748 u32 val;
749 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
750
751 val = clk_readl(c->reg);
752 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
753 clk_writel(val, c->reg);
754}
755
756static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
757 unsigned long parent_rate)
758{
759 struct clk_tegra *c = to_clk_tegra(hw);
760 unsigned long input_rate = parent_rate;
761 const struct clk_pll_freq_table *sel;
762 u32 val;
763
764 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
765
766 if (c->flags & PLL_FIXED) {
767 int ret = 0;
768 if (rate != c->u.pll.fixed_rate) {
769 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
770 __func__, __clk_get_name(hw->clk),
771 c->u.pll.fixed_rate, rate);
772 ret = -EINVAL;
773 }
774 return ret;
775 }
776
777 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
778 if (sel->input_rate == input_rate && sel->output_rate == rate) {
779 c->mul = sel->n;
780 c->div = sel->m * sel->p;
781
782 val = clk_readl(c->reg + PLL_BASE);
783 if (c->flags & PLL_FIXED)
784 val |= PLL_BASE_OVERRIDE;
785 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
786 PLL_BASE_DIVM_MASK);
787 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
788 (sel->n << PLL_BASE_DIVN_SHIFT);
789 BUG_ON(sel->p < 1 || sel->p > 2);
790 if (c->flags & PLLU) {
791 if (sel->p == 1)
792 val |= PLLU_BASE_POST_DIV;
793 } else {
794 if (sel->p == 2)
795 val |= 1 << PLL_BASE_DIVP_SHIFT;
796 }
797 clk_writel(val, c->reg + PLL_BASE);
798
799 if (c->flags & PLL_HAS_CPCON) {
800 val = clk_readl(c->reg + PLL_MISC(c));
801 val &= ~PLL_MISC_CPCON_MASK;
802 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
803 clk_writel(val, c->reg + PLL_MISC(c));
804 }
805
806 if (c->state == ON)
807 tegra20_pll_clk_enable(hw);
808 return 0;
809 }
810 }
811 return -EINVAL;
812}
813
814static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
815 unsigned long *prate)
816{
817 struct clk_tegra *c = to_clk_tegra(hw);
818 const struct clk_pll_freq_table *sel;
819 unsigned long input_rate = *prate;
820 u64 output_rate = *prate;
821 int mul;
822 int div;
823
824 if (c->flags & PLL_FIXED)
825 return c->u.pll.fixed_rate;
826
827 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
828 if (sel->input_rate == input_rate && sel->output_rate == rate) {
829 mul = sel->n;
830 div = sel->m * sel->p;
831 break;
832 }
833
834 if (sel->input_rate == 0)
835 return -EINVAL;
836
837 output_rate *= mul;
838 output_rate += div - 1; /* round up */
839 do_div(output_rate, div);
840
841 return output_rate;
842}
843
844struct clk_ops tegra_pll_ops = {
845 .is_enabled = tegra20_pll_clk_is_enabled,
846 .enable = tegra20_pll_clk_enable,
847 .disable = tegra20_pll_clk_disable,
848 .set_rate = tegra20_pll_clk_set_rate,
849 .recalc_rate = tegra20_pll_clk_recalc_rate,
850 .round_rate = tegra20_pll_clk_round_rate,
851};
852
853static void tegra20_pllx_clk_init(struct clk_hw *hw)
854{
855 struct clk_tegra *c = to_clk_tegra(hw);
856
857 if (tegra_sku_id == 7)
858 c->max_rate = 750000000;
859}
860
861struct clk_ops tegra_pllx_ops = {
862 .init = tegra20_pllx_clk_init,
863 .is_enabled = tegra20_pll_clk_is_enabled,
864 .enable = tegra20_pll_clk_enable,
865 .disable = tegra20_pll_clk_disable,
866 .set_rate = tegra20_pll_clk_set_rate,
867 .recalc_rate = tegra20_pll_clk_recalc_rate,
868 .round_rate = tegra20_pll_clk_round_rate,
869};
870
871static int tegra20_plle_clk_enable(struct clk_hw *hw)
872{
873 struct clk_tegra *c = to_clk_tegra(hw);
874 u32 val;
875
876 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
877
878 mdelay(1);
879
880 val = clk_readl(c->reg + PLL_BASE);
881 if (!(val & PLLE_MISC_READY))
882 return -EBUSY;
883
884 val = clk_readl(c->reg + PLL_BASE);
885 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
886 clk_writel(val, c->reg + PLL_BASE);
887
888 return 0;
889}
890
891struct clk_ops tegra_plle_ops = {
892 .is_enabled = tegra20_pll_clk_is_enabled,
893 .enable = tegra20_plle_clk_enable,
894 .set_rate = tegra20_pll_clk_set_rate,
895 .recalc_rate = tegra20_pll_clk_recalc_rate,
896 .round_rate = tegra20_pll_clk_round_rate,
897};
898
899/* Clock divider ops */
900static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
901{
902 struct clk_tegra *c = to_clk_tegra(hw);
903 u32 val = clk_readl(c->reg);
904
905 val >>= c->reg_shift;
906 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
907 if (!(val & PLL_OUT_RESET_DISABLE))
908 c->state = OFF;
909 return c->state;
910}
911
912static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
913 unsigned long prate)
914{
915 struct clk_tegra *c = to_clk_tegra(hw);
916 u64 rate = prate;
917 u32 val = clk_readl(c->reg);
918 u32 divu71;
919
920 val >>= c->reg_shift;
921
922 if (c->flags & DIV_U71) {
923 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
924 c->div = (divu71 + 2);
925 c->mul = 2;
926 } else if (c->flags & DIV_2) {
927 c->div = 2;
928 c->mul = 1;
929 } else {
930 c->div = 1;
931 c->mul = 1;
932 }
933
934 rate *= c->mul;
935 rate += c->div - 1; /* round up */
936 do_div(rate, c->div);
937
938 return rate;
939}
940
941static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
942{
943 struct clk_tegra *c = to_clk_tegra(hw);
944 unsigned long flags;
945 u32 new_val;
946 u32 val;
947
948 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
949
950 if (c->flags & DIV_U71) {
951 spin_lock_irqsave(&clock_register_lock, flags);
952 val = clk_readl(c->reg);
953 new_val = val >> c->reg_shift;
954 new_val &= 0xFFFF;
955
956 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
957
958 val &= ~(0xFFFF << c->reg_shift);
959 val |= new_val << c->reg_shift;
960 clk_writel(val, c->reg);
961 spin_unlock_irqrestore(&clock_register_lock, flags);
962 return 0;
963 } else if (c->flags & DIV_2) {
964 BUG_ON(!(c->flags & PLLD));
965 spin_lock_irqsave(&clock_register_lock, flags);
966 val = clk_readl(c->reg);
967 val &= ~PLLD_MISC_DIV_RST;
968 clk_writel(val, c->reg);
969 spin_unlock_irqrestore(&clock_register_lock, flags);
970 return 0;
971 }
972 return -EINVAL;
973}
974
975static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
976{
977 struct clk_tegra *c = to_clk_tegra(hw);
978 unsigned long flags;
979 u32 new_val;
980 u32 val;
981
982 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
983
984 if (c->flags & DIV_U71) {
985 spin_lock_irqsave(&clock_register_lock, flags);
986 val = clk_readl(c->reg);
987 new_val = val >> c->reg_shift;
988 new_val &= 0xFFFF;
989
990 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
991
992 val &= ~(0xFFFF << c->reg_shift);
993 val |= new_val << c->reg_shift;
994 clk_writel(val, c->reg);
995 spin_unlock_irqrestore(&clock_register_lock, flags);
996 } else if (c->flags & DIV_2) {
997 BUG_ON(!(c->flags & PLLD));
998 spin_lock_irqsave(&clock_register_lock, flags);
999 val = clk_readl(c->reg);
1000 val |= PLLD_MISC_DIV_RST;
1001 clk_writel(val, c->reg);
1002 spin_unlock_irqrestore(&clock_register_lock, flags);
1003 }
1004}
1005
1006static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1007 unsigned long parent_rate)
1008{
1009 struct clk_tegra *c = to_clk_tegra(hw);
1010 unsigned long flags;
1011 int divider_u71;
1012 u32 new_val;
1013 u32 val;
1014
1015 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1016
1017 if (c->flags & DIV_U71) {
1018 divider_u71 = clk_div71_get_divider(parent_rate, rate);
1019 if (divider_u71 >= 0) {
1020 spin_lock_irqsave(&clock_register_lock, flags);
1021 val = clk_readl(c->reg);
1022 new_val = val >> c->reg_shift;
1023 new_val &= 0xFFFF;
1024 if (c->flags & DIV_U71_FIXED)
1025 new_val |= PLL_OUT_OVERRIDE;
1026 new_val &= ~PLL_OUT_RATIO_MASK;
1027 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1028
1029 val &= ~(0xFFFF << c->reg_shift);
1030 val |= new_val << c->reg_shift;
1031 clk_writel(val, c->reg);
1032 c->div = divider_u71 + 2;
1033 c->mul = 2;
1034 spin_unlock_irqrestore(&clock_register_lock, flags);
1035 return 0;
1036 }
1037 } else if (c->flags & DIV_2) {
1038 if (parent_rate == rate * 2)
1039 return 0;
1040 }
1041 return -EINVAL;
1042}
1043
1044static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1045 unsigned long *prate)
1046{
1047 struct clk_tegra *c = to_clk_tegra(hw);
1048 unsigned long parent_rate = *prate;
1049 int divider;
1050
1051 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1052
1053 if (c->flags & DIV_U71) {
1054 divider = clk_div71_get_divider(parent_rate, rate);
1055 if (divider < 0)
1056 return divider;
1057 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1058 } else if (c->flags & DIV_2) {
1059 return DIV_ROUND_UP(parent_rate, 2);
1060 }
1061 return -EINVAL;
1062}
1063
1064struct clk_ops tegra_pll_div_ops = {
1065 .is_enabled = tegra20_pll_div_clk_is_enabled,
1066 .enable = tegra20_pll_div_clk_enable,
1067 .disable = tegra20_pll_div_clk_disable,
1068 .set_rate = tegra20_pll_div_clk_set_rate,
1069 .round_rate = tegra20_pll_div_clk_round_rate,
1070 .recalc_rate = tegra20_pll_div_clk_recalc_rate,
1071};
1072
1073/* Periph clk ops */
1074
1075static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
1076{
1077 struct clk_tegra *c = to_clk_tegra(hw);
1078
1079 c->state = ON;
1080
1081 if (!c->u.periph.clk_num)
1082 goto out;
1083
1084 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1085 PERIPH_CLK_TO_ENB_BIT(c)))
1086 c->state = OFF;
1087
1088 if (!(c->flags & PERIPH_NO_RESET))
1089 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
1090 PERIPH_CLK_TO_ENB_BIT(c))
1091 c->state = OFF;
1092
1093out:
1094 return c->state;
1095}
1096
1097static int tegra20_periph_clk_enable(struct clk_hw *hw)
1098{
1099 struct clk_tegra *c = to_clk_tegra(hw);
1100 unsigned long flags;
1101 u32 val;
1102
1103 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1104
1105 if (!c->u.periph.clk_num)
1106 return 0;
1107
1108 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1109 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1110 return 0;
1111
1112 spin_lock_irqsave(&clock_register_lock, flags);
1113
1114 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1115 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1116 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
1117 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1118 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1119 if (c->flags & PERIPH_EMC_ENB) {
1120 /* The EMC peripheral clock has 2 extra enable bits */
1121 /* FIXME: Do they need to be disabled? */
1122 val = clk_readl(c->reg);
1123 val |= 0x3 << 24;
1124 clk_writel(val, c->reg);
1125 }
1126
1127 spin_unlock_irqrestore(&clock_register_lock, flags);
1128
1129 return 0;
1130}
1131
1132static void tegra20_periph_clk_disable(struct clk_hw *hw)
1133{
1134 struct clk_tegra *c = to_clk_tegra(hw);
1135 unsigned long flags;
1136
1137 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1138
1139 if (!c->u.periph.clk_num)
1140 return;
1141
1142 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1143
1144 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1145 return;
1146
1147 spin_lock_irqsave(&clock_register_lock, flags);
1148
1149 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1150 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1151
1152 spin_unlock_irqrestore(&clock_register_lock, flags);
1153}
1154
1155void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
1156{
1157 struct clk_tegra *c = to_clk_tegra(hw);
1158 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1159
1160 pr_debug("%s %s on clock %s\n", __func__,
1161 assert ? "assert" : "deassert", __clk_get_name(hw->clk));
1162
1163 BUG_ON(!c->u.periph.clk_num);
1164
1165 if (!(c->flags & PERIPH_NO_RESET))
1166 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1167 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1168}
1169
1170static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1171{
1172 struct clk_tegra *c = to_clk_tegra(hw);
1173 u32 val;
1174 u32 mask;
1175 u32 shift;
1176
1177 pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
1178
1179 if (c->flags & MUX_PWM) {
1180 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1181 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1182 } else {
1183 shift = PERIPH_CLK_SOURCE_SHIFT;
1184 mask = PERIPH_CLK_SOURCE_MASK;
1185 }
1186
1187 val = clk_readl(c->reg);
1188 val &= ~mask;
1189 val |= (index) << shift;
1190
1191 clk_writel(val, c->reg);
1192
1193 return 0;
1194}
1195
1196static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
1197{
1198 struct clk_tegra *c = to_clk_tegra(hw);
1199 u32 val = clk_readl(c->reg);
1200 u32 mask;
1201 u32 shift;
1202
1203 if (c->flags & MUX_PWM) {
1204 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1205 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1206 } else {
1207 shift = PERIPH_CLK_SOURCE_SHIFT;
1208 mask = PERIPH_CLK_SOURCE_MASK;
1209 }
1210
1211 if (c->flags & MUX)
1212 return (val & mask) >> shift;
1213 else
1214 return 0;
1215}
1216
1217static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
1218 unsigned long prate)
1219{
1220 struct clk_tegra *c = to_clk_tegra(hw);
1221 unsigned long rate = prate;
1222 u32 val = clk_readl(c->reg);
1223
1224 if (c->flags & DIV_U71) {
1225 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1226 c->div = divu71 + 2;
1227 c->mul = 2;
1228 } else if (c->flags & DIV_U16) {
1229 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1230 c->div = divu16 + 1;
1231 c->mul = 1;
1232 } else {
1233 c->div = 1;
1234 c->mul = 1;
1235 return rate;
1236 }
1237
1238 if (c->mul != 0 && c->div != 0) {
1239 rate *= c->mul;
1240 rate += c->div - 1; /* round up */
1241 do_div(rate, c->div);
1242 }
1243
1244 return rate;
1245}
1246
1247static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1248 unsigned long parent_rate)
1249{
1250 struct clk_tegra *c = to_clk_tegra(hw);
1251 u32 val;
1252 int divider;
1253
1254 val = clk_readl(c->reg);
1255
1256 if (c->flags & DIV_U71) {
1257 divider = clk_div71_get_divider(parent_rate, rate);
1258
1259 if (divider >= 0) {
1260 val = clk_readl(c->reg);
1261 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1262 val |= divider;
1263 clk_writel(val, c->reg);
1264 c->div = divider + 2;
1265 c->mul = 2;
1266 return 0;
1267 }
1268 } else if (c->flags & DIV_U16) {
1269 divider = clk_div16_get_divider(parent_rate, rate);
1270 if (divider >= 0) {
1271 val = clk_readl(c->reg);
1272 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1273 val |= divider;
1274 clk_writel(val, c->reg);
1275 c->div = divider + 1;
1276 c->mul = 1;
1277 return 0;
1278 }
1279 } else if (parent_rate <= rate) {
1280 c->div = 1;
1281 c->mul = 1;
1282 return 0;
1283 }
1284
1285 return -EINVAL;
1286}
1287
1288static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
1289 unsigned long rate, unsigned long *prate)
1290{
1291 struct clk_tegra *c = to_clk_tegra(hw);
1292 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1293 int divider;
1294
1295 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1296
1297 if (prate)
1298 parent_rate = *prate;
1299
1300 if (c->flags & DIV_U71) {
1301 divider = clk_div71_get_divider(parent_rate, rate);
1302 if (divider < 0)
1303 return divider;
1304
1305 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1306 } else if (c->flags & DIV_U16) {
1307 divider = clk_div16_get_divider(parent_rate, rate);
1308 if (divider < 0)
1309 return divider;
1310 return DIV_ROUND_UP(parent_rate, divider + 1);
1311 }
1312 return -EINVAL;
1313}
1314
1315struct clk_ops tegra_periph_clk_ops = {
1316 .is_enabled = tegra20_periph_clk_is_enabled,
1317 .enable = tegra20_periph_clk_enable,
1318 .disable = tegra20_periph_clk_disable,
1319 .set_parent = tegra20_periph_clk_set_parent,
1320 .get_parent = tegra20_periph_clk_get_parent,
1321 .set_rate = tegra20_periph_clk_set_rate,
1322 .round_rate = tegra20_periph_clk_round_rate,
1323 .recalc_rate = tegra20_periph_clk_recalc_rate,
1324};
1325
1326/* External memory controller clock ops */
1327static void tegra20_emc_clk_init(struct clk_hw *hw)
1328{
1329 struct clk_tegra *c = to_clk_tegra(hw);
1330 c->max_rate = __clk_get_rate(hw->clk);
1331}
1332
1333static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1334 unsigned long *prate)
1335{
1336 struct clk_tegra *c = to_clk_tegra(hw);
1337 long emc_rate;
1338 long clk_rate;
1339
1340 /*
1341 * The slowest entry in the EMC clock table that is at least as
1342 * fast as rate.
1343 */
1344 emc_rate = tegra_emc_round_rate(rate);
1345 if (emc_rate < 0)
1346 return c->max_rate;
1347
1348 /*
1349 * The fastest rate the PLL will generate that is at most the
1350 * requested rate.
1351 */
1352 clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
1353
1354 /*
1355 * If this fails, and emc_rate > clk_rate, it's because the maximum
1356 * rate in the EMC tables is larger than the maximum rate of the EMC
1357 * clock. The EMC clock's max rate is the rate it was running when the
1358 * kernel booted. Such a mismatch is probably due to using the wrong
1359 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1360 */
1361 WARN_ONCE(emc_rate != clk_rate,
1362 "emc_rate %ld != clk_rate %ld",
1363 emc_rate, clk_rate);
1364
1365 return emc_rate;
1366}
1367
1368static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1369 unsigned long parent_rate)
1370{
1371 int ret;
1372
1373 /*
1374 * The Tegra2 memory controller has an interlock with the clock
1375 * block that allows memory shadowed registers to be updated,
1376 * and then transfer them to the main registers at the same
1377 * time as the clock update without glitches.
1378 */
1379 ret = tegra_emc_set_rate(rate);
1380 if (ret < 0)
1381 return ret;
1382
1383 ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
1384 udelay(1);
1385
1386 return ret;
1387}
1388
1389struct clk_ops tegra_emc_clk_ops = {
1390 .init = tegra20_emc_clk_init,
1391 .is_enabled = tegra20_periph_clk_is_enabled,
1392 .enable = tegra20_periph_clk_enable,
1393 .disable = tegra20_periph_clk_disable,
1394 .set_parent = tegra20_periph_clk_set_parent,
1395 .get_parent = tegra20_periph_clk_get_parent,
1396 .set_rate = tegra20_emc_clk_set_rate,
1397 .round_rate = tegra20_emc_clk_round_rate,
1398 .recalc_rate = tegra20_periph_clk_recalc_rate,
1399};
1400
1401/* Clock doubler ops */
1402static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
1403{
1404 struct clk_tegra *c = to_clk_tegra(hw);
1405
1406 c->state = ON;
1407
1408 if (!c->u.periph.clk_num)
1409 goto out;
1410
1411 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1412 PERIPH_CLK_TO_ENB_BIT(c)))
1413 c->state = OFF;
1414
1415out:
1416 return c->state;
1417};
1418
1419static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
1420 unsigned long prate)
1421{
1422 struct clk_tegra *c = to_clk_tegra(hw);
1423 u64 rate = prate;
1424
1425 c->mul = 2;
1426 c->div = 1;
1427
1428 rate *= c->mul;
1429 rate += c->div - 1; /* round up */
1430 do_div(rate, c->div);
1431
1432 return rate;
1433}
1434
1435static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
1436 unsigned long *prate)
1437{
1438 unsigned long output_rate = *prate;
1439
1440 do_div(output_rate, 2);
1441 return output_rate;
1442}
1443
1444static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
1445 unsigned long parent_rate)
1446{
1447 if (rate != 2 * parent_rate)
1448 return -EINVAL;
1449 return 0;
1450}
1451
1452struct clk_ops tegra_clk_double_ops = {
1453 .is_enabled = tegra20_clk_double_is_enabled,
1454 .enable = tegra20_periph_clk_enable,
1455 .disable = tegra20_periph_clk_disable,
1456 .set_rate = tegra20_clk_double_set_rate,
1457 .recalc_rate = tegra20_clk_double_recalc_rate,
1458 .round_rate = tegra20_clk_double_round_rate,
1459};
1460
1461/* Audio sync clock ops */
1462static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
1463{
1464 struct clk_tegra *c = to_clk_tegra(hw);
1465 u32 val = clk_readl(c->reg);
1466
1467 c->state = (val & (1<<4)) ? OFF : ON;
1468 return c->state;
1469}
1470
1471static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
1472{
1473 struct clk_tegra *c = to_clk_tegra(hw);
1474
1475 clk_writel(0, c->reg);
1476 return 0;
1477}
1478
1479static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
1480{
1481 struct clk_tegra *c = to_clk_tegra(hw);
1482 clk_writel(1, c->reg);
1483}
1484
1485static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
1486{
1487 struct clk_tegra *c = to_clk_tegra(hw);
1488 u32 val = clk_readl(c->reg);
1489 int source;
1490
1491 source = val & 0xf;
1492 return source;
1493}
1494
1495static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1496{
1497 struct clk_tegra *c = to_clk_tegra(hw);
1498 u32 val;
1499
1500 val = clk_readl(c->reg);
1501 val &= ~0xf;
1502 val |= index;
1503
1504 clk_writel(val, c->reg);
1505
1506 return 0;
1507}
1508
1509struct clk_ops tegra_audio_sync_clk_ops = {
1510 .is_enabled = tegra20_audio_sync_clk_is_enabled,
1511 .enable = tegra20_audio_sync_clk_enable,
1512 .disable = tegra20_audio_sync_clk_disable,
1513 .set_parent = tegra20_audio_sync_clk_set_parent,
1514 .get_parent = tegra20_audio_sync_clk_get_parent,
1515};
1516
1517/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1518
1519static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
1520{
1521 struct clk_tegra *c = to_clk_tegra(hw);
1522 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1523 * currently done in the pinmux code. */
1524 c->state = ON;
1525
1526 BUG_ON(!c->u.periph.clk_num);
1527
1528 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1529 PERIPH_CLK_TO_ENB_BIT(c)))
1530 c->state = OFF;
1531 return c->state;
1532}
1533
1534static int tegra20_cdev_clk_enable(struct clk_hw *hw)
1535{
1536 struct clk_tegra *c = to_clk_tegra(hw);
1537 BUG_ON(!c->u.periph.clk_num);
1538
1539 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1540 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1541 return 0;
1542}
1543
1544static void tegra20_cdev_clk_disable(struct clk_hw *hw)
1545{
1546 struct clk_tegra *c = to_clk_tegra(hw);
1547 BUG_ON(!c->u.periph.clk_num);
1548
1549 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1550 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1551}
1552
1553static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
1554 unsigned long prate)
1555{
1556 return to_clk_tegra(hw)->fixed_rate;
1557}
1558
1559struct clk_ops tegra_cdev_clk_ops = {
1560 .is_enabled = tegra20_cdev_clk_is_enabled,
1561 .enable = tegra20_cdev_clk_enable,
1562 .disable = tegra20_cdev_clk_disable,
1563 .recalc_rate = tegra20_cdev_recalc_rate,
1564};
1565
1566/* Tegra20 CPU clock and reset control functions */
1567static void tegra20_wait_cpu_in_reset(u32 cpu)
1568{
1569 unsigned int reg;
1570
1571 do {
1572 reg = readl(reg_clk_base +
1573 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1574 cpu_relax();
1575 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1576
1577 return;
1578}
1579
1580static void tegra20_put_cpu_in_reset(u32 cpu)
1581{
1582 writel(CPU_RESET(cpu),
1583 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1584 dmb();
1585}
1586
1587static void tegra20_cpu_out_of_reset(u32 cpu)
1588{
1589 writel(CPU_RESET(cpu),
1590 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1591 wmb();
1592}
1593
1594static void tegra20_enable_cpu_clock(u32 cpu)
1595{
1596 unsigned int reg;
1597
1598 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1599 writel(reg & ~CPU_CLOCK(cpu),
1600 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1601 barrier();
1602 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1603}
1604
1605static void tegra20_disable_cpu_clock(u32 cpu)
1606{
1607 unsigned int reg;
1608
1609 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1610 writel(reg | CPU_CLOCK(cpu),
1611 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1612}
1613
1614static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1615 .wait_for_reset = tegra20_wait_cpu_in_reset,
1616 .put_in_reset = tegra20_put_cpu_in_reset,
1617 .out_of_reset = tegra20_cpu_out_of_reset,
1618 .enable_clock = tegra20_enable_cpu_clock,
1619 .disable_clock = tegra20_disable_cpu_clock,
1620};
1621
1622void __init tegra20_cpu_car_ops_init(void)
1623{
1624 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1625}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 000000000000..8bfd31bcc490
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA20_CLOCK_H
18#define __MACH_TEGRA20_CLOCK_H
19
20extern struct clk_ops tegra_clk_32k_ops;
21extern struct clk_ops tegra_pll_ops;
22extern struct clk_ops tegra_clk_m_ops;
23extern struct clk_ops tegra_pll_div_ops;
24extern struct clk_ops tegra_pllx_ops;
25extern struct clk_ops tegra_plle_ops;
26extern struct clk_ops tegra_clk_double_ops;
27extern struct clk_ops tegra_cdev_clk_ops;
28extern struct clk_ops tegra_audio_sync_clk_ops;
29extern struct clk_ops tegra_super_ops;
30extern struct clk_ops tegra_cpu_ops;
31extern struct clk_ops tegra_twd_ops;
32extern struct clk_ops tegra_cop_ops;
33extern struct clk_ops tegra_bus_ops;
34extern struct clk_ops tegra_blink_clk_ops;
35extern struct clk_ops tegra_emc_clk_ops;
36extern struct clk_ops tegra_periph_clk_ops;
37extern struct clk_ops tegra_clk_shared_bus_ops;
38
39void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
40void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
41
42#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 000000000000..e81dcd239c95
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,1144 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29
30#include <mach/iomap.h>
31#include <mach/suspend.h>
32
33#include "clock.h"
34#include "fuse.h"
35#include "tegra2_emc.h"
36#include "tegra20_clocks.h"
37#include "tegra_cpu_car.h"
38
39/* Clock definitions */
40
41#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
42 _parent_names, _parents, _parent) \
43 static struct clk tegra_##_name = { \
44 .hw = &tegra_##_name##_hw.hw, \
45 .name = #_name, \
46 .rate = _rate, \
47 .ops = _ops, \
48 .flags = _flags, \
49 .parent_names = _parent_names, \
50 .parents = _parents, \
51 .num_parents = ARRAY_SIZE(_parent_names), \
52 .parent = _parent, \
53 };
54
55static struct clk tegra_clk_32k;
56static struct clk_tegra tegra_clk_32k_hw = {
57 .hw = {
58 .clk = &tegra_clk_32k,
59 },
60 .fixed_rate = 32768,
61};
62
63static struct clk tegra_clk_32k = {
64 .name = "clk_32k",
65 .rate = 32768,
66 .ops = &tegra_clk_32k_ops,
67 .hw = &tegra_clk_32k_hw.hw,
68 .flags = CLK_IS_ROOT,
69};
70
71static struct clk tegra_clk_m;
72static struct clk_tegra tegra_clk_m_hw = {
73 .hw = {
74 .clk = &tegra_clk_m,
75 },
76 .flags = ENABLE_ON_INIT,
77 .reg = 0x1fc,
78 .reg_shift = 28,
79 .max_rate = 26000000,
80 .fixed_rate = 0,
81};
82
83static struct clk tegra_clk_m = {
84 .name = "clk_m",
85 .ops = &tegra_clk_m_ops,
86 .hw = &tegra_clk_m_hw.hw,
87 .flags = CLK_IS_ROOT,
88};
89
90#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
91 _input_max, _cf_min, _cf_max, _vco_min, \
92 _vco_max, _freq_table, _lock_delay, _ops, \
93 _fixed_rate, _parent) \
94 static const char *tegra_##_name##_parent_names[] = { \
95 #_parent, \
96 }; \
97 static struct clk *tegra_##_name##_parents[] = { \
98 &tegra_##_parent, \
99 }; \
100 static struct clk tegra_##_name; \
101 static struct clk_tegra tegra_##_name##_hw = { \
102 .hw = { \
103 .clk = &tegra_##_name, \
104 }, \
105 .flags = _flags, \
106 .reg = _reg, \
107 .max_rate = _max_rate, \
108 .u.pll = { \
109 .input_min = _input_min, \
110 .input_max = _input_max, \
111 .cf_min = _cf_min, \
112 .cf_max = _cf_max, \
113 .vco_min = _vco_min, \
114 .vco_max = _vco_max, \
115 .freq_table = _freq_table, \
116 .lock_delay = _lock_delay, \
117 .fixed_rate = _fixed_rate, \
118 }, \
119 }; \
120 static struct clk tegra_##_name = { \
121 .name = #_name, \
122 .ops = &_ops, \
123 .hw = &tegra_##_name##_hw.hw, \
124 .parent = &tegra_##_parent, \
125 .parent_names = tegra_##_name##_parent_names, \
126 .parents = tegra_##_name##_parents, \
127 .num_parents = 1, \
128 };
129
130#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
131 _max_rate, _ops, _parent, _clk_flags) \
132 static const char *tegra_##_name##_parent_names[] = { \
133 #_parent, \
134 }; \
135 static struct clk *tegra_##_name##_parents[] = { \
136 &tegra_##_parent, \
137 }; \
138 static struct clk tegra_##_name; \
139 static struct clk_tegra tegra_##_name##_hw = { \
140 .hw = { \
141 .clk = &tegra_##_name, \
142 }, \
143 .flags = _flags, \
144 .reg = _reg, \
145 .max_rate = _max_rate, \
146 .reg_shift = _reg_shift, \
147 }; \
148 static struct clk tegra_##_name = { \
149 .name = #_name, \
150 .ops = &tegra_pll_div_ops, \
151 .hw = &tegra_##_name##_hw.hw, \
152 .parent = &tegra_##_parent, \
153 .parent_names = tegra_##_name##_parent_names, \
154 .parents = tegra_##_name##_parents, \
155 .num_parents = 1, \
156 .flags = _clk_flags, \
157 };
158
159
160static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
161 {32768, 12000000, 366, 1, 1, 0},
162 {32768, 13000000, 397, 1, 1, 0},
163 {32768, 19200000, 586, 1, 1, 0},
164 {32768, 26000000, 793, 1, 1, 0},
165 {0, 0, 0, 0, 0, 0},
166};
167
168DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
169 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
170 tegra_pll_ops, 0, clk_32k);
171
172static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
173 { 12000000, 600000000, 600, 12, 1, 8 },
174 { 13000000, 600000000, 600, 13, 1, 8 },
175 { 19200000, 600000000, 500, 16, 1, 6 },
176 { 26000000, 600000000, 600, 26, 1, 8 },
177 { 0, 0, 0, 0, 0, 0 },
178};
179
180DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
181 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
182 tegra_pll_ops, 0, clk_m);
183
184DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
185 tegra_pll_div_ops, pll_c, 0);
186
187static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
188 { 12000000, 666000000, 666, 12, 1, 8},
189 { 13000000, 666000000, 666, 13, 1, 8},
190 { 19200000, 666000000, 555, 16, 1, 8},
191 { 26000000, 666000000, 666, 26, 1, 8},
192 { 12000000, 600000000, 600, 12, 1, 8},
193 { 13000000, 600000000, 600, 13, 1, 8},
194 { 19200000, 600000000, 375, 12, 1, 6},
195 { 26000000, 600000000, 600, 26, 1, 8},
196 { 0, 0, 0, 0, 0, 0 },
197};
198
199DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
200 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
201 tegra_pll_ops, 0, clk_m);
202
203DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
204 tegra_pll_div_ops, pll_m, 0);
205
206static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
207 { 12000000, 216000000, 432, 12, 2, 8},
208 { 13000000, 216000000, 432, 13, 2, 8},
209 { 19200000, 216000000, 90, 4, 2, 1},
210 { 26000000, 216000000, 432, 26, 2, 8},
211 { 12000000, 432000000, 432, 12, 1, 8},
212 { 13000000, 432000000, 432, 13, 1, 8},
213 { 19200000, 432000000, 90, 4, 1, 1},
214 { 26000000, 432000000, 432, 26, 1, 8},
215 { 0, 0, 0, 0, 0, 0 },
216};
217
218
219DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
220 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
221 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
222
223DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
224 432000000, tegra_pll_div_ops, pll_p, 0);
225DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
226 432000000, tegra_pll_div_ops, pll_p, 0);
227DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
228 432000000, tegra_pll_div_ops, pll_p, 0);
229DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
230 432000000, tegra_pll_div_ops, pll_p, 0);
231
232static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
233 { 28800000, 56448000, 49, 25, 1, 1},
234 { 28800000, 73728000, 64, 25, 1, 1},
235 { 28800000, 24000000, 5, 6, 1, 1},
236 { 0, 0, 0, 0, 0, 0 },
237};
238
239DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
240 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
241 tegra_pll_ops, 0, pll_p_out1);
242
243DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
244 tegra_pll_div_ops, pll_a, 0);
245
246static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
247 { 12000000, 216000000, 216, 12, 1, 4},
248 { 13000000, 216000000, 216, 13, 1, 4},
249 { 19200000, 216000000, 135, 12, 1, 3},
250 { 26000000, 216000000, 216, 26, 1, 4},
251
252 { 12000000, 594000000, 594, 12, 1, 8},
253 { 13000000, 594000000, 594, 13, 1, 8},
254 { 19200000, 594000000, 495, 16, 1, 8},
255 { 26000000, 594000000, 594, 26, 1, 8},
256
257 { 12000000, 1000000000, 1000, 12, 1, 12},
258 { 13000000, 1000000000, 1000, 13, 1, 12},
259 { 19200000, 1000000000, 625, 12, 1, 8},
260 { 26000000, 1000000000, 1000, 26, 1, 12},
261
262 { 0, 0, 0, 0, 0, 0 },
263};
264
265DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
266 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
267 1000, tegra_pll_ops, 0, clk_m);
268
269DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
270 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
271
272static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
273 { 12000000, 480000000, 960, 12, 2, 0},
274 { 13000000, 480000000, 960, 13, 2, 0},
275 { 19200000, 480000000, 200, 4, 2, 0},
276 { 26000000, 480000000, 960, 26, 2, 0},
277 { 0, 0, 0, 0, 0, 0 },
278};
279
280DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
281 48000000, 960000000, tegra_pll_u_freq_table, 1000,
282 tegra_pll_ops, 0, clk_m);
283
284static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
285 /* 1 GHz */
286 { 12000000, 1000000000, 1000, 12, 1, 12},
287 { 13000000, 1000000000, 1000, 13, 1, 12},
288 { 19200000, 1000000000, 625, 12, 1, 8},
289 { 26000000, 1000000000, 1000, 26, 1, 12},
290
291 /* 912 MHz */
292 { 12000000, 912000000, 912, 12, 1, 12},
293 { 13000000, 912000000, 912, 13, 1, 12},
294 { 19200000, 912000000, 760, 16, 1, 8},
295 { 26000000, 912000000, 912, 26, 1, 12},
296
297 /* 816 MHz */
298 { 12000000, 816000000, 816, 12, 1, 12},
299 { 13000000, 816000000, 816, 13, 1, 12},
300 { 19200000, 816000000, 680, 16, 1, 8},
301 { 26000000, 816000000, 816, 26, 1, 12},
302
303 /* 760 MHz */
304 { 12000000, 760000000, 760, 12, 1, 12},
305 { 13000000, 760000000, 760, 13, 1, 12},
306 { 19200000, 760000000, 950, 24, 1, 8},
307 { 26000000, 760000000, 760, 26, 1, 12},
308
309 /* 750 MHz */
310 { 12000000, 750000000, 750, 12, 1, 12},
311 { 13000000, 750000000, 750, 13, 1, 12},
312 { 19200000, 750000000, 625, 16, 1, 8},
313 { 26000000, 750000000, 750, 26, 1, 12},
314
315 /* 608 MHz */
316 { 12000000, 608000000, 608, 12, 1, 12},
317 { 13000000, 608000000, 608, 13, 1, 12},
318 { 19200000, 608000000, 380, 12, 1, 8},
319 { 26000000, 608000000, 608, 26, 1, 12},
320
321 /* 456 MHz */
322 { 12000000, 456000000, 456, 12, 1, 12},
323 { 13000000, 456000000, 456, 13, 1, 12},
324 { 19200000, 456000000, 380, 16, 1, 8},
325 { 26000000, 456000000, 456, 26, 1, 12},
326
327 /* 312 MHz */
328 { 12000000, 312000000, 312, 12, 1, 12},
329 { 13000000, 312000000, 312, 13, 1, 12},
330 { 19200000, 312000000, 260, 16, 1, 8},
331 { 26000000, 312000000, 312, 26, 1, 12},
332
333 { 0, 0, 0, 0, 0, 0 },
334};
335
336DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
337 31000000, 1000000, 6000000, 20000000, 1200000000,
338 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
339
340static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
341 { 12000000, 100000000, 200, 24, 1, 0 },
342 { 0, 0, 0, 0, 0, 0 },
343};
344
345DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
346 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
347
348static const char *tegra_common_parent_names[] = {
349 "clk_m",
350};
351
352static struct clk *tegra_common_parents[] = {
353 &tegra_clk_m,
354};
355
356static struct clk tegra_clk_d;
357static struct clk_tegra tegra_clk_d_hw = {
358 .hw = {
359 .clk = &tegra_clk_d,
360 },
361 .flags = PERIPH_NO_RESET,
362 .reg = 0x34,
363 .reg_shift = 12,
364 .max_rate = 52000000,
365 .u.periph = {
366 .clk_num = 90,
367 },
368};
369
370static struct clk tegra_clk_d = {
371 .name = "clk_d",
372 .hw = &tegra_clk_d_hw.hw,
373 .ops = &tegra_clk_double_ops,
374 .parent = &tegra_clk_m,
375 .parent_names = tegra_common_parent_names,
376 .parents = tegra_common_parents,
377 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
378};
379
380static struct clk tegra_cdev1;
381static struct clk_tegra tegra_cdev1_hw = {
382 .hw = {
383 .clk = &tegra_cdev1,
384 },
385 .fixed_rate = 26000000,
386 .u.periph = {
387 .clk_num = 94,
388 },
389};
390static struct clk tegra_cdev1 = {
391 .name = "cdev1",
392 .hw = &tegra_cdev1_hw.hw,
393 .ops = &tegra_cdev_clk_ops,
394 .flags = CLK_IS_ROOT,
395};
396
397/* dap_mclk2, belongs to the cdev2 pingroup. */
398static struct clk tegra_cdev2;
399static struct clk_tegra tegra_cdev2_hw = {
400 .hw = {
401 .clk = &tegra_cdev2,
402 },
403 .fixed_rate = 26000000,
404 .u.periph = {
405 .clk_num = 93,
406 },
407};
408static struct clk tegra_cdev2 = {
409 .name = "cdev2",
410 .hw = &tegra_cdev2_hw.hw,
411 .ops = &tegra_cdev_clk_ops,
412 .flags = CLK_IS_ROOT,
413};
414
415/* initialized before peripheral clocks */
416static struct clk_mux_sel mux_audio_sync_clk[8+1];
417static const struct audio_sources {
418 const char *name;
419 int value;
420} mux_audio_sync_clk_sources[] = {
421 { .name = "spdif_in", .value = 0 },
422 { .name = "i2s1", .value = 1 },
423 { .name = "i2s2", .value = 2 },
424 { .name = "pll_a_out0", .value = 4 },
425#if 0 /* FIXME: not implemented */
426 { .name = "ac97", .value = 3 },
427 { .name = "ext_audio_clk2", .value = 5 },
428 { .name = "ext_audio_clk1", .value = 6 },
429 { .name = "ext_vimclk", .value = 7 },
430#endif
431 { NULL, 0 }
432};
433
434static const char *audio_parent_names[] = {
435 "spdif_in",
436 "i2s1",
437 "i2s2",
438 "dummy",
439 "pll_a_out0",
440 "dummy",
441 "dummy",
442 "dummy",
443};
444
445static struct clk *audio_parents[] = {
446 NULL,
447 NULL,
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453 NULL,
454};
455
456static struct clk tegra_audio;
457static struct clk_tegra tegra_audio_hw = {
458 .hw = {
459 .clk = &tegra_audio,
460 },
461 .reg = 0x38,
462 .max_rate = 73728000,
463};
464DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
465 audio_parents, NULL);
466
467static const char *audio_2x_parent_names[] = {
468 "audio",
469};
470
471static struct clk *audio_2x_parents[] = {
472 &tegra_audio,
473};
474
475static struct clk tegra_audio_2x;
476static struct clk_tegra tegra_audio_2x_hw = {
477 .hw = {
478 .clk = &tegra_audio_2x,
479 },
480 .flags = PERIPH_NO_RESET,
481 .max_rate = 48000000,
482 .reg = 0x34,
483 .reg_shift = 8,
484 .u.periph = {
485 .clk_num = 89,
486 },
487};
488DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
489 audio_2x_parents, &tegra_audio);
490
491static struct clk_lookup tegra_audio_clk_lookups[] = {
492 { .con_id = "audio", .clk = &tegra_audio },
493 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
494};
495
496/* This is called after peripheral clocks are initialized, as the
497 * audio_sync clock depends on some of the peripheral clocks.
498 */
499
500static void init_audio_sync_clock_mux(void)
501{
502 int i;
503 struct clk_mux_sel *sel = mux_audio_sync_clk;
504 const struct audio_sources *src = mux_audio_sync_clk_sources;
505 struct clk_lookup *lookup;
506
507 for (i = 0; src->name; i++, sel++, src++) {
508 sel->input = tegra_get_clock_by_name(src->name);
509 if (!sel->input)
510 pr_err("%s: could not find clk %s\n", __func__,
511 src->name);
512 audio_parents[src->value] = sel->input;
513 sel->value = src->value;
514 }
515
516 lookup = tegra_audio_clk_lookups;
517 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
518 struct clk *c = lookup->clk;
519 struct clk_tegra *clk = to_clk_tegra(c->hw);
520 __clk_init(NULL, c);
521 INIT_LIST_HEAD(&clk->shared_bus_list);
522 clk->lookup.con_id = lookup->con_id;
523 clk->lookup.clk = c;
524 clkdev_add(&clk->lookup);
525 tegra_clk_add(c);
526 }
527}
528
529static const char *mux_cclk[] = {
530 "clk_m",
531 "pll_c",
532 "clk_32k",
533 "pll_m",
534 "pll_p",
535 "pll_p_out4",
536 "pll_p_out3",
537 "clk_d",
538 "pll_x",
539};
540
541
542static struct clk *mux_cclk_p[] = {
543 &tegra_clk_m,
544 &tegra_pll_c,
545 &tegra_clk_32k,
546 &tegra_pll_m,
547 &tegra_pll_p,
548 &tegra_pll_p_out4,
549 &tegra_pll_p_out3,
550 &tegra_clk_d,
551 &tegra_pll_x,
552};
553
554static const char *mux_sclk[] = {
555 "clk_m",
556 "pll_c_out1",
557 "pll_p_out4",
558 "pllp_p_out3",
559 "pll_p_out2",
560 "clk_d",
561 "clk_32k",
562 "pll_m_out1",
563};
564
565static struct clk *mux_sclk_p[] = {
566 &tegra_clk_m,
567 &tegra_pll_c_out1,
568 &tegra_pll_p_out4,
569 &tegra_pll_p_out3,
570 &tegra_pll_p_out2,
571 &tegra_clk_d,
572 &tegra_clk_32k,
573 &tegra_pll_m_out1,
574};
575
576static struct clk tegra_cclk;
577static struct clk_tegra tegra_cclk_hw = {
578 .hw = {
579 .clk = &tegra_cclk,
580 },
581 .reg = 0x20,
582 .max_rate = 1000000000,
583};
584DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
585 mux_cclk_p, NULL);
586
587static const char *mux_twd[] = {
588 "cclk",
589};
590
591static struct clk *mux_twd_p[] = {
592 &tegra_cclk,
593};
594
595static struct clk tegra_clk_twd;
596static struct clk_tegra tegra_clk_twd_hw = {
597 .hw = {
598 .clk = &tegra_clk_twd,
599 },
600 .max_rate = 1000000000,
601 .mul = 1,
602 .div = 4,
603};
604
605static struct clk tegra_clk_twd = {
606 .name = "twd",
607 .ops = &tegra_twd_ops,
608 .hw = &tegra_clk_twd_hw.hw,
609 .parent = &tegra_cclk,
610 .parent_names = mux_twd,
611 .parents = mux_twd_p,
612 .num_parents = ARRAY_SIZE(mux_twd),
613};
614
615static struct clk tegra_sclk;
616static struct clk_tegra tegra_sclk_hw = {
617 .hw = {
618 .clk = &tegra_sclk,
619 },
620 .reg = 0x28,
621 .max_rate = 240000000,
622 .min_rate = 120000000,
623};
624DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
625 mux_sclk_p, NULL);
626
627static const char *tegra_cop_parent_names[] = {
628 "tegra_sclk",
629};
630
631static struct clk *tegra_cop_parents[] = {
632 &tegra_sclk,
633};
634
635static struct clk tegra_cop;
636static struct clk_tegra tegra_cop_hw = {
637 .hw = {
638 .clk = &tegra_cop,
639 },
640 .max_rate = 240000000,
641 .reset = &tegra2_cop_clk_reset,
642};
643DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
644 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
645
646static const char *tegra_hclk_parent_names[] = {
647 "tegra_sclk",
648};
649
650static struct clk *tegra_hclk_parents[] = {
651 &tegra_sclk,
652};
653
654static struct clk tegra_hclk;
655static struct clk_tegra tegra_hclk_hw = {
656 .hw = {
657 .clk = &tegra_hclk,
658 },
659 .flags = DIV_BUS,
660 .reg = 0x30,
661 .reg_shift = 4,
662 .max_rate = 240000000,
663};
664DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
665 tegra_hclk_parents, &tegra_sclk);
666
667static const char *tegra_pclk_parent_names[] = {
668 "tegra_hclk",
669};
670
671static struct clk *tegra_pclk_parents[] = {
672 &tegra_hclk,
673};
674
675static struct clk tegra_pclk;
676static struct clk_tegra tegra_pclk_hw = {
677 .hw = {
678 .clk = &tegra_pclk,
679 },
680 .flags = DIV_BUS,
681 .reg = 0x30,
682 .reg_shift = 0,
683 .max_rate = 120000000,
684};
685DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
686 tegra_pclk_parents, &tegra_hclk);
687
688static const char *tegra_blink_parent_names[] = {
689 "clk_32k",
690};
691
692static struct clk *tegra_blink_parents[] = {
693 &tegra_clk_32k,
694};
695
696static struct clk tegra_blink;
697static struct clk_tegra tegra_blink_hw = {
698 .hw = {
699 .clk = &tegra_blink,
700 },
701 .reg = 0x40,
702 .max_rate = 32768,
703};
704DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
705 tegra_blink_parents, &tegra_clk_32k);
706
707static const char *mux_pllm_pllc_pllp_plla[] = {
708 "pll_m",
709 "pll_c",
710 "pll_p",
711 "pll_a_out0",
712};
713
714static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
715 &tegra_pll_m,
716 &tegra_pll_c,
717 &tegra_pll_p,
718 &tegra_pll_a_out0,
719};
720
721static const char *mux_pllm_pllc_pllp_clkm[] = {
722 "pll_m",
723 "pll_c",
724 "pll_p",
725 "clk_m",
726};
727
728static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
729 &tegra_pll_m,
730 &tegra_pll_c,
731 &tegra_pll_p,
732 &tegra_clk_m,
733};
734
735static const char *mux_pllp_pllc_pllm_clkm[] = {
736 "pll_p",
737 "pll_c",
738 "pll_m",
739 "clk_m",
740};
741
742static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
743 &tegra_pll_p,
744 &tegra_pll_c,
745 &tegra_pll_m,
746 &tegra_clk_m,
747};
748
749static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
750 "pll_a_out0",
751 "audio_2x",
752 "pll_p",
753 "clk_m",
754};
755
756static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
757 &tegra_pll_a_out0,
758 &tegra_audio_2x,
759 &tegra_pll_p,
760 &tegra_clk_m,
761};
762
763static const char *mux_pllp_plld_pllc_clkm[] = {
764 "pllp",
765 "pll_d_out0",
766 "pll_c",
767 "clk_m",
768};
769
770static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
771 &tegra_pll_p,
772 &tegra_pll_d_out0,
773 &tegra_pll_c,
774 &tegra_clk_m,
775};
776
777static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
778 "pll_p",
779 "pll_c",
780 "audio",
781 "clk_m",
782 "clk_32k",
783};
784
785static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
786 &tegra_pll_p,
787 &tegra_pll_c,
788 &tegra_audio,
789 &tegra_clk_m,
790 &tegra_clk_32k,
791};
792
793static const char *mux_pllp_pllc_pllm[] = {
794 "pll_p",
795 "pll_c",
796 "pll_m"
797};
798
799static struct clk *mux_pllp_pllc_pllm_p[] = {
800 &tegra_pll_p,
801 &tegra_pll_c,
802 &tegra_pll_m,
803};
804
805static const char *mux_clk_m[] = {
806 "clk_m",
807};
808
809static struct clk *mux_clk_m_p[] = {
810 &tegra_clk_m,
811};
812
813static const char *mux_pllp_out3[] = {
814 "pll_p_out3",
815};
816
817static struct clk *mux_pllp_out3_p[] = {
818 &tegra_pll_p_out3,
819};
820
821static const char *mux_plld[] = {
822 "pll_d",
823};
824
825static struct clk *mux_plld_p[] = {
826 &tegra_pll_d,
827};
828
829static const char *mux_clk_32k[] = {
830 "clk_32k",
831};
832
833static struct clk *mux_clk_32k_p[] = {
834 &tegra_clk_32k,
835};
836
837static const char *mux_pclk[] = {
838 "pclk",
839};
840
841static struct clk *mux_pclk_p[] = {
842 &tegra_pclk,
843};
844
845static struct clk tegra_emc;
846static struct clk_tegra tegra_emc_hw = {
847 .hw = {
848 .clk = &tegra_emc,
849 },
850 .reg = 0x19c,
851 .max_rate = 800000000,
852 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
853 .reset = &tegra2_periph_clk_reset,
854 .u.periph = {
855 .clk_num = 57,
856 },
857};
858DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
859 mux_pllm_pllc_pllp_clkm_p, NULL);
860
861#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
862 _max, _inputs, _flags) \
863 static struct clk tegra_##_name; \
864 static struct clk_tegra tegra_##_name##_hw = { \
865 .hw = { \
866 .clk = &tegra_##_name, \
867 }, \
868 .lookup = { \
869 .dev_id = _dev, \
870 .con_id = _con, \
871 }, \
872 .reg = _reg, \
873 .flags = _flags, \
874 .max_rate = _max, \
875 .u.periph = { \
876 .clk_num = _clk_num, \
877 }, \
878 .reset = tegra2_periph_clk_reset, \
879 }; \
880 static struct clk tegra_##_name = { \
881 .name = #_name, \
882 .ops = &tegra_periph_clk_ops, \
883 .hw = &tegra_##_name##_hw.hw, \
884 .parent_names = _inputs, \
885 .parents = _inputs##_p, \
886 .num_parents = ARRAY_SIZE(_inputs), \
887 };
888
889PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
890PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
891PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
892PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
893PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
894PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
895PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
896PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
897PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
898PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
899PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
903PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
904PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
905PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
906PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
907PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
909PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
910PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
911PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
912PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
913PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
914PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
915PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
916/* FIXME: what is la? */
917PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
918PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
919PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
920PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
921PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
922PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
923PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
925PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
926PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
927PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
928PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
929PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
932PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
933PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
934PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
935PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
936PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
937PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
938PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
939PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
940PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
941PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
942PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
943PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
944PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
945PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
946PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
947PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
948PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
949PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
950PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
951PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
952PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
953PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
954PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
955PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
956PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
957
958static struct clk *tegra_list_clks[] = {
959 &tegra_apbdma,
960 &tegra_rtc,
961 &tegra_i2s1,
962 &tegra_i2s2,
963 &tegra_spdif_out,
964 &tegra_spdif_in,
965 &tegra_pwm,
966 &tegra_spi,
967 &tegra_xio,
968 &tegra_twc,
969 &tegra_sbc1,
970 &tegra_sbc2,
971 &tegra_sbc3,
972 &tegra_sbc4,
973 &tegra_ide,
974 &tegra_ndflash,
975 &tegra_vfir,
976 &tegra_sdmmc1,
977 &tegra_sdmmc2,
978 &tegra_sdmmc3,
979 &tegra_sdmmc4,
980 &tegra_vcp,
981 &tegra_bsea,
982 &tegra_bsev,
983 &tegra_vde,
984 &tegra_csite,
985 &tegra_la,
986 &tegra_owr,
987 &tegra_nor,
988 &tegra_mipi,
989 &tegra_i2c1,
990 &tegra_i2c2,
991 &tegra_i2c3,
992 &tegra_dvc,
993 &tegra_i2c1_i2c,
994 &tegra_i2c2_i2c,
995 &tegra_i2c3_i2c,
996 &tegra_dvc_i2c,
997 &tegra_uarta,
998 &tegra_uartb,
999 &tegra_uartc,
1000 &tegra_uartd,
1001 &tegra_uarte,
1002 &tegra_3d,
1003 &tegra_2d,
1004 &tegra_vi,
1005 &tegra_vi_sensor,
1006 &tegra_epp,
1007 &tegra_mpe,
1008 &tegra_host1x,
1009 &tegra_cve,
1010 &tegra_tvo,
1011 &tegra_hdmi,
1012 &tegra_tvdac,
1013 &tegra_disp1,
1014 &tegra_disp2,
1015 &tegra_usbd,
1016 &tegra_usb2,
1017 &tegra_usb3,
1018 &tegra_dsi,
1019 &tegra_csi,
1020 &tegra_isp,
1021 &tegra_csus,
1022 &tegra_pex,
1023 &tegra_afi,
1024 &tegra_pcie_xclk,
1025};
1026
1027#define CLK_DUPLICATE(_name, _dev, _con) \
1028 { \
1029 .name = _name, \
1030 .lookup = { \
1031 .dev_id = _dev, \
1032 .con_id = _con, \
1033 }, \
1034 }
1035
1036/* Some clocks may be used by different drivers depending on the board
1037 * configuration. List those here to register them twice in the clock lookup
1038 * table under two names.
1039 */
1040static struct clk_duplicate tegra_clk_duplicates[] = {
1041 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1042 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1043 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1044 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1045 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1046 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1047 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1048 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1049 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1050 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1051 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
1052 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1053 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1054 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1055 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1056 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1057 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1058 CLK_DUPLICATE("cclk", NULL, "cpu"),
1059 CLK_DUPLICATE("twd", "smp_twd", NULL),
1060};
1061
1062#define CLK(dev, con, ck) \
1063 { \
1064 .dev_id = dev, \
1065 .con_id = con, \
1066 .clk = ck, \
1067 }
1068
1069static struct clk *tegra_ptr_clks[] = {
1070 &tegra_clk_32k,
1071 &tegra_pll_s,
1072 &tegra_clk_m,
1073 &tegra_pll_m,
1074 &tegra_pll_m_out1,
1075 &tegra_pll_c,
1076 &tegra_pll_c_out1,
1077 &tegra_pll_p,
1078 &tegra_pll_p_out1,
1079 &tegra_pll_p_out2,
1080 &tegra_pll_p_out3,
1081 &tegra_pll_p_out4,
1082 &tegra_pll_a,
1083 &tegra_pll_a_out0,
1084 &tegra_pll_d,
1085 &tegra_pll_d_out0,
1086 &tegra_pll_u,
1087 &tegra_pll_x,
1088 &tegra_pll_e,
1089 &tegra_cclk,
1090 &tegra_clk_twd,
1091 &tegra_sclk,
1092 &tegra_hclk,
1093 &tegra_pclk,
1094 &tegra_clk_d,
1095 &tegra_cdev1,
1096 &tegra_cdev2,
1097 &tegra_blink,
1098 &tegra_cop,
1099 &tegra_emc,
1100};
1101
1102static void tegra2_init_one_clock(struct clk *c)
1103{
1104 struct clk_tegra *clk = to_clk_tegra(c->hw);
1105 int ret;
1106
1107 ret = __clk_init(NULL, c);
1108 if (ret)
1109 pr_err("clk init failed %s\n", __clk_get_name(c));
1110
1111 INIT_LIST_HEAD(&clk->shared_bus_list);
1112 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1113 clk->lookup.con_id = c->name;
1114 clk->lookup.clk = c;
1115 clkdev_add(&clk->lookup);
1116 tegra_clk_add(c);
1117}
1118
1119void __init tegra2_init_clocks(void)
1120{
1121 int i;
1122 struct clk *c;
1123
1124 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1125 tegra2_init_one_clock(tegra_ptr_clks[i]);
1126
1127 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1128 tegra2_init_one_clock(tegra_list_clks[i]);
1129
1130 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1131 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1132 if (!c) {
1133 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1134 tegra_clk_duplicates[i].name);
1135 continue;
1136 }
1137
1138 tegra_clk_duplicates[i].lookup.clk = c;
1139 clkdev_add(&tegra_clk_duplicates[i].lookup);
1140 }
1141
1142 init_audio_sync_clock_mux();
1143 tegra20_cpu_car_ops_init();
1144}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
deleted file mode 100644
index a703844b2061..000000000000
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ /dev/null
@@ -1,2484 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/spinlock.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26#include <linux/clkdev.h>
27#include <linux/clk.h>
28
29#include <mach/iomap.h>
30#include <mach/suspend.h>
31
32#include "clock.h"
33#include "fuse.h"
34#include "tegra2_emc.h"
35
36#define RST_DEVICES 0x004
37#define RST_DEVICES_SET 0x300
38#define RST_DEVICES_CLR 0x304
39#define RST_DEVICES_NUM 3
40
41#define CLK_OUT_ENB 0x010
42#define CLK_OUT_ENB_SET 0x320
43#define CLK_OUT_ENB_CLR 0x324
44#define CLK_OUT_ENB_NUM 3
45
46#define CLK_MASK_ARM 0x44
47#define MISC_CLK_ENB 0x48
48
49#define OSC_CTRL 0x50
50#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57#define OSC_FREQ_DET 0x58
58#define OSC_FREQ_DET_TRIG (1<<31)
59
60#define OSC_FREQ_DET_STATUS 0x5C
61#define OSC_FREQ_DET_BUSY (1<<31)
62#define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64#define PERIPH_CLK_SOURCE_I2S1 0x100
65#define PERIPH_CLK_SOURCE_EMC 0x19c
66#define PERIPH_CLK_SOURCE_OSC 0x1fc
67#define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70#define PERIPH_CLK_SOURCE_MASK (3<<30)
71#define PERIPH_CLK_SOURCE_SHIFT 30
72#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
74#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
75#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
76#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
77#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78
79#define SDMMC_CLK_INT_FB_SEL (1 << 23)
80#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
81#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
82
83#define PLL_BASE 0x0
84#define PLL_BASE_BYPASS (1<<31)
85#define PLL_BASE_ENABLE (1<<30)
86#define PLL_BASE_REF_ENABLE (1<<29)
87#define PLL_BASE_OVERRIDE (1<<28)
88#define PLL_BASE_DIVP_MASK (0x7<<20)
89#define PLL_BASE_DIVP_SHIFT 20
90#define PLL_BASE_DIVN_MASK (0x3FF<<8)
91#define PLL_BASE_DIVN_SHIFT 8
92#define PLL_BASE_DIVM_MASK (0x1F)
93#define PLL_BASE_DIVM_SHIFT 0
94
95#define PLL_OUT_RATIO_MASK (0xFF<<8)
96#define PLL_OUT_RATIO_SHIFT 8
97#define PLL_OUT_OVERRIDE (1<<2)
98#define PLL_OUT_CLKEN (1<<1)
99#define PLL_OUT_RESET_DISABLE (1<<0)
100
101#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
102
103#define PLL_MISC_DCCON_SHIFT 20
104#define PLL_MISC_CPCON_SHIFT 8
105#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
106#define PLL_MISC_LFCON_SHIFT 4
107#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
108#define PLL_MISC_VCOCON_SHIFT 0
109#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
110
111#define PLLU_BASE_POST_DIV (1<<20)
112
113#define PLLD_MISC_CLKENABLE (1<<30)
114#define PLLD_MISC_DIV_RST (1<<23)
115#define PLLD_MISC_DCCON_SHIFT 12
116
117#define PLLE_MISC_READY (1 << 15)
118
119#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
120#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
121#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
122
123#define SUPER_CLK_MUX 0x00
124#define SUPER_STATE_SHIFT 28
125#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
126#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
127#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
128#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
129#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
130#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
131#define SUPER_SOURCE_MASK 0xF
132#define SUPER_FIQ_SOURCE_SHIFT 12
133#define SUPER_IRQ_SOURCE_SHIFT 8
134#define SUPER_RUN_SOURCE_SHIFT 4
135#define SUPER_IDLE_SOURCE_SHIFT 0
136
137#define SUPER_CLK_DIVIDER 0x04
138
139#define BUS_CLK_DISABLE (1<<3)
140#define BUS_CLK_DIV_MASK 0x3
141
142#define PMC_CTRL 0x0
143 #define PMC_CTRL_BLINK_ENB (1 << 7)
144
145#define PMC_DPD_PADS_ORIDE 0x1c
146 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
147
148#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
149#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
150#define PMC_BLINK_TIMER_ENB (1 << 15)
151#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
152#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
153
154static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
155static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
156
157/*
158 * Some clocks share a register with other clocks. Any clock op that
159 * non-atomically modifies a register used by another clock must lock
160 * clock_register_lock first.
161 */
162static DEFINE_SPINLOCK(clock_register_lock);
163
164/*
165 * Some peripheral clocks share an enable bit, so refcount the enable bits
166 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
167 */
168static int tegra_periph_clk_enable_refcount[3 * 32];
169
170#define clk_writel(value, reg) \
171 __raw_writel(value, reg_clk_base + (reg))
172#define clk_readl(reg) \
173 __raw_readl(reg_clk_base + (reg))
174#define pmc_writel(value, reg) \
175 __raw_writel(value, reg_pmc_base + (reg))
176#define pmc_readl(reg) \
177 __raw_readl(reg_pmc_base + (reg))
178
179static unsigned long clk_measure_input_freq(void)
180{
181 u32 clock_autodetect;
182 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
183 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
184 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
185 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
186 return 12000000;
187 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
188 return 13000000;
189 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
190 return 19200000;
191 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
192 return 26000000;
193 } else {
194 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
195 BUG();
196 return 0;
197 }
198}
199
200static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
201{
202 s64 divider_u71 = parent_rate * 2;
203 divider_u71 += rate - 1;
204 do_div(divider_u71, rate);
205
206 if (divider_u71 - 2 < 0)
207 return 0;
208
209 if (divider_u71 - 2 > 255)
210 return -EINVAL;
211
212 return divider_u71 - 2;
213}
214
215static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
216{
217 s64 divider_u16;
218
219 divider_u16 = parent_rate;
220 divider_u16 += rate - 1;
221 do_div(divider_u16, rate);
222
223 if (divider_u16 - 1 < 0)
224 return 0;
225
226 if (divider_u16 - 1 > 255)
227 return -EINVAL;
228
229 return divider_u16 - 1;
230}
231
232/* clk_m functions */
233static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
234{
235 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
236
237 c->rate = clk_measure_input_freq();
238 switch (c->rate) {
239 case 12000000:
240 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
241 break;
242 case 13000000:
243 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
244 break;
245 case 19200000:
246 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
247 break;
248 case 26000000:
249 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
250 break;
251 default:
252 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
253 BUG();
254 }
255 clk_writel(auto_clock_control, OSC_CTRL);
256 return c->rate;
257}
258
259static void tegra2_clk_m_init(struct clk *c)
260{
261 pr_debug("%s on clock %s\n", __func__, c->name);
262 tegra2_clk_m_autodetect_rate(c);
263}
264
265static int tegra2_clk_m_enable(struct clk *c)
266{
267 pr_debug("%s on clock %s\n", __func__, c->name);
268 return 0;
269}
270
271static void tegra2_clk_m_disable(struct clk *c)
272{
273 pr_debug("%s on clock %s\n", __func__, c->name);
274 BUG();
275}
276
277static struct clk_ops tegra_clk_m_ops = {
278 .init = tegra2_clk_m_init,
279 .enable = tegra2_clk_m_enable,
280 .disable = tegra2_clk_m_disable,
281};
282
283/* super clock functions */
284/* "super clocks" on tegra have two-stage muxes and a clock skipping
285 * super divider. We will ignore the clock skipping divider, since we
286 * can't lower the voltage when using the clock skip, but we can if we
287 * lower the PLL frequency.
288 */
289static void tegra2_super_clk_init(struct clk *c)
290{
291 u32 val;
292 int source;
293 int shift;
294 const struct clk_mux_sel *sel;
295 val = clk_readl(c->reg + SUPER_CLK_MUX);
296 c->state = ON;
297 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
298 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
299 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
300 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
301 source = (val >> shift) & SUPER_SOURCE_MASK;
302 for (sel = c->inputs; sel->input != NULL; sel++) {
303 if (sel->value == source)
304 break;
305 }
306 BUG_ON(sel->input == NULL);
307 c->parent = sel->input;
308}
309
310static int tegra2_super_clk_enable(struct clk *c)
311{
312 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
313 return 0;
314}
315
316static void tegra2_super_clk_disable(struct clk *c)
317{
318 pr_debug("%s on clock %s\n", __func__, c->name);
319
320 /* oops - don't disable the CPU clock! */
321 BUG();
322}
323
324static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
325{
326 u32 val;
327 const struct clk_mux_sel *sel;
328 int shift;
329
330 val = clk_readl(c->reg + SUPER_CLK_MUX);
331 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
332 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
333 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
334 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
335 for (sel = c->inputs; sel->input != NULL; sel++) {
336 if (sel->input == p) {
337 val &= ~(SUPER_SOURCE_MASK << shift);
338 val |= sel->value << shift;
339
340 if (c->refcnt)
341 clk_enable(p);
342
343 clk_writel(val, c->reg);
344
345 if (c->refcnt && c->parent)
346 clk_disable(c->parent);
347
348 clk_reparent(c, p);
349 return 0;
350 }
351 }
352 return -EINVAL;
353}
354
355/*
356 * Super clocks have "clock skippers" instead of dividers. Dividing using
357 * a clock skipper does not allow the voltage to be scaled down, so instead
358 * adjust the rate of the parent clock. This requires that the parent of a
359 * super clock have no other children, otherwise the rate will change
360 * underneath the other children.
361 */
362static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
363{
364 return clk_set_rate(c->parent, rate);
365}
366
367static struct clk_ops tegra_super_ops = {
368 .init = tegra2_super_clk_init,
369 .enable = tegra2_super_clk_enable,
370 .disable = tegra2_super_clk_disable,
371 .set_parent = tegra2_super_clk_set_parent,
372 .set_rate = tegra2_super_clk_set_rate,
373};
374
375/* virtual cpu clock functions */
376/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
377 To change the frequency of these clocks, the parent pll may need to be
378 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
379 and then the clock moved back to the pll. To hide this sequence, a virtual
380 clock handles it.
381 */
382static void tegra2_cpu_clk_init(struct clk *c)
383{
384}
385
386static int tegra2_cpu_clk_enable(struct clk *c)
387{
388 return 0;
389}
390
391static void tegra2_cpu_clk_disable(struct clk *c)
392{
393 pr_debug("%s on clock %s\n", __func__, c->name);
394
395 /* oops - don't disable the CPU clock! */
396 BUG();
397}
398
399static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
400{
401 int ret;
402 /*
403 * Take an extra reference to the main pll so it doesn't turn
404 * off when we move the cpu off of it
405 */
406 clk_enable(c->u.cpu.main);
407
408 ret = clk_set_parent(c->parent, c->u.cpu.backup);
409 if (ret) {
410 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
411 goto out;
412 }
413
414 if (rate == clk_get_rate(c->u.cpu.backup))
415 goto out;
416
417 ret = clk_set_rate(c->u.cpu.main, rate);
418 if (ret) {
419 pr_err("Failed to change cpu pll to %lu\n", rate);
420 goto out;
421 }
422
423 ret = clk_set_parent(c->parent, c->u.cpu.main);
424 if (ret) {
425 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
426 goto out;
427 }
428
429out:
430 clk_disable(c->u.cpu.main);
431 return ret;
432}
433
434static struct clk_ops tegra_cpu_ops = {
435 .init = tegra2_cpu_clk_init,
436 .enable = tegra2_cpu_clk_enable,
437 .disable = tegra2_cpu_clk_disable,
438 .set_rate = tegra2_cpu_clk_set_rate,
439};
440
441/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
442 * reset the COP block (i.e. AVP) */
443static void tegra2_cop_clk_reset(struct clk *c, bool assert)
444{
445 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
446
447 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
448 clk_writel(1 << 1, reg);
449}
450
451static struct clk_ops tegra_cop_ops = {
452 .reset = tegra2_cop_clk_reset,
453};
454
455/* bus clock functions */
456static void tegra2_bus_clk_init(struct clk *c)
457{
458 u32 val = clk_readl(c->reg);
459 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
460 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
461 c->mul = 1;
462}
463
464static int tegra2_bus_clk_enable(struct clk *c)
465{
466 u32 val;
467 unsigned long flags;
468
469 spin_lock_irqsave(&clock_register_lock, flags);
470
471 val = clk_readl(c->reg);
472 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
473 clk_writel(val, c->reg);
474
475 spin_unlock_irqrestore(&clock_register_lock, flags);
476
477 return 0;
478}
479
480static void tegra2_bus_clk_disable(struct clk *c)
481{
482 u32 val;
483 unsigned long flags;
484
485 spin_lock_irqsave(&clock_register_lock, flags);
486
487 val = clk_readl(c->reg);
488 val |= BUS_CLK_DISABLE << c->reg_shift;
489 clk_writel(val, c->reg);
490
491 spin_unlock_irqrestore(&clock_register_lock, flags);
492}
493
494static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
495{
496 u32 val;
497 unsigned long parent_rate = clk_get_rate(c->parent);
498 unsigned long flags;
499 int ret = -EINVAL;
500 int i;
501
502 spin_lock_irqsave(&clock_register_lock, flags);
503
504 val = clk_readl(c->reg);
505 for (i = 1; i <= 4; i++) {
506 if (rate == parent_rate / i) {
507 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
508 val |= (i - 1) << c->reg_shift;
509 clk_writel(val, c->reg);
510 c->div = i;
511 c->mul = 1;
512 ret = 0;
513 break;
514 }
515 }
516
517 spin_unlock_irqrestore(&clock_register_lock, flags);
518
519 return ret;
520}
521
522static struct clk_ops tegra_bus_ops = {
523 .init = tegra2_bus_clk_init,
524 .enable = tegra2_bus_clk_enable,
525 .disable = tegra2_bus_clk_disable,
526 .set_rate = tegra2_bus_clk_set_rate,
527};
528
529/* Blink output functions */
530
531static void tegra2_blink_clk_init(struct clk *c)
532{
533 u32 val;
534
535 val = pmc_readl(PMC_CTRL);
536 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
537 c->mul = 1;
538 val = pmc_readl(c->reg);
539
540 if (val & PMC_BLINK_TIMER_ENB) {
541 unsigned int on_off;
542
543 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
544 PMC_BLINK_TIMER_DATA_ON_MASK;
545 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
546 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
547 on_off += val;
548 /* each tick in the blink timer is 4 32KHz clocks */
549 c->div = on_off * 4;
550 } else {
551 c->div = 1;
552 }
553}
554
555static int tegra2_blink_clk_enable(struct clk *c)
556{
557 u32 val;
558
559 val = pmc_readl(PMC_DPD_PADS_ORIDE);
560 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
561
562 val = pmc_readl(PMC_CTRL);
563 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
564
565 return 0;
566}
567
568static void tegra2_blink_clk_disable(struct clk *c)
569{
570 u32 val;
571
572 val = pmc_readl(PMC_CTRL);
573 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
574
575 val = pmc_readl(PMC_DPD_PADS_ORIDE);
576 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
577}
578
579static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
580{
581 unsigned long parent_rate = clk_get_rate(c->parent);
582 if (rate >= parent_rate) {
583 c->div = 1;
584 pmc_writel(0, c->reg);
585 } else {
586 unsigned int on_off;
587 u32 val;
588
589 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
590 c->div = on_off * 8;
591
592 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
593 PMC_BLINK_TIMER_DATA_ON_SHIFT;
594 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
595 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
596 val |= on_off;
597 val |= PMC_BLINK_TIMER_ENB;
598 pmc_writel(val, c->reg);
599 }
600
601 return 0;
602}
603
604static struct clk_ops tegra_blink_clk_ops = {
605 .init = &tegra2_blink_clk_init,
606 .enable = &tegra2_blink_clk_enable,
607 .disable = &tegra2_blink_clk_disable,
608 .set_rate = &tegra2_blink_clk_set_rate,
609};
610
611/* PLL Functions */
612static int tegra2_pll_clk_wait_for_lock(struct clk *c)
613{
614 udelay(c->u.pll.lock_delay);
615
616 return 0;
617}
618
619static void tegra2_pll_clk_init(struct clk *c)
620{
621 u32 val = clk_readl(c->reg + PLL_BASE);
622
623 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
624
625 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
626 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
627 c->mul = 1;
628 c->div = 1;
629 } else if (val & PLL_BASE_BYPASS) {
630 c->mul = 1;
631 c->div = 1;
632 } else {
633 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
634 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
635 if (c->flags & PLLU)
636 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
637 else
638 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
639 }
640}
641
642static int tegra2_pll_clk_enable(struct clk *c)
643{
644 u32 val;
645 pr_debug("%s on clock %s\n", __func__, c->name);
646
647 val = clk_readl(c->reg + PLL_BASE);
648 val &= ~PLL_BASE_BYPASS;
649 val |= PLL_BASE_ENABLE;
650 clk_writel(val, c->reg + PLL_BASE);
651
652 tegra2_pll_clk_wait_for_lock(c);
653
654 return 0;
655}
656
657static void tegra2_pll_clk_disable(struct clk *c)
658{
659 u32 val;
660 pr_debug("%s on clock %s\n", __func__, c->name);
661
662 val = clk_readl(c->reg);
663 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
664 clk_writel(val, c->reg);
665}
666
667static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
668{
669 u32 val;
670 unsigned long input_rate;
671 const struct clk_pll_freq_table *sel;
672
673 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
674
675 input_rate = clk_get_rate(c->parent);
676 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
677 if (sel->input_rate == input_rate && sel->output_rate == rate) {
678 c->mul = sel->n;
679 c->div = sel->m * sel->p;
680
681 val = clk_readl(c->reg + PLL_BASE);
682 if (c->flags & PLL_FIXED)
683 val |= PLL_BASE_OVERRIDE;
684 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
685 PLL_BASE_DIVM_MASK);
686 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
687 (sel->n << PLL_BASE_DIVN_SHIFT);
688 BUG_ON(sel->p < 1 || sel->p > 2);
689 if (c->flags & PLLU) {
690 if (sel->p == 1)
691 val |= PLLU_BASE_POST_DIV;
692 } else {
693 if (sel->p == 2)
694 val |= 1 << PLL_BASE_DIVP_SHIFT;
695 }
696 clk_writel(val, c->reg + PLL_BASE);
697
698 if (c->flags & PLL_HAS_CPCON) {
699 val = clk_readl(c->reg + PLL_MISC(c));
700 val &= ~PLL_MISC_CPCON_MASK;
701 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
702 clk_writel(val, c->reg + PLL_MISC(c));
703 }
704
705 if (c->state == ON)
706 tegra2_pll_clk_enable(c);
707
708 return 0;
709 }
710 }
711 return -EINVAL;
712}
713
714static struct clk_ops tegra_pll_ops = {
715 .init = tegra2_pll_clk_init,
716 .enable = tegra2_pll_clk_enable,
717 .disable = tegra2_pll_clk_disable,
718 .set_rate = tegra2_pll_clk_set_rate,
719};
720
721static void tegra2_pllx_clk_init(struct clk *c)
722{
723 tegra2_pll_clk_init(c);
724
725 if (tegra_sku_id == 7)
726 c->max_rate = 750000000;
727}
728
729static struct clk_ops tegra_pllx_ops = {
730 .init = tegra2_pllx_clk_init,
731 .enable = tegra2_pll_clk_enable,
732 .disable = tegra2_pll_clk_disable,
733 .set_rate = tegra2_pll_clk_set_rate,
734};
735
736static int tegra2_plle_clk_enable(struct clk *c)
737{
738 u32 val;
739
740 pr_debug("%s on clock %s\n", __func__, c->name);
741
742 mdelay(1);
743
744 val = clk_readl(c->reg + PLL_BASE);
745 if (!(val & PLLE_MISC_READY))
746 return -EBUSY;
747
748 val = clk_readl(c->reg + PLL_BASE);
749 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
750 clk_writel(val, c->reg + PLL_BASE);
751
752 return 0;
753}
754
755static struct clk_ops tegra_plle_ops = {
756 .init = tegra2_pll_clk_init,
757 .enable = tegra2_plle_clk_enable,
758 .set_rate = tegra2_pll_clk_set_rate,
759};
760
761/* Clock divider ops */
762static void tegra2_pll_div_clk_init(struct clk *c)
763{
764 u32 val = clk_readl(c->reg);
765 u32 divu71;
766 val >>= c->reg_shift;
767 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
768 if (!(val & PLL_OUT_RESET_DISABLE))
769 c->state = OFF;
770
771 if (c->flags & DIV_U71) {
772 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
773 c->div = (divu71 + 2);
774 c->mul = 2;
775 } else if (c->flags & DIV_2) {
776 c->div = 2;
777 c->mul = 1;
778 } else {
779 c->div = 1;
780 c->mul = 1;
781 }
782}
783
784static int tegra2_pll_div_clk_enable(struct clk *c)
785{
786 u32 val;
787 u32 new_val;
788 unsigned long flags;
789
790 pr_debug("%s: %s\n", __func__, c->name);
791 if (c->flags & DIV_U71) {
792 spin_lock_irqsave(&clock_register_lock, flags);
793 val = clk_readl(c->reg);
794 new_val = val >> c->reg_shift;
795 new_val &= 0xFFFF;
796
797 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
798
799 val &= ~(0xFFFF << c->reg_shift);
800 val |= new_val << c->reg_shift;
801 clk_writel(val, c->reg);
802 spin_unlock_irqrestore(&clock_register_lock, flags);
803 return 0;
804 } else if (c->flags & DIV_2) {
805 BUG_ON(!(c->flags & PLLD));
806 spin_lock_irqsave(&clock_register_lock, flags);
807 val = clk_readl(c->reg);
808 val &= ~PLLD_MISC_DIV_RST;
809 clk_writel(val, c->reg);
810 spin_unlock_irqrestore(&clock_register_lock, flags);
811 return 0;
812 }
813 return -EINVAL;
814}
815
816static void tegra2_pll_div_clk_disable(struct clk *c)
817{
818 u32 val;
819 u32 new_val;
820 unsigned long flags;
821
822 pr_debug("%s: %s\n", __func__, c->name);
823 if (c->flags & DIV_U71) {
824 spin_lock_irqsave(&clock_register_lock, flags);
825 val = clk_readl(c->reg);
826 new_val = val >> c->reg_shift;
827 new_val &= 0xFFFF;
828
829 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
830
831 val &= ~(0xFFFF << c->reg_shift);
832 val |= new_val << c->reg_shift;
833 clk_writel(val, c->reg);
834 spin_unlock_irqrestore(&clock_register_lock, flags);
835 } else if (c->flags & DIV_2) {
836 BUG_ON(!(c->flags & PLLD));
837 spin_lock_irqsave(&clock_register_lock, flags);
838 val = clk_readl(c->reg);
839 val |= PLLD_MISC_DIV_RST;
840 clk_writel(val, c->reg);
841 spin_unlock_irqrestore(&clock_register_lock, flags);
842 }
843}
844
845static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
846{
847 u32 val;
848 u32 new_val;
849 int divider_u71;
850 unsigned long parent_rate = clk_get_rate(c->parent);
851 unsigned long flags;
852
853 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
854 if (c->flags & DIV_U71) {
855 divider_u71 = clk_div71_get_divider(parent_rate, rate);
856 if (divider_u71 >= 0) {
857 spin_lock_irqsave(&clock_register_lock, flags);
858 val = clk_readl(c->reg);
859 new_val = val >> c->reg_shift;
860 new_val &= 0xFFFF;
861 if (c->flags & DIV_U71_FIXED)
862 new_val |= PLL_OUT_OVERRIDE;
863 new_val &= ~PLL_OUT_RATIO_MASK;
864 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
865
866 val &= ~(0xFFFF << c->reg_shift);
867 val |= new_val << c->reg_shift;
868 clk_writel(val, c->reg);
869 c->div = divider_u71 + 2;
870 c->mul = 2;
871 spin_unlock_irqrestore(&clock_register_lock, flags);
872 return 0;
873 }
874 } else if (c->flags & DIV_2) {
875 if (parent_rate == rate * 2)
876 return 0;
877 }
878 return -EINVAL;
879}
880
881static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
882{
883 int divider;
884 unsigned long parent_rate = clk_get_rate(c->parent);
885 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
886
887 if (c->flags & DIV_U71) {
888 divider = clk_div71_get_divider(parent_rate, rate);
889 if (divider < 0)
890 return divider;
891 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
892 } else if (c->flags & DIV_2) {
893 return DIV_ROUND_UP(parent_rate, 2);
894 }
895 return -EINVAL;
896}
897
898static struct clk_ops tegra_pll_div_ops = {
899 .init = tegra2_pll_div_clk_init,
900 .enable = tegra2_pll_div_clk_enable,
901 .disable = tegra2_pll_div_clk_disable,
902 .set_rate = tegra2_pll_div_clk_set_rate,
903 .round_rate = tegra2_pll_div_clk_round_rate,
904};
905
906/* Periph clk ops */
907
908static void tegra2_periph_clk_init(struct clk *c)
909{
910 u32 val = clk_readl(c->reg);
911 const struct clk_mux_sel *mux = NULL;
912 const struct clk_mux_sel *sel;
913 u32 shift;
914 u32 mask;
915
916 if (c->flags & MUX_PWM) {
917 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
918 mask = PERIPH_CLK_SOURCE_PWM_MASK;
919 } else {
920 shift = PERIPH_CLK_SOURCE_SHIFT;
921 mask = PERIPH_CLK_SOURCE_MASK;
922 }
923
924 if (c->flags & MUX) {
925 for (sel = c->inputs; sel->input != NULL; sel++) {
926 if ((val & mask) >> shift == sel->value)
927 mux = sel;
928 }
929 BUG_ON(!mux);
930
931 c->parent = mux->input;
932 } else {
933 c->parent = c->inputs[0].input;
934 }
935
936 if (c->flags & DIV_U71) {
937 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
938 c->div = divu71 + 2;
939 c->mul = 2;
940 } else if (c->flags & DIV_U16) {
941 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
942 c->div = divu16 + 1;
943 c->mul = 1;
944 } else {
945 c->div = 1;
946 c->mul = 1;
947 }
948
949 c->state = ON;
950
951 if (!c->u.periph.clk_num)
952 return;
953
954 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
955 PERIPH_CLK_TO_ENB_BIT(c)))
956 c->state = OFF;
957
958 if (!(c->flags & PERIPH_NO_RESET))
959 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
960 PERIPH_CLK_TO_ENB_BIT(c))
961 c->state = OFF;
962}
963
964static int tegra2_periph_clk_enable(struct clk *c)
965{
966 u32 val;
967 unsigned long flags;
968 int refcount;
969 pr_debug("%s on clock %s\n", __func__, c->name);
970
971 if (!c->u.periph.clk_num)
972 return 0;
973
974 spin_lock_irqsave(&clock_register_lock, flags);
975
976 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
977
978 if (refcount > 1)
979 goto out;
980
981 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
982 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
983 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
984 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
985 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
986 if (c->flags & PERIPH_EMC_ENB) {
987 /* The EMC peripheral clock has 2 extra enable bits */
988 /* FIXME: Do they need to be disabled? */
989 val = clk_readl(c->reg);
990 val |= 0x3 << 24;
991 clk_writel(val, c->reg);
992 }
993
994out:
995 spin_unlock_irqrestore(&clock_register_lock, flags);
996
997 return 0;
998}
999
1000static void tegra2_periph_clk_disable(struct clk *c)
1001{
1002 unsigned long flags;
1003
1004 pr_debug("%s on clock %s\n", __func__, c->name);
1005
1006 if (!c->u.periph.clk_num)
1007 return;
1008
1009 spin_lock_irqsave(&clock_register_lock, flags);
1010
1011 if (c->refcnt)
1012 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1013
1014 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
1015 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1016 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1017
1018 spin_unlock_irqrestore(&clock_register_lock, flags);
1019}
1020
1021static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1022{
1023 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1024
1025 pr_debug("%s %s on clock %s\n", __func__,
1026 assert ? "assert" : "deassert", c->name);
1027
1028 BUG_ON(!c->u.periph.clk_num);
1029
1030 if (!(c->flags & PERIPH_NO_RESET))
1031 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1032 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1033}
1034
1035static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1036{
1037 u32 val;
1038 const struct clk_mux_sel *sel;
1039 u32 mask, shift;
1040
1041 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1042
1043 if (c->flags & MUX_PWM) {
1044 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1045 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1046 } else {
1047 shift = PERIPH_CLK_SOURCE_SHIFT;
1048 mask = PERIPH_CLK_SOURCE_MASK;
1049 }
1050
1051 for (sel = c->inputs; sel->input != NULL; sel++) {
1052 if (sel->input == p) {
1053 val = clk_readl(c->reg);
1054 val &= ~mask;
1055 val |= (sel->value) << shift;
1056
1057 if (c->refcnt)
1058 clk_enable(p);
1059
1060 clk_writel(val, c->reg);
1061
1062 if (c->refcnt && c->parent)
1063 clk_disable(c->parent);
1064
1065 clk_reparent(c, p);
1066 return 0;
1067 }
1068 }
1069
1070 return -EINVAL;
1071}
1072
1073static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1074{
1075 u32 val;
1076 int divider;
1077 unsigned long parent_rate = clk_get_rate(c->parent);
1078
1079 if (c->flags & DIV_U71) {
1080 divider = clk_div71_get_divider(parent_rate, rate);
1081 if (divider >= 0) {
1082 val = clk_readl(c->reg);
1083 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1084 val |= divider;
1085 clk_writel(val, c->reg);
1086 c->div = divider + 2;
1087 c->mul = 2;
1088 return 0;
1089 }
1090 } else if (c->flags & DIV_U16) {
1091 divider = clk_div16_get_divider(parent_rate, rate);
1092 if (divider >= 0) {
1093 val = clk_readl(c->reg);
1094 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1095 val |= divider;
1096 clk_writel(val, c->reg);
1097 c->div = divider + 1;
1098 c->mul = 1;
1099 return 0;
1100 }
1101 } else if (parent_rate <= rate) {
1102 c->div = 1;
1103 c->mul = 1;
1104 return 0;
1105 }
1106 return -EINVAL;
1107}
1108
1109static long tegra2_periph_clk_round_rate(struct clk *c,
1110 unsigned long rate)
1111{
1112 int divider;
1113 unsigned long parent_rate = clk_get_rate(c->parent);
1114 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1115
1116 if (c->flags & DIV_U71) {
1117 divider = clk_div71_get_divider(parent_rate, rate);
1118 if (divider < 0)
1119 return divider;
1120
1121 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1122 } else if (c->flags & DIV_U16) {
1123 divider = clk_div16_get_divider(parent_rate, rate);
1124 if (divider < 0)
1125 return divider;
1126 return DIV_ROUND_UP(parent_rate, divider + 1);
1127 }
1128 return -EINVAL;
1129}
1130
1131static struct clk_ops tegra_periph_clk_ops = {
1132 .init = &tegra2_periph_clk_init,
1133 .enable = &tegra2_periph_clk_enable,
1134 .disable = &tegra2_periph_clk_disable,
1135 .set_parent = &tegra2_periph_clk_set_parent,
1136 .set_rate = &tegra2_periph_clk_set_rate,
1137 .round_rate = &tegra2_periph_clk_round_rate,
1138 .reset = &tegra2_periph_clk_reset,
1139};
1140
1141/* The SDMMC controllers have extra bits in the clock source register that
1142 * adjust the delay between the clock and data to compenstate for delays
1143 * on the PCB. */
1144void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1145{
1146 u32 reg;
1147 unsigned long flags;
1148
1149 spin_lock_irqsave(&c->spinlock, flags);
1150
1151 delay = clamp(delay, 0, 15);
1152 reg = clk_readl(c->reg);
1153 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1154 reg |= SDMMC_CLK_INT_FB_SEL;
1155 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1156 clk_writel(reg, c->reg);
1157
1158 spin_unlock_irqrestore(&c->spinlock, flags);
1159}
1160
1161/* External memory controller clock ops */
1162static void tegra2_emc_clk_init(struct clk *c)
1163{
1164 tegra2_periph_clk_init(c);
1165 c->max_rate = clk_get_rate_locked(c);
1166}
1167
1168static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1169{
1170 long emc_rate;
1171 long clk_rate;
1172
1173 /*
1174 * The slowest entry in the EMC clock table that is at least as
1175 * fast as rate.
1176 */
1177 emc_rate = tegra_emc_round_rate(rate);
1178 if (emc_rate < 0)
1179 return c->max_rate;
1180
1181 /*
1182 * The fastest rate the PLL will generate that is at most the
1183 * requested rate.
1184 */
1185 clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
1186
1187 /*
1188 * If this fails, and emc_rate > clk_rate, it's because the maximum
1189 * rate in the EMC tables is larger than the maximum rate of the EMC
1190 * clock. The EMC clock's max rate is the rate it was running when the
1191 * kernel booted. Such a mismatch is probably due to using the wrong
1192 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1193 */
1194 WARN_ONCE(emc_rate != clk_rate,
1195 "emc_rate %ld != clk_rate %ld",
1196 emc_rate, clk_rate);
1197
1198 return emc_rate;
1199}
1200
1201static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1202{
1203 int ret;
1204 /*
1205 * The Tegra2 memory controller has an interlock with the clock
1206 * block that allows memory shadowed registers to be updated,
1207 * and then transfer them to the main registers at the same
1208 * time as the clock update without glitches.
1209 */
1210 ret = tegra_emc_set_rate(rate);
1211 if (ret < 0)
1212 return ret;
1213
1214 ret = tegra2_periph_clk_set_rate(c, rate);
1215 udelay(1);
1216
1217 return ret;
1218}
1219
1220static struct clk_ops tegra_emc_clk_ops = {
1221 .init = &tegra2_emc_clk_init,
1222 .enable = &tegra2_periph_clk_enable,
1223 .disable = &tegra2_periph_clk_disable,
1224 .set_parent = &tegra2_periph_clk_set_parent,
1225 .set_rate = &tegra2_emc_clk_set_rate,
1226 .round_rate = &tegra2_emc_clk_round_rate,
1227 .reset = &tegra2_periph_clk_reset,
1228};
1229
1230/* Clock doubler ops */
1231static void tegra2_clk_double_init(struct clk *c)
1232{
1233 c->mul = 2;
1234 c->div = 1;
1235 c->state = ON;
1236
1237 if (!c->u.periph.clk_num)
1238 return;
1239
1240 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1241 PERIPH_CLK_TO_ENB_BIT(c)))
1242 c->state = OFF;
1243};
1244
1245static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1246{
1247 if (rate != 2 * clk_get_rate(c->parent))
1248 return -EINVAL;
1249 c->mul = 2;
1250 c->div = 1;
1251 return 0;
1252}
1253
1254static struct clk_ops tegra_clk_double_ops = {
1255 .init = &tegra2_clk_double_init,
1256 .enable = &tegra2_periph_clk_enable,
1257 .disable = &tegra2_periph_clk_disable,
1258 .set_rate = &tegra2_clk_double_set_rate,
1259};
1260
1261/* Audio sync clock ops */
1262static void tegra2_audio_sync_clk_init(struct clk *c)
1263{
1264 int source;
1265 const struct clk_mux_sel *sel;
1266 u32 val = clk_readl(c->reg);
1267 c->state = (val & (1<<4)) ? OFF : ON;
1268 source = val & 0xf;
1269 for (sel = c->inputs; sel->input != NULL; sel++)
1270 if (sel->value == source)
1271 break;
1272 BUG_ON(sel->input == NULL);
1273 c->parent = sel->input;
1274}
1275
1276static int tegra2_audio_sync_clk_enable(struct clk *c)
1277{
1278 clk_writel(0, c->reg);
1279 return 0;
1280}
1281
1282static void tegra2_audio_sync_clk_disable(struct clk *c)
1283{
1284 clk_writel(1, c->reg);
1285}
1286
1287static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1288{
1289 u32 val;
1290 const struct clk_mux_sel *sel;
1291 for (sel = c->inputs; sel->input != NULL; sel++) {
1292 if (sel->input == p) {
1293 val = clk_readl(c->reg);
1294 val &= ~0xf;
1295 val |= sel->value;
1296
1297 if (c->refcnt)
1298 clk_enable(p);
1299
1300 clk_writel(val, c->reg);
1301
1302 if (c->refcnt && c->parent)
1303 clk_disable(c->parent);
1304
1305 clk_reparent(c, p);
1306 return 0;
1307 }
1308 }
1309
1310 return -EINVAL;
1311}
1312
1313static struct clk_ops tegra_audio_sync_clk_ops = {
1314 .init = tegra2_audio_sync_clk_init,
1315 .enable = tegra2_audio_sync_clk_enable,
1316 .disable = tegra2_audio_sync_clk_disable,
1317 .set_parent = tegra2_audio_sync_clk_set_parent,
1318};
1319
1320/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1321
1322static void tegra2_cdev_clk_init(struct clk *c)
1323{
1324 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1325 * currently done in the pinmux code. */
1326 c->state = ON;
1327
1328 BUG_ON(!c->u.periph.clk_num);
1329
1330 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1331 PERIPH_CLK_TO_ENB_BIT(c)))
1332 c->state = OFF;
1333}
1334
1335static int tegra2_cdev_clk_enable(struct clk *c)
1336{
1337 BUG_ON(!c->u.periph.clk_num);
1338
1339 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1340 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1341 return 0;
1342}
1343
1344static void tegra2_cdev_clk_disable(struct clk *c)
1345{
1346 BUG_ON(!c->u.periph.clk_num);
1347
1348 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1349 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1350}
1351
1352static struct clk_ops tegra_cdev_clk_ops = {
1353 .init = &tegra2_cdev_clk_init,
1354 .enable = &tegra2_cdev_clk_enable,
1355 .disable = &tegra2_cdev_clk_disable,
1356};
1357
1358/* shared bus ops */
1359/*
1360 * Some clocks may have multiple downstream users that need to request a
1361 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1362 * clock to each user. The frequency of the bus is set to the highest
1363 * enabled shared_bus_user clock, with a minimum value set by the
1364 * shared bus.
1365 */
1366static int tegra_clk_shared_bus_update(struct clk *bus)
1367{
1368 struct clk *c;
1369 unsigned long rate = bus->min_rate;
1370
1371 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1372 if (c->u.shared_bus_user.enabled)
1373 rate = max(c->u.shared_bus_user.rate, rate);
1374
1375 if (rate == clk_get_rate_locked(bus))
1376 return 0;
1377
1378 return clk_set_rate_locked(bus, rate);
1379};
1380
1381static void tegra_clk_shared_bus_init(struct clk *c)
1382{
1383 unsigned long flags;
1384
1385 c->max_rate = c->parent->max_rate;
1386 c->u.shared_bus_user.rate = c->parent->max_rate;
1387 c->state = OFF;
1388 c->set = true;
1389
1390 spin_lock_irqsave(&c->parent->spinlock, flags);
1391
1392 list_add_tail(&c->u.shared_bus_user.node,
1393 &c->parent->shared_bus_list);
1394
1395 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1396}
1397
1398static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1399{
1400 unsigned long flags;
1401 int ret;
1402 long new_rate = rate;
1403
1404 new_rate = clk_round_rate(c->parent, new_rate);
1405 if (new_rate < 0)
1406 return new_rate;
1407
1408 spin_lock_irqsave(&c->parent->spinlock, flags);
1409
1410 c->u.shared_bus_user.rate = new_rate;
1411 ret = tegra_clk_shared_bus_update(c->parent);
1412
1413 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1414
1415 return ret;
1416}
1417
1418static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1419{
1420 return clk_round_rate(c->parent, rate);
1421}
1422
1423static int tegra_clk_shared_bus_enable(struct clk *c)
1424{
1425 unsigned long flags;
1426 int ret;
1427
1428 spin_lock_irqsave(&c->parent->spinlock, flags);
1429
1430 c->u.shared_bus_user.enabled = true;
1431 ret = tegra_clk_shared_bus_update(c->parent);
1432
1433 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1434
1435 return ret;
1436}
1437
1438static void tegra_clk_shared_bus_disable(struct clk *c)
1439{
1440 unsigned long flags;
1441 int ret;
1442
1443 spin_lock_irqsave(&c->parent->spinlock, flags);
1444
1445 c->u.shared_bus_user.enabled = false;
1446 ret = tegra_clk_shared_bus_update(c->parent);
1447 WARN_ON_ONCE(ret);
1448
1449 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1450}
1451
1452static struct clk_ops tegra_clk_shared_bus_ops = {
1453 .init = tegra_clk_shared_bus_init,
1454 .enable = tegra_clk_shared_bus_enable,
1455 .disable = tegra_clk_shared_bus_disable,
1456 .set_rate = tegra_clk_shared_bus_set_rate,
1457 .round_rate = tegra_clk_shared_bus_round_rate,
1458};
1459
1460
1461/* Clock definitions */
1462static struct clk tegra_clk_32k = {
1463 .name = "clk_32k",
1464 .rate = 32768,
1465 .ops = NULL,
1466 .max_rate = 32768,
1467};
1468
1469static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1470 {32768, 12000000, 366, 1, 1, 0},
1471 {32768, 13000000, 397, 1, 1, 0},
1472 {32768, 19200000, 586, 1, 1, 0},
1473 {32768, 26000000, 793, 1, 1, 0},
1474 {0, 0, 0, 0, 0, 0},
1475};
1476
1477static struct clk tegra_pll_s = {
1478 .name = "pll_s",
1479 .flags = PLL_ALT_MISC_REG,
1480 .ops = &tegra_pll_ops,
1481 .parent = &tegra_clk_32k,
1482 .max_rate = 26000000,
1483 .reg = 0xf0,
1484 .u.pll = {
1485 .input_min = 32768,
1486 .input_max = 32768,
1487 .cf_min = 0, /* FIXME */
1488 .cf_max = 0, /* FIXME */
1489 .vco_min = 12000000,
1490 .vco_max = 26000000,
1491 .freq_table = tegra_pll_s_freq_table,
1492 .lock_delay = 300,
1493 },
1494};
1495
1496static struct clk_mux_sel tegra_clk_m_sel[] = {
1497 { .input = &tegra_clk_32k, .value = 0},
1498 { .input = &tegra_pll_s, .value = 1},
1499 { NULL , 0},
1500};
1501
1502static struct clk tegra_clk_m = {
1503 .name = "clk_m",
1504 .flags = ENABLE_ON_INIT,
1505 .ops = &tegra_clk_m_ops,
1506 .inputs = tegra_clk_m_sel,
1507 .reg = 0x1fc,
1508 .reg_shift = 28,
1509 .max_rate = 26000000,
1510};
1511
1512static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1513 { 12000000, 600000000, 600, 12, 1, 8 },
1514 { 13000000, 600000000, 600, 13, 1, 8 },
1515 { 19200000, 600000000, 500, 16, 1, 6 },
1516 { 26000000, 600000000, 600, 26, 1, 8 },
1517 { 0, 0, 0, 0, 0, 0 },
1518};
1519
1520static struct clk tegra_pll_c = {
1521 .name = "pll_c",
1522 .flags = PLL_HAS_CPCON,
1523 .ops = &tegra_pll_ops,
1524 .reg = 0x80,
1525 .parent = &tegra_clk_m,
1526 .max_rate = 600000000,
1527 .u.pll = {
1528 .input_min = 2000000,
1529 .input_max = 31000000,
1530 .cf_min = 1000000,
1531 .cf_max = 6000000,
1532 .vco_min = 20000000,
1533 .vco_max = 1400000000,
1534 .freq_table = tegra_pll_c_freq_table,
1535 .lock_delay = 300,
1536 },
1537};
1538
1539static struct clk tegra_pll_c_out1 = {
1540 .name = "pll_c_out1",
1541 .ops = &tegra_pll_div_ops,
1542 .flags = DIV_U71,
1543 .parent = &tegra_pll_c,
1544 .reg = 0x84,
1545 .reg_shift = 0,
1546 .max_rate = 600000000,
1547};
1548
1549static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1550 { 12000000, 666000000, 666, 12, 1, 8},
1551 { 13000000, 666000000, 666, 13, 1, 8},
1552 { 19200000, 666000000, 555, 16, 1, 8},
1553 { 26000000, 666000000, 666, 26, 1, 8},
1554 { 12000000, 600000000, 600, 12, 1, 8},
1555 { 13000000, 600000000, 600, 13, 1, 8},
1556 { 19200000, 600000000, 375, 12, 1, 6},
1557 { 26000000, 600000000, 600, 26, 1, 8},
1558 { 0, 0, 0, 0, 0, 0 },
1559};
1560
1561static struct clk tegra_pll_m = {
1562 .name = "pll_m",
1563 .flags = PLL_HAS_CPCON,
1564 .ops = &tegra_pll_ops,
1565 .reg = 0x90,
1566 .parent = &tegra_clk_m,
1567 .max_rate = 800000000,
1568 .u.pll = {
1569 .input_min = 2000000,
1570 .input_max = 31000000,
1571 .cf_min = 1000000,
1572 .cf_max = 6000000,
1573 .vco_min = 20000000,
1574 .vco_max = 1200000000,
1575 .freq_table = tegra_pll_m_freq_table,
1576 .lock_delay = 300,
1577 },
1578};
1579
1580static struct clk tegra_pll_m_out1 = {
1581 .name = "pll_m_out1",
1582 .ops = &tegra_pll_div_ops,
1583 .flags = DIV_U71,
1584 .parent = &tegra_pll_m,
1585 .reg = 0x94,
1586 .reg_shift = 0,
1587 .max_rate = 600000000,
1588};
1589
1590static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1591 { 12000000, 216000000, 432, 12, 2, 8},
1592 { 13000000, 216000000, 432, 13, 2, 8},
1593 { 19200000, 216000000, 90, 4, 2, 1},
1594 { 26000000, 216000000, 432, 26, 2, 8},
1595 { 12000000, 432000000, 432, 12, 1, 8},
1596 { 13000000, 432000000, 432, 13, 1, 8},
1597 { 19200000, 432000000, 90, 4, 1, 1},
1598 { 26000000, 432000000, 432, 26, 1, 8},
1599 { 0, 0, 0, 0, 0, 0 },
1600};
1601
1602static struct clk tegra_pll_p = {
1603 .name = "pll_p",
1604 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1605 .ops = &tegra_pll_ops,
1606 .reg = 0xa0,
1607 .parent = &tegra_clk_m,
1608 .max_rate = 432000000,
1609 .u.pll = {
1610 .input_min = 2000000,
1611 .input_max = 31000000,
1612 .cf_min = 1000000,
1613 .cf_max = 6000000,
1614 .vco_min = 20000000,
1615 .vco_max = 1400000000,
1616 .freq_table = tegra_pll_p_freq_table,
1617 .lock_delay = 300,
1618 },
1619};
1620
1621static struct clk tegra_pll_p_out1 = {
1622 .name = "pll_p_out1",
1623 .ops = &tegra_pll_div_ops,
1624 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1625 .parent = &tegra_pll_p,
1626 .reg = 0xa4,
1627 .reg_shift = 0,
1628 .max_rate = 432000000,
1629};
1630
1631static struct clk tegra_pll_p_out2 = {
1632 .name = "pll_p_out2",
1633 .ops = &tegra_pll_div_ops,
1634 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1635 .parent = &tegra_pll_p,
1636 .reg = 0xa4,
1637 .reg_shift = 16,
1638 .max_rate = 432000000,
1639};
1640
1641static struct clk tegra_pll_p_out3 = {
1642 .name = "pll_p_out3",
1643 .ops = &tegra_pll_div_ops,
1644 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1645 .parent = &tegra_pll_p,
1646 .reg = 0xa8,
1647 .reg_shift = 0,
1648 .max_rate = 432000000,
1649};
1650
1651static struct clk tegra_pll_p_out4 = {
1652 .name = "pll_p_out4",
1653 .ops = &tegra_pll_div_ops,
1654 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1655 .parent = &tegra_pll_p,
1656 .reg = 0xa8,
1657 .reg_shift = 16,
1658 .max_rate = 432000000,
1659};
1660
1661static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1662 { 28800000, 56448000, 49, 25, 1, 1},
1663 { 28800000, 73728000, 64, 25, 1, 1},
1664 { 28800000, 24000000, 5, 6, 1, 1},
1665 { 0, 0, 0, 0, 0, 0 },
1666};
1667
1668static struct clk tegra_pll_a = {
1669 .name = "pll_a",
1670 .flags = PLL_HAS_CPCON,
1671 .ops = &tegra_pll_ops,
1672 .reg = 0xb0,
1673 .parent = &tegra_pll_p_out1,
1674 .max_rate = 73728000,
1675 .u.pll = {
1676 .input_min = 2000000,
1677 .input_max = 31000000,
1678 .cf_min = 1000000,
1679 .cf_max = 6000000,
1680 .vco_min = 20000000,
1681 .vco_max = 1400000000,
1682 .freq_table = tegra_pll_a_freq_table,
1683 .lock_delay = 300,
1684 },
1685};
1686
1687static struct clk tegra_pll_a_out0 = {
1688 .name = "pll_a_out0",
1689 .ops = &tegra_pll_div_ops,
1690 .flags = DIV_U71,
1691 .parent = &tegra_pll_a,
1692 .reg = 0xb4,
1693 .reg_shift = 0,
1694 .max_rate = 73728000,
1695};
1696
1697static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1698 { 12000000, 216000000, 216, 12, 1, 4},
1699 { 13000000, 216000000, 216, 13, 1, 4},
1700 { 19200000, 216000000, 135, 12, 1, 3},
1701 { 26000000, 216000000, 216, 26, 1, 4},
1702
1703 { 12000000, 594000000, 594, 12, 1, 8},
1704 { 13000000, 594000000, 594, 13, 1, 8},
1705 { 19200000, 594000000, 495, 16, 1, 8},
1706 { 26000000, 594000000, 594, 26, 1, 8},
1707
1708 { 12000000, 1000000000, 1000, 12, 1, 12},
1709 { 13000000, 1000000000, 1000, 13, 1, 12},
1710 { 19200000, 1000000000, 625, 12, 1, 8},
1711 { 26000000, 1000000000, 1000, 26, 1, 12},
1712
1713 { 0, 0, 0, 0, 0, 0 },
1714};
1715
1716static struct clk tegra_pll_d = {
1717 .name = "pll_d",
1718 .flags = PLL_HAS_CPCON | PLLD,
1719 .ops = &tegra_pll_ops,
1720 .reg = 0xd0,
1721 .parent = &tegra_clk_m,
1722 .max_rate = 1000000000,
1723 .u.pll = {
1724 .input_min = 2000000,
1725 .input_max = 40000000,
1726 .cf_min = 1000000,
1727 .cf_max = 6000000,
1728 .vco_min = 40000000,
1729 .vco_max = 1000000000,
1730 .freq_table = tegra_pll_d_freq_table,
1731 .lock_delay = 1000,
1732 },
1733};
1734
1735static struct clk tegra_pll_d_out0 = {
1736 .name = "pll_d_out0",
1737 .ops = &tegra_pll_div_ops,
1738 .flags = DIV_2 | PLLD,
1739 .parent = &tegra_pll_d,
1740 .max_rate = 500000000,
1741};
1742
1743static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1744 { 12000000, 480000000, 960, 12, 2, 0},
1745 { 13000000, 480000000, 960, 13, 2, 0},
1746 { 19200000, 480000000, 200, 4, 2, 0},
1747 { 26000000, 480000000, 960, 26, 2, 0},
1748 { 0, 0, 0, 0, 0, 0 },
1749};
1750
1751static struct clk tegra_pll_u = {
1752 .name = "pll_u",
1753 .flags = PLLU,
1754 .ops = &tegra_pll_ops,
1755 .reg = 0xc0,
1756 .parent = &tegra_clk_m,
1757 .max_rate = 480000000,
1758 .u.pll = {
1759 .input_min = 2000000,
1760 .input_max = 40000000,
1761 .cf_min = 1000000,
1762 .cf_max = 6000000,
1763 .vco_min = 480000000,
1764 .vco_max = 960000000,
1765 .freq_table = tegra_pll_u_freq_table,
1766 .lock_delay = 1000,
1767 },
1768};
1769
1770static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1771 /* 1 GHz */
1772 { 12000000, 1000000000, 1000, 12, 1, 12},
1773 { 13000000, 1000000000, 1000, 13, 1, 12},
1774 { 19200000, 1000000000, 625, 12, 1, 8},
1775 { 26000000, 1000000000, 1000, 26, 1, 12},
1776
1777 /* 912 MHz */
1778 { 12000000, 912000000, 912, 12, 1, 12},
1779 { 13000000, 912000000, 912, 13, 1, 12},
1780 { 19200000, 912000000, 760, 16, 1, 8},
1781 { 26000000, 912000000, 912, 26, 1, 12},
1782
1783 /* 816 MHz */
1784 { 12000000, 816000000, 816, 12, 1, 12},
1785 { 13000000, 816000000, 816, 13, 1, 12},
1786 { 19200000, 816000000, 680, 16, 1, 8},
1787 { 26000000, 816000000, 816, 26, 1, 12},
1788
1789 /* 760 MHz */
1790 { 12000000, 760000000, 760, 12, 1, 12},
1791 { 13000000, 760000000, 760, 13, 1, 12},
1792 { 19200000, 760000000, 950, 24, 1, 8},
1793 { 26000000, 760000000, 760, 26, 1, 12},
1794
1795 /* 750 MHz */
1796 { 12000000, 750000000, 750, 12, 1, 12},
1797 { 13000000, 750000000, 750, 13, 1, 12},
1798 { 19200000, 750000000, 625, 16, 1, 8},
1799 { 26000000, 750000000, 750, 26, 1, 12},
1800
1801 /* 608 MHz */
1802 { 12000000, 608000000, 608, 12, 1, 12},
1803 { 13000000, 608000000, 608, 13, 1, 12},
1804 { 19200000, 608000000, 380, 12, 1, 8},
1805 { 26000000, 608000000, 608, 26, 1, 12},
1806
1807 /* 456 MHz */
1808 { 12000000, 456000000, 456, 12, 1, 12},
1809 { 13000000, 456000000, 456, 13, 1, 12},
1810 { 19200000, 456000000, 380, 16, 1, 8},
1811 { 26000000, 456000000, 456, 26, 1, 12},
1812
1813 /* 312 MHz */
1814 { 12000000, 312000000, 312, 12, 1, 12},
1815 { 13000000, 312000000, 312, 13, 1, 12},
1816 { 19200000, 312000000, 260, 16, 1, 8},
1817 { 26000000, 312000000, 312, 26, 1, 12},
1818
1819 { 0, 0, 0, 0, 0, 0 },
1820};
1821
1822static struct clk tegra_pll_x = {
1823 .name = "pll_x",
1824 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1825 .ops = &tegra_pllx_ops,
1826 .reg = 0xe0,
1827 .parent = &tegra_clk_m,
1828 .max_rate = 1000000000,
1829 .u.pll = {
1830 .input_min = 2000000,
1831 .input_max = 31000000,
1832 .cf_min = 1000000,
1833 .cf_max = 6000000,
1834 .vco_min = 20000000,
1835 .vco_max = 1200000000,
1836 .freq_table = tegra_pll_x_freq_table,
1837 .lock_delay = 300,
1838 },
1839};
1840
1841static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1842 { 12000000, 100000000, 200, 24, 1, 0 },
1843 { 0, 0, 0, 0, 0, 0 },
1844};
1845
1846static struct clk tegra_pll_e = {
1847 .name = "pll_e",
1848 .flags = PLL_ALT_MISC_REG,
1849 .ops = &tegra_plle_ops,
1850 .parent = &tegra_clk_m,
1851 .reg = 0xe8,
1852 .max_rate = 100000000,
1853 .u.pll = {
1854 .input_min = 12000000,
1855 .input_max = 12000000,
1856 .freq_table = tegra_pll_e_freq_table,
1857 },
1858};
1859
1860static struct clk tegra_clk_d = {
1861 .name = "clk_d",
1862 .flags = PERIPH_NO_RESET,
1863 .ops = &tegra_clk_double_ops,
1864 .reg = 0x34,
1865 .reg_shift = 12,
1866 .parent = &tegra_clk_m,
1867 .max_rate = 52000000,
1868 .u.periph = {
1869 .clk_num = 90,
1870 },
1871};
1872
1873/* dap_mclk1, belongs to the cdev1 pingroup. */
1874static struct clk tegra_clk_cdev1 = {
1875 .name = "cdev1",
1876 .ops = &tegra_cdev_clk_ops,
1877 .rate = 26000000,
1878 .max_rate = 26000000,
1879 .u.periph = {
1880 .clk_num = 94,
1881 },
1882};
1883
1884/* dap_mclk2, belongs to the cdev2 pingroup. */
1885static struct clk tegra_clk_cdev2 = {
1886 .name = "cdev2",
1887 .ops = &tegra_cdev_clk_ops,
1888 .rate = 26000000,
1889 .max_rate = 26000000,
1890 .u.periph = {
1891 .clk_num = 93,
1892 },
1893};
1894
1895/* initialized before peripheral clocks */
1896static struct clk_mux_sel mux_audio_sync_clk[8+1];
1897static const struct audio_sources {
1898 const char *name;
1899 int value;
1900} mux_audio_sync_clk_sources[] = {
1901 { .name = "spdif_in", .value = 0 },
1902 { .name = "i2s1", .value = 1 },
1903 { .name = "i2s2", .value = 2 },
1904 { .name = "pll_a_out0", .value = 4 },
1905#if 0 /* FIXME: not implemented */
1906 { .name = "ac97", .value = 3 },
1907 { .name = "ext_audio_clk2", .value = 5 },
1908 { .name = "ext_audio_clk1", .value = 6 },
1909 { .name = "ext_vimclk", .value = 7 },
1910#endif
1911 { NULL, 0 }
1912};
1913
1914static struct clk tegra_clk_audio = {
1915 .name = "audio",
1916 .inputs = mux_audio_sync_clk,
1917 .reg = 0x38,
1918 .max_rate = 73728000,
1919 .ops = &tegra_audio_sync_clk_ops
1920};
1921
1922static struct clk tegra_clk_audio_2x = {
1923 .name = "audio_2x",
1924 .flags = PERIPH_NO_RESET,
1925 .max_rate = 48000000,
1926 .ops = &tegra_clk_double_ops,
1927 .reg = 0x34,
1928 .reg_shift = 8,
1929 .parent = &tegra_clk_audio,
1930 .u.periph = {
1931 .clk_num = 89,
1932 },
1933};
1934
1935static struct clk_lookup tegra_audio_clk_lookups[] = {
1936 { .con_id = "audio", .clk = &tegra_clk_audio },
1937 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1938};
1939
1940/* This is called after peripheral clocks are initialized, as the
1941 * audio_sync clock depends on some of the peripheral clocks.
1942 */
1943
1944static void init_audio_sync_clock_mux(void)
1945{
1946 int i;
1947 struct clk_mux_sel *sel = mux_audio_sync_clk;
1948 const struct audio_sources *src = mux_audio_sync_clk_sources;
1949 struct clk_lookup *lookup;
1950
1951 for (i = 0; src->name; i++, sel++, src++) {
1952 sel->input = tegra_get_clock_by_name(src->name);
1953 if (!sel->input)
1954 pr_err("%s: could not find clk %s\n", __func__,
1955 src->name);
1956 sel->value = src->value;
1957 }
1958
1959 lookup = tegra_audio_clk_lookups;
1960 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1961 clk_init(lookup->clk);
1962 clkdev_add(lookup);
1963 }
1964}
1965
1966static struct clk_mux_sel mux_cclk[] = {
1967 { .input = &tegra_clk_m, .value = 0},
1968 { .input = &tegra_pll_c, .value = 1},
1969 { .input = &tegra_clk_32k, .value = 2},
1970 { .input = &tegra_pll_m, .value = 3},
1971 { .input = &tegra_pll_p, .value = 4},
1972 { .input = &tegra_pll_p_out4, .value = 5},
1973 { .input = &tegra_pll_p_out3, .value = 6},
1974 { .input = &tegra_clk_d, .value = 7},
1975 { .input = &tegra_pll_x, .value = 8},
1976 { NULL, 0},
1977};
1978
1979static struct clk_mux_sel mux_sclk[] = {
1980 { .input = &tegra_clk_m, .value = 0},
1981 { .input = &tegra_pll_c_out1, .value = 1},
1982 { .input = &tegra_pll_p_out4, .value = 2},
1983 { .input = &tegra_pll_p_out3, .value = 3},
1984 { .input = &tegra_pll_p_out2, .value = 4},
1985 { .input = &tegra_clk_d, .value = 5},
1986 { .input = &tegra_clk_32k, .value = 6},
1987 { .input = &tegra_pll_m_out1, .value = 7},
1988 { NULL, 0},
1989};
1990
1991static struct clk tegra_clk_cclk = {
1992 .name = "cclk",
1993 .inputs = mux_cclk,
1994 .reg = 0x20,
1995 .ops = &tegra_super_ops,
1996 .max_rate = 1000000000,
1997};
1998
1999static struct clk tegra_clk_sclk = {
2000 .name = "sclk",
2001 .inputs = mux_sclk,
2002 .reg = 0x28,
2003 .ops = &tegra_super_ops,
2004 .max_rate = 240000000,
2005 .min_rate = 120000000,
2006};
2007
2008static struct clk tegra_clk_virtual_cpu = {
2009 .name = "cpu",
2010 .parent = &tegra_clk_cclk,
2011 .ops = &tegra_cpu_ops,
2012 .max_rate = 1000000000,
2013 .u.cpu = {
2014 .main = &tegra_pll_x,
2015 .backup = &tegra_pll_p,
2016 },
2017};
2018
2019static struct clk tegra_clk_cop = {
2020 .name = "cop",
2021 .parent = &tegra_clk_sclk,
2022 .ops = &tegra_cop_ops,
2023 .max_rate = 240000000,
2024};
2025
2026static struct clk tegra_clk_hclk = {
2027 .name = "hclk",
2028 .flags = DIV_BUS,
2029 .parent = &tegra_clk_sclk,
2030 .reg = 0x30,
2031 .reg_shift = 4,
2032 .ops = &tegra_bus_ops,
2033 .max_rate = 240000000,
2034};
2035
2036static struct clk tegra_clk_pclk = {
2037 .name = "pclk",
2038 .flags = DIV_BUS,
2039 .parent = &tegra_clk_hclk,
2040 .reg = 0x30,
2041 .reg_shift = 0,
2042 .ops = &tegra_bus_ops,
2043 .max_rate = 120000000,
2044};
2045
2046static struct clk tegra_clk_blink = {
2047 .name = "blink",
2048 .parent = &tegra_clk_32k,
2049 .reg = 0x40,
2050 .ops = &tegra_blink_clk_ops,
2051 .max_rate = 32768,
2052};
2053
2054static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2055 { .input = &tegra_pll_m, .value = 0},
2056 { .input = &tegra_pll_c, .value = 1},
2057 { .input = &tegra_pll_p, .value = 2},
2058 { .input = &tegra_pll_a_out0, .value = 3},
2059 { NULL, 0},
2060};
2061
2062static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2063 { .input = &tegra_pll_m, .value = 0},
2064 { .input = &tegra_pll_c, .value = 1},
2065 { .input = &tegra_pll_p, .value = 2},
2066 { .input = &tegra_clk_m, .value = 3},
2067 { NULL, 0},
2068};
2069
2070static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2071 { .input = &tegra_pll_p, .value = 0},
2072 { .input = &tegra_pll_c, .value = 1},
2073 { .input = &tegra_pll_m, .value = 2},
2074 { .input = &tegra_clk_m, .value = 3},
2075 { NULL, 0},
2076};
2077
2078static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2079 {.input = &tegra_pll_a_out0, .value = 0},
2080 {.input = &tegra_clk_audio_2x, .value = 1},
2081 {.input = &tegra_pll_p, .value = 2},
2082 {.input = &tegra_clk_m, .value = 3},
2083 { NULL, 0},
2084};
2085
2086static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2087 {.input = &tegra_pll_p, .value = 0},
2088 {.input = &tegra_pll_d_out0, .value = 1},
2089 {.input = &tegra_pll_c, .value = 2},
2090 {.input = &tegra_clk_m, .value = 3},
2091 { NULL, 0},
2092};
2093
2094static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2095 {.input = &tegra_pll_p, .value = 0},
2096 {.input = &tegra_pll_c, .value = 1},
2097 {.input = &tegra_clk_audio, .value = 2},
2098 {.input = &tegra_clk_m, .value = 3},
2099 {.input = &tegra_clk_32k, .value = 4},
2100 { NULL, 0},
2101};
2102
2103static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2104 {.input = &tegra_pll_p, .value = 0},
2105 {.input = &tegra_pll_c, .value = 1},
2106 {.input = &tegra_pll_m, .value = 2},
2107 { NULL, 0},
2108};
2109
2110static struct clk_mux_sel mux_clk_m[] = {
2111 { .input = &tegra_clk_m, .value = 0},
2112 { NULL, 0},
2113};
2114
2115static struct clk_mux_sel mux_pllp_out3[] = {
2116 { .input = &tegra_pll_p_out3, .value = 0},
2117 { NULL, 0},
2118};
2119
2120static struct clk_mux_sel mux_plld[] = {
2121 { .input = &tegra_pll_d, .value = 0},
2122 { NULL, 0},
2123};
2124
2125static struct clk_mux_sel mux_clk_32k[] = {
2126 { .input = &tegra_clk_32k, .value = 0},
2127 { NULL, 0},
2128};
2129
2130static struct clk_mux_sel mux_pclk[] = {
2131 { .input = &tegra_clk_pclk, .value = 0},
2132 { NULL, 0},
2133};
2134
2135static struct clk tegra_clk_emc = {
2136 .name = "emc",
2137 .ops = &tegra_emc_clk_ops,
2138 .reg = 0x19c,
2139 .max_rate = 800000000,
2140 .inputs = mux_pllm_pllc_pllp_clkm,
2141 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2142 .u.periph = {
2143 .clk_num = 57,
2144 },
2145};
2146
2147#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2148 { \
2149 .name = _name, \
2150 .lookup = { \
2151 .dev_id = _dev, \
2152 .con_id = _con, \
2153 }, \
2154 .ops = &tegra_periph_clk_ops, \
2155 .reg = _reg, \
2156 .inputs = _inputs, \
2157 .flags = _flags, \
2158 .max_rate = _max, \
2159 .u.periph = { \
2160 .clk_num = _clk_num, \
2161 }, \
2162 }
2163
2164#define SHARED_CLK(_name, _dev, _con, _parent) \
2165 { \
2166 .name = _name, \
2167 .lookup = { \
2168 .dev_id = _dev, \
2169 .con_id = _con, \
2170 }, \
2171 .ops = &tegra_clk_shared_bus_ops, \
2172 .parent = _parent, \
2173 }
2174
2175static struct clk tegra_list_clks[] = {
2176 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
2177 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2178 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2179 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2187 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2188 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2189 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2190 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2191 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2192 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2193 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2194 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2195 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2196 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2197 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2198 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2199 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2200 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2201 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2202 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2203 /* FIXME: what is la? */
2204 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2205 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2206 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2207 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2208 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2209 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2210 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2211 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2212 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2213 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2214 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2215 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2216 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2217 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2218 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2219 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2220 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2221 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2222 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2223 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2224 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2225 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2226 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2227 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2228 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2229 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2230 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2231 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2232 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2233 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2234 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2235 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2236 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2237 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2238 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2239 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2240 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2241 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2242 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2243 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2244
2245 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2246 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2247 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2248 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2249 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2250 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2251 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2252 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2253 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2254 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2255 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2256};
2257
2258#define CLK_DUPLICATE(_name, _dev, _con) \
2259 { \
2260 .name = _name, \
2261 .lookup = { \
2262 .dev_id = _dev, \
2263 .con_id = _con, \
2264 }, \
2265 }
2266
2267/* Some clocks may be used by different drivers depending on the board
2268 * configuration. List those here to register them twice in the clock lookup
2269 * table under two names.
2270 */
2271static struct clk_duplicate tegra_clk_duplicates[] = {
2272 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2273 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2274 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2275 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2276 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2277 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2278 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2285 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2286 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2287 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2288 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2289};
2290
2291#define CLK(dev, con, ck) \
2292 { \
2293 .dev_id = dev, \
2294 .con_id = con, \
2295 .clk = ck, \
2296 }
2297
2298static struct clk *tegra_ptr_clks[] = {
2299 &tegra_clk_32k,
2300 &tegra_pll_s,
2301 &tegra_clk_m,
2302 &tegra_pll_m,
2303 &tegra_pll_m_out1,
2304 &tegra_pll_c,
2305 &tegra_pll_c_out1,
2306 &tegra_pll_p,
2307 &tegra_pll_p_out1,
2308 &tegra_pll_p_out2,
2309 &tegra_pll_p_out3,
2310 &tegra_pll_p_out4,
2311 &tegra_pll_a,
2312 &tegra_pll_a_out0,
2313 &tegra_pll_d,
2314 &tegra_pll_d_out0,
2315 &tegra_pll_u,
2316 &tegra_pll_x,
2317 &tegra_pll_e,
2318 &tegra_clk_cclk,
2319 &tegra_clk_sclk,
2320 &tegra_clk_hclk,
2321 &tegra_clk_pclk,
2322 &tegra_clk_d,
2323 &tegra_clk_cdev1,
2324 &tegra_clk_cdev2,
2325 &tegra_clk_virtual_cpu,
2326 &tegra_clk_blink,
2327 &tegra_clk_cop,
2328 &tegra_clk_emc,
2329};
2330
2331static void tegra2_init_one_clock(struct clk *c)
2332{
2333 clk_init(c);
2334 INIT_LIST_HEAD(&c->shared_bus_list);
2335 if (!c->lookup.dev_id && !c->lookup.con_id)
2336 c->lookup.con_id = c->name;
2337 c->lookup.clk = c;
2338 clkdev_add(&c->lookup);
2339}
2340
2341void __init tegra2_init_clocks(void)
2342{
2343 int i;
2344 struct clk *c;
2345
2346 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2347 tegra2_init_one_clock(tegra_ptr_clks[i]);
2348
2349 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2350 tegra2_init_one_clock(&tegra_list_clks[i]);
2351
2352 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2353 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2354 if (!c) {
2355 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2356 tegra_clk_duplicates[i].name);
2357 continue;
2358 }
2359
2360 tegra_clk_duplicates[i].lookup.clk = c;
2361 clkdev_add(&tegra_clk_duplicates[i].lookup);
2362 }
2363
2364 init_audio_sync_clock_mux();
2365}
2366
2367#ifdef CONFIG_PM
2368static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2369 PERIPH_CLK_SOURCE_NUM + 22];
2370
2371void tegra_clk_suspend(void)
2372{
2373 unsigned long off, i;
2374 u32 *ctx = clk_rst_suspend;
2375
2376 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2377 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2378 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2379 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2380 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2381 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2382 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2383 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2384 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2385 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2386 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2387
2388 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2389 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2390 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2391
2392 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2393 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2394
2395 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2396 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2397 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2398
2399 *ctx++ = clk_readl(tegra_clk_audio.reg);
2400
2401 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2402 off += 4) {
2403 if (off == PERIPH_CLK_SOURCE_EMC)
2404 continue;
2405 *ctx++ = clk_readl(off);
2406 }
2407
2408 off = RST_DEVICES;
2409 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2410 *ctx++ = clk_readl(off);
2411
2412 off = CLK_OUT_ENB;
2413 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2414 *ctx++ = clk_readl(off);
2415
2416 *ctx++ = clk_readl(MISC_CLK_ENB);
2417 *ctx++ = clk_readl(CLK_MASK_ARM);
2418
2419 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2420}
2421
2422void tegra_clk_resume(void)
2423{
2424 unsigned long off, i;
2425 const u32 *ctx = clk_rst_suspend;
2426 u32 val;
2427
2428 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2429 val |= *ctx++;
2430 clk_writel(val, OSC_CTRL);
2431
2432 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2433 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2434 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2435 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2436 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2437 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2438 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2439 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2440 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2441 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2442 udelay(1000);
2443
2444 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2445 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2446 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2447
2448 clk_writel(*ctx++, tegra_clk_cclk.reg);
2449 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2450
2451 clk_writel(*ctx++, tegra_clk_sclk.reg);
2452 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2453 clk_writel(*ctx++, tegra_clk_pclk.reg);
2454
2455 clk_writel(*ctx++, tegra_clk_audio.reg);
2456
2457 /* enable all clocks before configuring clock sources */
2458 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2459 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2460 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2461 wmb();
2462
2463 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2464 off += 4) {
2465 if (off == PERIPH_CLK_SOURCE_EMC)
2466 continue;
2467 clk_writel(*ctx++, off);
2468 }
2469 wmb();
2470
2471 off = RST_DEVICES;
2472 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2473 clk_writel(*ctx++, off);
2474 wmb();
2475
2476 off = CLK_OUT_ENB;
2477 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2478 clk_writel(*ctx++, off);
2479 wmb();
2480
2481 clk_writel(*ctx++, MISC_CLK_ENB);
2482 clk_writel(*ctx++, CLK_MASK_ARM);
2483}
2484#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..5cd502c27163 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c 2 * arch/arm/mach-tegra/tegra30_clocks.c
3 * 3 *
4 * Copyright (c) 2010-2011 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -35,6 +35,7 @@
35 35
36#include "clock.h" 36#include "clock.h"
37#include "fuse.h" 37#include "fuse.h"
38#include "tegra_cpu_car.h"
38 39
39#define USE_PLL_LOCK_BITS 0 40#define USE_PLL_LOCK_BITS 0
40 41
@@ -299,6 +300,16 @@
299/* FIXME: recommended safety delay after lock is detected */ 300/* FIXME: recommended safety delay after lock is detected */
300#define PLL_POST_LOCK_DELAY 100 301#define PLL_POST_LOCK_DELAY 100
301 302
303/* Tegra CPU clock and reset control regs */
304#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
305#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
306#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
307#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
308#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
309
310#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
311#define CPU_RESET(cpu) (0x1111ul << (cpu))
312
302/** 313/**
303* Structure defining the fields for USB UTMI clocks Parameters. 314* Structure defining the fields for USB UTMI clocks Parameters.
304*/ 315*/
@@ -365,30 +376,32 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
365static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; 376static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
366 377
367#define clk_writel(value, reg) \ 378#define clk_writel(value, reg) \
368 __raw_writel(value, (u32)reg_clk_base + (reg)) 379 __raw_writel(value, reg_clk_base + (reg))
369#define clk_readl(reg) \ 380#define clk_readl(reg) \
370 __raw_readl((u32)reg_clk_base + (reg)) 381 __raw_readl(reg_clk_base + (reg))
371#define pmc_writel(value, reg) \ 382#define pmc_writel(value, reg) \
372 __raw_writel(value, (u32)reg_pmc_base + (reg)) 383 __raw_writel(value, reg_pmc_base + (reg))
373#define pmc_readl(reg) \ 384#define pmc_readl(reg) \
374 __raw_readl((u32)reg_pmc_base + (reg)) 385 __raw_readl(reg_pmc_base + (reg))
375#define chipid_readl() \ 386#define chipid_readl() \
376 __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV) 387 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
377 388
378#define clk_writel_delay(value, reg) \ 389#define clk_writel_delay(value, reg) \
379 do { \ 390 do { \
380 __raw_writel((value), (u32)reg_clk_base + (reg)); \ 391 __raw_writel((value), reg_clk_base + (reg)); \
381 udelay(2); \ 392 udelay(2); \
382 } while (0) 393 } while (0)
383 394
384 395static inline int clk_set_div(struct clk_tegra *c, u32 n)
385static inline int clk_set_div(struct clk *c, u32 n)
386{ 396{
387 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); 397 struct clk *clk = c->hw.clk;
398
399 return clk_set_rate(clk,
400 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
388} 401}
389 402
390static inline u32 periph_clk_to_reg( 403static inline u32 periph_clk_to_reg(
391 struct clk *c, u32 reg_L, u32 reg_V, int offs) 404 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
392{ 405{
393 u32 reg = c->u.periph.clk_num / 32; 406 u32 reg = c->u.periph.clk_num / 32;
394 BUG_ON(reg >= RST_DEVICES_NUM); 407 BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +483,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
470 return divider_u16 - 1; 483 return divider_u16 - 1;
471} 484}
472 485
486static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
487 unsigned long parent_rate)
488{
489 return to_clk_tegra(hw)->fixed_rate;
490}
491
492struct clk_ops tegra30_clk_32k_ops = {
493 .recalc_rate = tegra30_clk_fixed_recalc_rate,
494};
495
473/* clk_m functions */ 496/* clk_m functions */
474static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c) 497static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
498 unsigned long parent_rate)
499{
500 if (!to_clk_tegra(hw)->fixed_rate)
501 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
502 return to_clk_tegra(hw)->fixed_rate;
503}
504
505static void tegra30_clk_m_init(struct clk_hw *hw)
475{ 506{
476 u32 osc_ctrl = clk_readl(OSC_CTRL); 507 u32 osc_ctrl = clk_readl(OSC_CTRL);
477 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; 508 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
478 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 509 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
479 510
480 c->rate = clk_measure_input_freq(); 511 switch (to_clk_tegra(hw)->fixed_rate) {
481 switch (c->rate) {
482 case 12000000: 512 case 12000000:
483 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; 513 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
484 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 514 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +538,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
508 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 538 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
509 break; 539 break;
510 default: 540 default:
511 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); 541 pr_err("%s: Unexpected clock rate %ld", __func__,
542 to_clk_tegra(hw)->fixed_rate);
512 BUG(); 543 BUG();
513 } 544 }
514 clk_writel(auto_clock_control, OSC_CTRL); 545 clk_writel(auto_clock_control, OSC_CTRL);
515 return c->rate;
516} 546}
517 547
518static void tegra30_clk_m_init(struct clk *c) 548struct clk_ops tegra30_clk_m_ops = {
519{ 549 .init = tegra30_clk_m_init,
520 pr_debug("%s on clock %s\n", __func__, c->name); 550 .recalc_rate = tegra30_clk_m_recalc_rate,
521 tegra30_clk_m_autodetect_rate(c); 551};
522}
523 552
524static int tegra30_clk_m_enable(struct clk *c) 553static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
554 unsigned long parent_rate)
525{ 555{
526 pr_debug("%s on clock %s\n", __func__, c->name); 556 struct clk_tegra *c = to_clk_tegra(hw);
527 return 0; 557 u64 rate = parent_rate;
528}
529 558
530static void tegra30_clk_m_disable(struct clk *c) 559 if (c->mul != 0 && c->div != 0) {
531{ 560 rate *= c->mul;
532 pr_debug("%s on clock %s\n", __func__, c->name); 561 rate += c->div - 1; /* round up */
533 WARN(1, "Attempting to disable main SoC clock\n"); 562 do_div(rate, c->div);
534} 563 }
535 564
536static struct clk_ops tegra_clk_m_ops = { 565 return rate;
537 .init = tegra30_clk_m_init, 566}
538 .enable = tegra30_clk_m_enable,
539 .disable = tegra30_clk_m_disable,
540};
541 567
542static struct clk_ops tegra_clk_m_div_ops = { 568struct clk_ops tegra_clk_m_div_ops = {
543 .enable = tegra30_clk_m_enable, 569 .recalc_rate = tegra30_clk_m_div_recalc_rate,
544}; 570};
545 571
546/* PLL reference divider functions */ 572/* PLL reference divider functions */
547static void tegra30_pll_ref_init(struct clk *c) 573static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
574 unsigned long parent_rate)
548{ 575{
576 struct clk_tegra *c = to_clk_tegra(hw);
577 unsigned long rate = parent_rate;
549 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; 578 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
550 pr_debug("%s on clock %s\n", __func__, c->name);
551 579
552 switch (pll_ref_div) { 580 switch (pll_ref_div) {
553 case OSC_CTRL_PLL_REF_DIV_1: 581 case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +592,18 @@ static void tegra30_pll_ref_init(struct clk *c)
564 BUG(); 592 BUG();
565 } 593 }
566 c->mul = 1; 594 c->mul = 1;
567 c->state = ON; 595
596 if (c->mul != 0 && c->div != 0) {
597 rate *= c->mul;
598 rate += c->div - 1; /* round up */
599 do_div(rate, c->div);
600 }
601
602 return rate;
568} 603}
569 604
570static struct clk_ops tegra_pll_ref_ops = { 605struct clk_ops tegra_pll_ref_ops = {
571 .init = tegra30_pll_ref_init, 606 .recalc_rate = tegra30_pll_ref_recalc_rate,
572 .enable = tegra30_clk_m_enable,
573 .disable = tegra30_clk_m_disable,
574}; 607};
575 608
576/* super clock functions */ 609/* super clock functions */
@@ -581,56 +614,50 @@ static struct clk_ops tegra_pll_ref_ops = {
581 * only when its parent is a fixed rate PLL, since we can't change PLL rate 614 * only when its parent is a fixed rate PLL, since we can't change PLL rate
582 * in this case. 615 * in this case.
583 */ 616 */
584static void tegra30_super_clk_init(struct clk *c) 617static void tegra30_super_clk_init(struct clk_hw *hw)
585{ 618{
586 u32 val; 619 struct clk_tegra *c = to_clk_tegra(hw);
587 int source; 620 struct clk_tegra *p =
588 int shift; 621 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
589 const struct clk_mux_sel *sel;
590 val = clk_readl(c->reg + SUPER_CLK_MUX);
591 c->state = ON;
592 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
593 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
594 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
595 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
596 source = (val >> shift) & SUPER_SOURCE_MASK;
597 if (c->flags & DIV_2)
598 source |= val & SUPER_LP_DIV2_BYPASS;
599 for (sel = c->inputs; sel->input != NULL; sel++) {
600 if (sel->value == source)
601 break;
602 }
603 BUG_ON(sel->input == NULL);
604 c->parent = sel->input;
605 622
623 c->state = ON;
606 if (c->flags & DIV_U71) { 624 if (c->flags & DIV_U71) {
607 /* Init safe 7.1 divider value (does not affect PLLX path) */ 625 /* Init safe 7.1 divider value (does not affect PLLX path) */
608 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, 626 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
609 c->reg + SUPER_CLK_DIVIDER); 627 c->reg + SUPER_CLK_DIVIDER);
610 c->mul = 2; 628 c->mul = 2;
611 c->div = 2; 629 c->div = 2;
612 if (!(c->parent->flags & PLLX)) 630 if (!(p->flags & PLLX))
613 c->div += SUPER_CLOCK_DIV_U71_MIN; 631 c->div += SUPER_CLOCK_DIV_U71_MIN;
614 } else 632 } else
615 clk_writel(0, c->reg + SUPER_CLK_DIVIDER); 633 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
616} 634}
617 635
618static int tegra30_super_clk_enable(struct clk *c) 636static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
619{ 637{
620 return 0; 638 struct clk_tegra *c = to_clk_tegra(hw);
621} 639 u32 val;
640 int source;
641 int shift;
622 642
623static void tegra30_super_clk_disable(struct clk *c) 643 val = clk_readl(c->reg + SUPER_CLK_MUX);
624{ 644 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
625 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and 645 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
626 geared up g-mode super clock - mode switch may request to disable 646 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
627 either of them; accept request with no affect on h/w */ 647 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
648 source = (val >> shift) & SUPER_SOURCE_MASK;
649 if (c->flags & DIV_2)
650 source |= val & SUPER_LP_DIV2_BYPASS;
651
652 return source;
628} 653}
629 654
630static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p) 655static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
631{ 656{
657 struct clk_tegra *c = to_clk_tegra(hw);
658 struct clk_tegra *p =
659 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
632 u32 val; 660 u32 val;
633 const struct clk_mux_sel *sel;
634 int shift; 661 int shift;
635 662
636 val = clk_readl(c->reg + SUPER_CLK_MUX); 663 val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +665,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
638 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 665 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
639 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 666 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
640 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; 667 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
641 for (sel = c->inputs; sel->input != NULL; sel++) {
642 if (sel->input == p) {
643 /* For LP mode super-clock switch between PLLX direct
644 and divided-by-2 outputs is allowed only when other
645 than PLLX clock source is current parent */
646 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
647 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
648 if (c->parent->flags & PLLX)
649 return -EINVAL;
650 val ^= SUPER_LP_DIV2_BYPASS;
651 clk_writel_delay(val, c->reg);
652 }
653 val &= ~(SUPER_SOURCE_MASK << shift);
654 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
655
656 /* 7.1 divider for CPU super-clock does not affect
657 PLLX path */
658 if (c->flags & DIV_U71) {
659 u32 div = 0;
660 if (!(p->flags & PLLX)) {
661 div = clk_readl(c->reg +
662 SUPER_CLK_DIVIDER);
663 div &= SUPER_CLOCK_DIV_U71_MASK;
664 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
665 }
666 c->div = div + 2;
667 c->mul = 2;
668 }
669
670 if (c->refcnt)
671 clk_enable(p);
672
673 clk_writel_delay(val, c->reg);
674 668
675 if (c->refcnt && c->parent) 669 /* For LP mode super-clock switch between PLLX direct
676 clk_disable(c->parent); 670 and divided-by-2 outputs is allowed only when other
671 than PLLX clock source is current parent */
672 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
673 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
674 if (p->flags & PLLX)
675 return -EINVAL;
676 val ^= SUPER_LP_DIV2_BYPASS;
677 clk_writel_delay(val, c->reg);
678 }
679 val &= ~(SUPER_SOURCE_MASK << shift);
680 val |= (index & SUPER_SOURCE_MASK) << shift;
677 681
678 clk_reparent(c, p); 682 /* 7.1 divider for CPU super-clock does not affect
679 return 0; 683 PLLX path */
684 if (c->flags & DIV_U71) {
685 u32 div = 0;
686 if (!(p->flags & PLLX)) {
687 div = clk_readl(c->reg +
688 SUPER_CLK_DIVIDER);
689 div &= SUPER_CLOCK_DIV_U71_MASK;
690 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
680 } 691 }
692 c->div = div + 2;
693 c->mul = 2;
681 } 694 }
682 return -EINVAL; 695 clk_writel_delay(val, c->reg);
696
697 return 0;
683} 698}
684 699
685/* 700/*
@@ -691,10 +706,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
691 * rate of this PLL can't be changed, and it has many other children. In 706 * rate of this PLL can't be changed, and it has many other children. In
692 * this case use 7.1 fractional divider to adjust the super clock rate. 707 * this case use 7.1 fractional divider to adjust the super clock rate.
693 */ 708 */
694static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate) 709static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
710 unsigned long parent_rate)
695{ 711{
696 if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) { 712 struct clk_tegra *c = to_clk_tegra(hw);
697 int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate, 713 struct clk *parent = __clk_get_parent(hw->clk);
714 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
715
716 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
717 int div = clk_div71_get_divider(parent_rate,
698 rate, c->flags, ROUND_DIVIDER_DOWN); 718 rate, c->flags, ROUND_DIVIDER_DOWN);
699 div = max(div, SUPER_CLOCK_DIV_U71_MIN); 719 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
700 720
@@ -704,55 +724,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
704 c->mul = 2; 724 c->mul = 2;
705 return 0; 725 return 0;
706 } 726 }
707 return clk_set_rate(c->parent, rate); 727 return 0;
728}
729
730static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
731 unsigned long parent_rate)
732{
733 struct clk_tegra *c = to_clk_tegra(hw);
734 u64 rate = parent_rate;
735
736 if (c->mul != 0 && c->div != 0) {
737 rate *= c->mul;
738 rate += c->div - 1; /* round up */
739 do_div(rate, c->div);
740 }
741
742 return rate;
708} 743}
709 744
710static struct clk_ops tegra_super_ops = { 745static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
711 .init = tegra30_super_clk_init, 746 unsigned long *prate)
712 .enable = tegra30_super_clk_enable, 747{
713 .disable = tegra30_super_clk_disable, 748 struct clk_tegra *c = to_clk_tegra(hw);
714 .set_parent = tegra30_super_clk_set_parent, 749 struct clk *parent = __clk_get_parent(hw->clk);
715 .set_rate = tegra30_super_clk_set_rate, 750 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
751 int mul = 2;
752 int div;
753
754 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
755 div = clk_div71_get_divider(*prate,
756 rate, c->flags, ROUND_DIVIDER_DOWN);
757 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
758 rate = *prate * mul;
759 rate += div - 1; /* round up */
760 do_div(rate, c->div);
761
762 return rate;
763 }
764 return *prate;
765}
766
767struct clk_ops tegra30_super_ops = {
768 .init = tegra30_super_clk_init,
769 .set_parent = tegra30_super_clk_set_parent,
770 .get_parent = tegra30_super_clk_get_parent,
771 .recalc_rate = tegra30_super_clk_recalc_rate,
772 .round_rate = tegra30_super_clk_round_rate,
773 .set_rate = tegra30_super_clk_set_rate,
716}; 774};
717 775
718static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate) 776static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
777 unsigned long parent_rate)
719{ 778{
720 /* The input value 'rate' is the clock rate of the CPU complex. */ 779 struct clk_tegra *c = to_clk_tegra(hw);
721 c->rate = (rate * c->mul) / c->div; 780 u64 rate = parent_rate;
722 return 0; 781
782 if (c->mul != 0 && c->div != 0) {
783 rate *= c->mul;
784 rate += c->div - 1; /* round up */
785 do_div(rate, c->div);
786 }
787
788 return rate;
723} 789}
724 790
725static struct clk_ops tegra30_twd_ops = { 791struct clk_ops tegra30_twd_ops = {
726 .set_rate = tegra30_twd_clk_set_rate, 792 .recalc_rate = tegra30_twd_clk_recalc_rate,
727}; 793};
728 794
729/* Blink output functions */ 795/* Blink output functions */
730 796static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
731static void tegra30_blink_clk_init(struct clk *c)
732{ 797{
798 struct clk_tegra *c = to_clk_tegra(hw);
733 u32 val; 799 u32 val;
734 800
735 val = pmc_readl(PMC_CTRL); 801 val = pmc_readl(PMC_CTRL);
736 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; 802 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
737 c->mul = 1; 803 return c->state;
738 val = pmc_readl(c->reg);
739
740 if (val & PMC_BLINK_TIMER_ENB) {
741 unsigned int on_off;
742
743 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
744 PMC_BLINK_TIMER_DATA_ON_MASK;
745 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
746 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
747 on_off += val;
748 /* each tick in the blink timer is 4 32KHz clocks */
749 c->div = on_off * 4;
750 } else {
751 c->div = 1;
752 }
753} 804}
754 805
755static int tegra30_blink_clk_enable(struct clk *c) 806static int tegra30_blink_clk_enable(struct clk_hw *hw)
756{ 807{
757 u32 val; 808 u32 val;
758 809
@@ -765,7 +816,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
765 return 0; 816 return 0;
766} 817}
767 818
768static void tegra30_blink_clk_disable(struct clk *c) 819static void tegra30_blink_clk_disable(struct clk_hw *hw)
769{ 820{
770 u32 val; 821 u32 val;
771 822
@@ -776,9 +827,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
776 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); 827 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
777} 828}
778 829
779static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate) 830static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
831 unsigned long parent_rate)
780{ 832{
781 unsigned long parent_rate = clk_get_rate(c->parent); 833 struct clk_tegra *c = to_clk_tegra(hw);
834
782 if (rate >= parent_rate) { 835 if (rate >= parent_rate) {
783 c->div = 1; 836 c->div = 1;
784 pmc_writel(0, c->reg); 837 pmc_writel(0, c->reg);
@@ -801,41 +854,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
801 return 0; 854 return 0;
802} 855}
803 856
804static struct clk_ops tegra_blink_clk_ops = { 857static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
805 .init = &tegra30_blink_clk_init, 858 unsigned long parent_rate)
806 .enable = &tegra30_blink_clk_enable, 859{
807 .disable = &tegra30_blink_clk_disable, 860 struct clk_tegra *c = to_clk_tegra(hw);
808 .set_rate = &tegra30_blink_clk_set_rate, 861 u64 rate = parent_rate;
809}; 862 u32 val;
863 u32 mul;
864 u32 div;
865 u32 on_off;
810 866
811/* PLL Functions */ 867 mul = 1;
812static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, 868 val = pmc_readl(c->reg);
813 u32 lock_bit) 869
870 if (val & PMC_BLINK_TIMER_ENB) {
871 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
872 PMC_BLINK_TIMER_DATA_ON_MASK;
873 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
874 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
875 on_off += val;
876 /* each tick in the blink timer is 4 32KHz clocks */
877 div = on_off * 4;
878 } else {
879 div = 1;
880 }
881
882 if (mul != 0 && div != 0) {
883 rate *= mul;
884 rate += div - 1; /* round up */
885 do_div(rate, div);
886 }
887 return rate;
888}
889
890static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
891 unsigned long *prate)
814{ 892{
815#if USE_PLL_LOCK_BITS 893 int div;
816 int i; 894 int mul;
817 for (i = 0; i < c->u.pll.lock_delay; i++) { 895 long round_rate = *prate;
818 if (clk_readl(lock_reg) & lock_bit) { 896
819 udelay(PLL_POST_LOCK_DELAY); 897 mul = 1;
820 return 0; 898
821 } 899 if (rate >= *prate) {
822 udelay(2); /* timeout = 2 * lock time */ 900 div = 1;
901 } else {
902 div = DIV_ROUND_UP(*prate / 8, rate);
903 div *= 8;
823 } 904 }
824 pr_err("Timed out waiting for lock bit on pll %s", c->name);
825 return -1;
826#endif
827 udelay(c->u.pll.lock_delay);
828 905
829 return 0; 906 round_rate *= mul;
907 round_rate += div - 1;
908 do_div(round_rate, div);
909
910 return round_rate;
830} 911}
831 912
913struct clk_ops tegra30_blink_clk_ops = {
914 .is_enabled = tegra30_blink_clk_is_enabled,
915 .enable = tegra30_blink_clk_enable,
916 .disable = tegra30_blink_clk_disable,
917 .recalc_rate = tegra30_blink_clk_recalc_rate,
918 .round_rate = tegra30_blink_clk_round_rate,
919 .set_rate = tegra30_blink_clk_set_rate,
920};
832 921
833static void tegra30_utmi_param_configure(struct clk *c) 922static void tegra30_utmi_param_configure(struct clk_hw *hw)
834{ 923{
924 unsigned long main_rate =
925 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
835 u32 reg; 926 u32 reg;
836 int i; 927 int i;
837 unsigned long main_rate =
838 clk_get_rate(c->parent->parent);
839 928
840 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 929 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
841 if (main_rate == utmi_parameters[i].osc_frequency) 930 if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +975,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
886 clk_writel(reg, UTMIP_PLL_CFG1); 975 clk_writel(reg, UTMIP_PLL_CFG1);
887} 976}
888 977
889static void tegra30_pll_clk_init(struct clk *c) 978/* PLL Functions */
979static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
980 u32 lock_bit)
981{
982 int ret = 0;
983
984#if USE_PLL_LOCK_BITS
985 int i;
986 for (i = 0; i < c->u.pll.lock_delay; i++) {
987 if (clk_readl(lock_reg) & lock_bit) {
988 udelay(PLL_POST_LOCK_DELAY);
989 return 0;
990 }
991 udelay(2); /* timeout = 2 * lock time */
992 }
993 pr_err("Timed out waiting for lock bit on pll %s",
994 __clk_get_name(hw->clk));
995 ret = -1;
996#else
997 udelay(c->u.pll.lock_delay);
998#endif
999 return ret;
1000}
1001
1002static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
890{ 1003{
1004 struct clk_tegra *c = to_clk_tegra(hw);
891 u32 val = clk_readl(c->reg + PLL_BASE); 1005 u32 val = clk_readl(c->reg + PLL_BASE);
892 1006
893 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; 1007 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1008 return c->state;
1009}
894 1010
895 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { 1011static void tegra30_pll_clk_init(struct clk_hw *hw)
896 const struct clk_pll_freq_table *sel; 1012{
897 unsigned long input_rate = clk_get_rate(c->parent); 1013 struct clk_tegra *c = to_clk_tegra(hw);
898 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
899 if (sel->input_rate == input_rate &&
900 sel->output_rate == c->u.pll.fixed_rate) {
901 c->mul = sel->n;
902 c->div = sel->m * sel->p;
903 return;
904 }
905 }
906 pr_err("Clock %s has unknown fixed frequency\n", c->name);
907 BUG();
908 } else if (val & PLL_BASE_BYPASS) {
909 c->mul = 1;
910 c->div = 1;
911 } else {
912 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
913 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
914 if (c->flags & PLLU)
915 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
916 else
917 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
918 PLL_BASE_DIVP_SHIFT));
919 if (c->flags & PLL_FIXED) {
920 unsigned long rate = clk_get_rate_locked(c);
921 BUG_ON(rate != c->u.pll.fixed_rate);
922 }
923 }
924 1014
925 if (c->flags & PLLU) 1015 if (c->flags & PLLU)
926 tegra30_utmi_param_configure(c); 1016 tegra30_utmi_param_configure(hw);
927} 1017}
928 1018
929static int tegra30_pll_clk_enable(struct clk *c) 1019static int tegra30_pll_clk_enable(struct clk_hw *hw)
930{ 1020{
1021 struct clk_tegra *c = to_clk_tegra(hw);
931 u32 val; 1022 u32 val;
932 pr_debug("%s on clock %s\n", __func__, c->name); 1023 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
933 1024
934#if USE_PLL_LOCK_BITS 1025#if USE_PLL_LOCK_BITS
935 val = clk_readl(c->reg + PLL_MISC(c)); 1026 val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1043,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
952 return 0; 1043 return 0;
953} 1044}
954 1045
955static void tegra30_pll_clk_disable(struct clk *c) 1046static void tegra30_pll_clk_disable(struct clk_hw *hw)
956{ 1047{
1048 struct clk_tegra *c = to_clk_tegra(hw);
957 u32 val; 1049 u32 val;
958 pr_debug("%s on clock %s\n", __func__, c->name); 1050 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
959 1051
960 val = clk_readl(c->reg); 1052 val = clk_readl(c->reg);
961 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1053 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1060,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
968 } 1060 }
969} 1061}
970 1062
971static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate) 1063static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1064 unsigned long parent_rate)
972{ 1065{
1066 struct clk_tegra *c = to_clk_tegra(hw);
973 u32 val, p_div, old_base; 1067 u32 val, p_div, old_base;
974 unsigned long input_rate; 1068 unsigned long input_rate;
975 const struct clk_pll_freq_table *sel; 1069 const struct clk_pll_freq_table *sel;
976 struct clk_pll_freq_table cfg; 1070 struct clk_pll_freq_table cfg;
977 1071
978 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
979
980 if (c->flags & PLL_FIXED) { 1072 if (c->flags & PLL_FIXED) {
981 int ret = 0; 1073 int ret = 0;
982 if (rate != c->u.pll.fixed_rate) { 1074 if (rate != c->u.pll.fixed_rate) {
983 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 1075 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
984 __func__, c->name, c->u.pll.fixed_rate, rate); 1076 __func__, __clk_get_name(hw->clk),
1077 c->u.pll.fixed_rate, rate);
985 ret = -EINVAL; 1078 ret = -EINVAL;
986 } 1079 }
987 return ret; 1080 return ret;
988 } 1081 }
989 1082
990 if (c->flags & PLLM) { 1083 if (c->flags & PLLM) {
991 if (rate != clk_get_rate_locked(c)) { 1084 if (rate != __clk_get_rate(hw->clk)) {
992 pr_err("%s: Can not change memory %s rate in flight\n", 1085 pr_err("%s: Can not change memory %s rate in flight\n",
993 __func__, c->name); 1086 __func__, __clk_get_name(hw->clk));
994 return -EINVAL; 1087 return -EINVAL;
995 } 1088 }
996 return 0;
997 } 1089 }
998 1090
999 p_div = 0; 1091 p_div = 0;
1000 input_rate = clk_get_rate(c->parent); 1092 input_rate = parent_rate;
1001 1093
1002 /* Check if the target rate is tabulated */ 1094 /* Check if the target rate is tabulated */
1003 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1095 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1147,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1055 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || 1147 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1056 (cfg.output_rate > c->u.pll.vco_max)) { 1148 (cfg.output_rate > c->u.pll.vco_max)) {
1057 pr_err("%s: Failed to set %s out-of-table rate %lu\n", 1149 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1058 __func__, c->name, rate); 1150 __func__, __clk_get_name(hw->clk), rate);
1059 return -EINVAL; 1151 return -EINVAL;
1060 } 1152 }
1061 p_div <<= PLL_BASE_DIVP_SHIFT; 1153 p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1165,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1073 return 0; 1165 return 0;
1074 1166
1075 if (c->state == ON) { 1167 if (c->state == ON) {
1076 tegra30_pll_clk_disable(c); 1168 tegra30_pll_clk_disable(hw);
1077 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1169 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1078 } 1170 }
1079 clk_writel(val, c->reg + PLL_BASE); 1171 clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1187,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1095 } 1187 }
1096 1188
1097 if (c->state == ON) 1189 if (c->state == ON)
1098 tegra30_pll_clk_enable(c); 1190 tegra30_pll_clk_enable(hw);
1191
1192 c->u.pll.fixed_rate = rate;
1099 1193
1100 return 0; 1194 return 0;
1101} 1195}
1102 1196
1103static struct clk_ops tegra_pll_ops = { 1197static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1104 .init = tegra30_pll_clk_init, 1198 unsigned long *prate)
1105 .enable = tegra30_pll_clk_enable, 1199{
1106 .disable = tegra30_pll_clk_disable, 1200 struct clk_tegra *c = to_clk_tegra(hw);
1107 .set_rate = tegra30_pll_clk_set_rate, 1201 unsigned long input_rate = *prate;
1202 unsigned long output_rate = *prate;
1203 const struct clk_pll_freq_table *sel;
1204 struct clk_pll_freq_table cfg;
1205 int mul;
1206 int div;
1207 u32 p_div;
1208 u32 val;
1209
1210 if (c->flags & PLL_FIXED)
1211 return c->u.pll.fixed_rate;
1212
1213 if (c->flags & PLLM)
1214 return __clk_get_rate(hw->clk);
1215
1216 p_div = 0;
1217 /* Check if the target rate is tabulated */
1218 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1219 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1220 if (c->flags & PLLU) {
1221 BUG_ON(sel->p < 1 || sel->p > 2);
1222 if (sel->p == 1)
1223 p_div = PLLU_BASE_POST_DIV;
1224 } else {
1225 BUG_ON(sel->p < 1);
1226 for (val = sel->p; val > 1; val >>= 1)
1227 p_div++;
1228 p_div <<= PLL_BASE_DIVP_SHIFT;
1229 }
1230 break;
1231 }
1232 }
1233
1234 if (sel->input_rate == 0) {
1235 unsigned long cfreq;
1236 BUG_ON(c->flags & PLLU);
1237 sel = &cfg;
1238
1239 switch (input_rate) {
1240 case 12000000:
1241 case 26000000:
1242 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1243 break;
1244 case 13000000:
1245 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1246 break;
1247 case 16800000:
1248 case 19200000:
1249 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1250 break;
1251 default:
1252 pr_err("%s: Unexpected reference rate %lu\n",
1253 __func__, input_rate);
1254 BUG();
1255 }
1256
1257 /* Raise VCO to guarantee 0.5% accuracy */
1258 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1259 cfg.output_rate <<= 1)
1260 p_div++;
1261
1262 cfg.p = 0x1 << p_div;
1263 cfg.m = input_rate / cfreq;
1264 cfg.n = cfg.output_rate / cfreq;
1265 }
1266
1267 mul = sel->n;
1268 div = sel->m * sel->p;
1269
1270 output_rate *= mul;
1271 output_rate += div - 1; /* round up */
1272 do_div(output_rate, div);
1273
1274 return output_rate;
1275}
1276
1277static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1278 unsigned long parent_rate)
1279{
1280 struct clk_tegra *c = to_clk_tegra(hw);
1281 u64 rate = parent_rate;
1282 u32 val = clk_readl(c->reg + PLL_BASE);
1283
1284 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1285 const struct clk_pll_freq_table *sel;
1286 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1287 if (sel->input_rate == parent_rate &&
1288 sel->output_rate == c->u.pll.fixed_rate) {
1289 c->mul = sel->n;
1290 c->div = sel->m * sel->p;
1291 break;
1292 }
1293 }
1294 pr_err("Clock %s has unknown fixed frequency\n",
1295 __clk_get_name(hw->clk));
1296 BUG();
1297 } else if (val & PLL_BASE_BYPASS) {
1298 c->mul = 1;
1299 c->div = 1;
1300 } else {
1301 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1302 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1303 if (c->flags & PLLU)
1304 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1305 else
1306 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1307 PLL_BASE_DIVP_SHIFT));
1308 }
1309
1310 if (c->mul != 0 && c->div != 0) {
1311 rate *= c->mul;
1312 rate += c->div - 1; /* round up */
1313 do_div(rate, c->div);
1314 }
1315
1316 return rate;
1317}
1318
1319struct clk_ops tegra30_pll_ops = {
1320 .is_enabled = tegra30_pll_clk_is_enabled,
1321 .init = tegra30_pll_clk_init,
1322 .enable = tegra30_pll_clk_enable,
1323 .disable = tegra30_pll_clk_disable,
1324 .recalc_rate = tegra30_pll_recalc_rate,
1325 .round_rate = tegra30_pll_round_rate,
1326 .set_rate = tegra30_pll_clk_set_rate,
1108}; 1327};
1109 1328
1110static int 1329int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1111tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1330 enum tegra_clk_ex_param p, u32 setting)
1112{ 1331{
1332 struct clk_tegra *c = to_clk_tegra(hw);
1113 u32 val, mask, reg; 1333 u32 val, mask, reg;
1114 1334
1115 switch (p) { 1335 switch (p) {
@@ -1141,41 +1361,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1141 return 0; 1361 return 0;
1142} 1362}
1143 1363
1144static struct clk_ops tegra_plld_ops = { 1364static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1145 .init = tegra30_pll_clk_init,
1146 .enable = tegra30_pll_clk_enable,
1147 .disable = tegra30_pll_clk_disable,
1148 .set_rate = tegra30_pll_clk_set_rate,
1149 .clk_cfg_ex = tegra30_plld_clk_cfg_ex,
1150};
1151
1152static void tegra30_plle_clk_init(struct clk *c)
1153{ 1365{
1366 struct clk_tegra *c = to_clk_tegra(hw);
1154 u32 val; 1367 u32 val;
1155 1368
1156 val = clk_readl(PLLE_AUX);
1157 c->parent = (val & PLLE_AUX_PLLP_SEL) ?
1158 tegra_get_clock_by_name("pll_p") :
1159 tegra_get_clock_by_name("pll_ref");
1160
1161 val = clk_readl(c->reg + PLL_BASE); 1369 val = clk_readl(c->reg + PLL_BASE);
1162 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; 1370 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1163 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; 1371 return c->state;
1164 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1165 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1166} 1372}
1167 1373
1168static void tegra30_plle_clk_disable(struct clk *c) 1374static void tegra30_plle_clk_disable(struct clk_hw *hw)
1169{ 1375{
1376 struct clk_tegra *c = to_clk_tegra(hw);
1170 u32 val; 1377 u32 val;
1171 pr_debug("%s on clock %s\n", __func__, c->name);
1172 1378
1173 val = clk_readl(c->reg + PLL_BASE); 1379 val = clk_readl(c->reg + PLL_BASE);
1174 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); 1380 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1175 clk_writel(val, c->reg + PLL_BASE); 1381 clk_writel(val, c->reg + PLL_BASE);
1176} 1382}
1177 1383
1178static void tegra30_plle_training(struct clk *c) 1384static void tegra30_plle_training(struct clk_tegra *c)
1179{ 1385{
1180 u32 val; 1386 u32 val;
1181 1387
@@ -1198,12 +1404,15 @@ static void tegra30_plle_training(struct clk *c)
1198 } while (!(val & PLLE_MISC_READY)); 1404 } while (!(val & PLLE_MISC_READY));
1199} 1405}
1200 1406
1201static int tegra30_plle_configure(struct clk *c, bool force_training) 1407static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1202{ 1408{
1203 u32 val; 1409 struct clk_tegra *c = to_clk_tegra(hw);
1410 struct clk *parent = __clk_get_parent(hw->clk);
1204 const struct clk_pll_freq_table *sel; 1411 const struct clk_pll_freq_table *sel;
1412 u32 val;
1413
1205 unsigned long rate = c->u.pll.fixed_rate; 1414 unsigned long rate = c->u.pll.fixed_rate;
1206 unsigned long input_rate = clk_get_rate(c->parent); 1415 unsigned long input_rate = __clk_get_rate(parent);
1207 1416
1208 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1417 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1209 if (sel->input_rate == input_rate && sel->output_rate == rate) 1418 if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1423,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1214 return -ENOSYS; 1423 return -ENOSYS;
1215 1424
1216 /* disable PLLE, clear setup fiels */ 1425 /* disable PLLE, clear setup fiels */
1217 tegra30_plle_clk_disable(c); 1426 tegra30_plle_clk_disable(hw);
1218 1427
1219 val = clk_readl(c->reg + PLL_MISC(c)); 1428 val = clk_readl(c->reg + PLL_MISC(c));
1220 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 1429 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1461,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1252 return 0; 1461 return 0;
1253} 1462}
1254 1463
1255static int tegra30_plle_clk_enable(struct clk *c) 1464static int tegra30_plle_clk_enable(struct clk_hw *hw)
1465{
1466 struct clk_tegra *c = to_clk_tegra(hw);
1467
1468 return tegra30_plle_configure(hw, !c->set);
1469}
1470
1471static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1472 unsigned long parent_rate)
1256{ 1473{
1257 pr_debug("%s on clock %s\n", __func__, c->name); 1474 struct clk_tegra *c = to_clk_tegra(hw);
1258 return tegra30_plle_configure(c, !c->set); 1475 unsigned long rate = parent_rate;
1476 u32 val;
1477
1478 val = clk_readl(c->reg + PLL_BASE);
1479 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1480 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1481 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1482
1483 if (c->mul != 0 && c->div != 0) {
1484 rate *= c->mul;
1485 rate += c->div - 1; /* round up */
1486 do_div(rate, c->div);
1487 }
1488 return rate;
1259} 1489}
1260 1490
1261static struct clk_ops tegra_plle_ops = { 1491struct clk_ops tegra30_plle_ops = {
1262 .init = tegra30_plle_clk_init, 1492 .is_enabled = tegra30_plle_clk_is_enabled,
1263 .enable = tegra30_plle_clk_enable, 1493 .enable = tegra30_plle_clk_enable,
1264 .disable = tegra30_plle_clk_disable, 1494 .disable = tegra30_plle_clk_disable,
1495 .recalc_rate = tegra30_plle_clk_recalc_rate,
1265}; 1496};
1266 1497
1267/* Clock divider ops */ 1498/* Clock divider ops */
1268static void tegra30_pll_div_clk_init(struct clk *c) 1499static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1269{ 1500{
1501 struct clk_tegra *c = to_clk_tegra(hw);
1502
1270 if (c->flags & DIV_U71) { 1503 if (c->flags & DIV_U71) {
1271 u32 divu71;
1272 u32 val = clk_readl(c->reg); 1504 u32 val = clk_readl(c->reg);
1273 val >>= c->reg_shift; 1505 val >>= c->reg_shift;
1274 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; 1506 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1275 if (!(val & PLL_OUT_RESET_DISABLE)) 1507 if (!(val & PLL_OUT_RESET_DISABLE))
1276 c->state = OFF; 1508 c->state = OFF;
1277
1278 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1279 c->div = (divu71 + 2);
1280 c->mul = 2;
1281 } else if (c->flags & DIV_2) {
1282 c->state = ON;
1283 if (c->flags & (PLLD | PLLX)) {
1284 c->div = 2;
1285 c->mul = 1;
1286 } else
1287 BUG();
1288 } else { 1509 } else {
1289 c->state = ON; 1510 c->state = ON;
1290 c->div = 1;
1291 c->mul = 1;
1292 } 1511 }
1512 return c->state;
1293} 1513}
1294 1514
1295static int tegra30_pll_div_clk_enable(struct clk *c) 1515static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1296{ 1516{
1517 struct clk_tegra *c = to_clk_tegra(hw);
1297 u32 val; 1518 u32 val;
1298 u32 new_val; 1519 u32 new_val;
1299 1520
1300 pr_debug("%s: %s\n", __func__, c->name); 1521 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1301 if (c->flags & DIV_U71) { 1522 if (c->flags & DIV_U71) {
1302 val = clk_readl(c->reg); 1523 val = clk_readl(c->reg);
1303 new_val = val >> c->reg_shift; 1524 new_val = val >> c->reg_shift;
@@ -1315,12 +1536,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
1315 return -EINVAL; 1536 return -EINVAL;
1316} 1537}
1317 1538
1318static void tegra30_pll_div_clk_disable(struct clk *c) 1539static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1319{ 1540{
1541 struct clk_tegra *c = to_clk_tegra(hw);
1320 u32 val; 1542 u32 val;
1321 u32 new_val; 1543 u32 new_val;
1322 1544
1323 pr_debug("%s: %s\n", __func__, c->name); 1545 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1324 if (c->flags & DIV_U71) { 1546 if (c->flags & DIV_U71) {
1325 val = clk_readl(c->reg); 1547 val = clk_readl(c->reg);
1326 new_val = val >> c->reg_shift; 1548 new_val = val >> c->reg_shift;
@@ -1334,14 +1556,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
1334 } 1556 }
1335} 1557}
1336 1558
1337static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate) 1559static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1560 unsigned long parent_rate)
1338{ 1561{
1562 struct clk_tegra *c = to_clk_tegra(hw);
1339 u32 val; 1563 u32 val;
1340 u32 new_val; 1564 u32 new_val;
1341 int divider_u71; 1565 int divider_u71;
1342 unsigned long parent_rate = clk_get_rate(c->parent);
1343 1566
1344 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1345 if (c->flags & DIV_U71) { 1567 if (c->flags & DIV_U71) {
1346 divider_u71 = clk_div71_get_divider( 1568 divider_u71 = clk_div71_get_divider(
1347 parent_rate, rate, c->flags, ROUND_DIVIDER_UP); 1569 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1581,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
1359 clk_writel_delay(val, c->reg); 1581 clk_writel_delay(val, c->reg);
1360 c->div = divider_u71 + 2; 1582 c->div = divider_u71 + 2;
1361 c->mul = 2; 1583 c->mul = 2;
1584 c->fixed_rate = rate;
1362 return 0; 1585 return 0;
1363 } 1586 }
1364 } else if (c->flags & DIV_2) 1587 } else if (c->flags & DIV_2) {
1365 return clk_set_rate(c->parent, rate * 2); 1588 c->fixed_rate = rate;
1589 return 0;
1590 }
1366 1591
1367 return -EINVAL; 1592 return -EINVAL;
1368} 1593}
1369 1594
1370static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate) 1595static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1596 unsigned long parent_rate)
1597{
1598 struct clk_tegra *c = to_clk_tegra(hw);
1599 u64 rate = parent_rate;
1600
1601 if (c->flags & DIV_U71) {
1602 u32 divu71;
1603 u32 val = clk_readl(c->reg);
1604 val >>= c->reg_shift;
1605
1606 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1607 c->div = (divu71 + 2);
1608 c->mul = 2;
1609 } else if (c->flags & DIV_2) {
1610 if (c->flags & (PLLD | PLLX)) {
1611 c->div = 2;
1612 c->mul = 1;
1613 } else
1614 BUG();
1615 } else {
1616 c->div = 1;
1617 c->mul = 1;
1618 }
1619 if (c->mul != 0 && c->div != 0) {
1620 rate *= c->mul;
1621 rate += c->div - 1; /* round up */
1622 do_div(rate, c->div);
1623 }
1624
1625 return rate;
1626}
1627
1628static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1629 unsigned long rate, unsigned long *prate)
1371{ 1630{
1631 struct clk_tegra *c = to_clk_tegra(hw);
1632 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1372 int divider; 1633 int divider;
1373 unsigned long parent_rate = clk_get_rate(c->parent); 1634
1374 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1635 if (prate)
1636 parent_rate = *prate;
1375 1637
1376 if (c->flags & DIV_U71) { 1638 if (c->flags & DIV_U71) {
1377 divider = clk_div71_get_divider( 1639 divider = clk_div71_get_divider(
@@ -1379,23 +1641,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1379 if (divider < 0) 1641 if (divider < 0)
1380 return divider; 1642 return divider;
1381 return DIV_ROUND_UP(parent_rate * 2, divider + 2); 1643 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1382 } else if (c->flags & DIV_2) 1644 } else if (c->flags & DIV_2) {
1383 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ 1645 *prate = rate * 2;
1384 return rate; 1646 return rate;
1647 }
1385 1648
1386 return -EINVAL; 1649 return -EINVAL;
1387} 1650}
1388 1651
1389static struct clk_ops tegra_pll_div_ops = { 1652struct clk_ops tegra30_pll_div_ops = {
1390 .init = tegra30_pll_div_clk_init, 1653 .is_enabled = tegra30_pll_div_clk_is_enabled,
1391 .enable = tegra30_pll_div_clk_enable, 1654 .enable = tegra30_pll_div_clk_enable,
1392 .disable = tegra30_pll_div_clk_disable, 1655 .disable = tegra30_pll_div_clk_disable,
1393 .set_rate = tegra30_pll_div_clk_set_rate, 1656 .set_rate = tegra30_pll_div_clk_set_rate,
1394 .round_rate = tegra30_pll_div_clk_round_rate, 1657 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1658 .round_rate = tegra30_pll_div_clk_round_rate,
1395}; 1659};
1396 1660
1397/* Periph clk ops */ 1661/* Periph clk ops */
1398static inline u32 periph_clk_source_mask(struct clk *c) 1662static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1399{ 1663{
1400 if (c->flags & MUX8) 1664 if (c->flags & MUX8)
1401 return 7 << 29; 1665 return 7 << 29;
@@ -1409,7 +1673,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
1409 return 3 << 30; 1673 return 3 << 30;
1410} 1674}
1411 1675
1412static inline u32 periph_clk_source_shift(struct clk *c) 1676static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1413{ 1677{
1414 if (c->flags & MUX8) 1678 if (c->flags & MUX8)
1415 return 29; 1679 return 29;
@@ -1423,47 +1687,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
1423 return 30; 1687 return 30;
1424} 1688}
1425 1689
1426static void tegra30_periph_clk_init(struct clk *c) 1690static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1427{ 1691{
1428 u32 val = clk_readl(c->reg); 1692 struct clk_tegra *c = to_clk_tegra(hw);
1429 const struct clk_mux_sel *mux = 0;
1430 const struct clk_mux_sel *sel;
1431 if (c->flags & MUX) {
1432 for (sel = c->inputs; sel->input != NULL; sel++) {
1433 if (((val & periph_clk_source_mask(c)) >>
1434 periph_clk_source_shift(c)) == sel->value)
1435 mux = sel;
1436 }
1437 BUG_ON(!mux);
1438
1439 c->parent = mux->input;
1440 } else {
1441 c->parent = c->inputs[0].input;
1442 }
1443
1444 if (c->flags & DIV_U71) {
1445 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1446 if ((c->flags & DIV_U71_UART) &&
1447 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1448 divu71 = 0;
1449 }
1450 if (c->flags & DIV_U71_IDLE) {
1451 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1452 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1453 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1454 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1455 clk_writel(val, c->reg);
1456 }
1457 c->div = divu71 + 2;
1458 c->mul = 2;
1459 } else if (c->flags & DIV_U16) {
1460 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1461 c->div = divu16 + 1;
1462 c->mul = 1;
1463 } else {
1464 c->div = 1;
1465 c->mul = 1;
1466 }
1467 1693
1468 c->state = ON; 1694 c->state = ON;
1469 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 1695 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1697,12 @@ static void tegra30_periph_clk_init(struct clk *c)
1471 if (!(c->flags & PERIPH_NO_RESET)) 1697 if (!(c->flags & PERIPH_NO_RESET))
1472 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) 1698 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1473 c->state = OFF; 1699 c->state = OFF;
1700 return c->state;
1474} 1701}
1475 1702
1476static int tegra30_periph_clk_enable(struct clk *c) 1703static int tegra30_periph_clk_enable(struct clk_hw *hw)
1477{ 1704{
1478 pr_debug("%s on clock %s\n", __func__, c->name); 1705 struct clk_tegra *c = to_clk_tegra(hw);
1479 1706
1480 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; 1707 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1481 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) 1708 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1721,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
1494 return 0; 1721 return 0;
1495} 1722}
1496 1723
1497static void tegra30_periph_clk_disable(struct clk *c) 1724static void tegra30_periph_clk_disable(struct clk_hw *hw)
1498{ 1725{
1726 struct clk_tegra *c = to_clk_tegra(hw);
1499 unsigned long val; 1727 unsigned long val;
1500 pr_debug("%s on clock %s\n", __func__, c->name);
1501 1728
1502 if (c->refcnt) 1729 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1503 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; 1730
1731 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1732 return;
1504 1733
1505 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { 1734 /* If peripheral is in the APB bus then read the APB bus to
1506 /* If peripheral is in the APB bus then read the APB bus to 1735 * flush the write operation in apb bus. This will avoid the
1507 * flush the write operation in apb bus. This will avoid the 1736 * peripheral access after disabling clock*/
1508 * peripheral access after disabling clock*/ 1737 if (c->flags & PERIPH_ON_APB)
1509 if (c->flags & PERIPH_ON_APB) 1738 val = chipid_readl();
1510 val = chipid_readl();
1511 1739
1512 clk_writel_delay( 1740 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1513 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1514 }
1515} 1741}
1516 1742
1517static void tegra30_periph_clk_reset(struct clk *c, bool assert) 1743void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1518{ 1744{
1745 struct clk_tegra *c = to_clk_tegra(hw);
1519 unsigned long val; 1746 unsigned long val;
1520 pr_debug("%s %s on clock %s\n", __func__,
1521 assert ? "assert" : "deassert", c->name);
1522 1747
1523 if (!(c->flags & PERIPH_NO_RESET)) { 1748 if (!(c->flags & PERIPH_NO_RESET)) {
1524 if (assert) { 1749 if (assert) {
@@ -1537,42 +1762,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
1537 } 1762 }
1538} 1763}
1539 1764
1540static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p) 1765static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1541{ 1766{
1767 struct clk_tegra *c = to_clk_tegra(hw);
1542 u32 val; 1768 u32 val;
1543 const struct clk_mux_sel *sel;
1544 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1545 1769
1546 if (!(c->flags & MUX)) 1770 if (!(c->flags & MUX))
1547 return (p == c->parent) ? 0 : (-EINVAL); 1771 return (index == 0) ? 0 : (-EINVAL);
1548
1549 for (sel = c->inputs; sel->input != NULL; sel++) {
1550 if (sel->input == p) {
1551 val = clk_readl(c->reg);
1552 val &= ~periph_clk_source_mask(c);
1553 val |= (sel->value << periph_clk_source_shift(c));
1554
1555 if (c->refcnt)
1556 clk_enable(p);
1557 1772
1558 clk_writel_delay(val, c->reg); 1773 val = clk_readl(c->reg);
1774 val &= ~periph_clk_source_mask(c);
1775 val |= (index << periph_clk_source_shift(c));
1776 clk_writel_delay(val, c->reg);
1777 return 0;
1778}
1559 1779
1560 if (c->refcnt && c->parent) 1780static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1561 clk_disable(c->parent); 1781{
1782 struct clk_tegra *c = to_clk_tegra(hw);
1783 u32 val = clk_readl(c->reg);
1784 int source = (val & periph_clk_source_mask(c)) >>
1785 periph_clk_source_shift(c);
1562 1786
1563 clk_reparent(c, p); 1787 if (!(c->flags & MUX))
1564 return 0; 1788 return 0;
1565 }
1566 }
1567 1789
1568 return -EINVAL; 1790 return source;
1569} 1791}
1570 1792
1571static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate) 1793static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1794 unsigned long parent_rate)
1572{ 1795{
1796 struct clk_tegra *c = to_clk_tegra(hw);
1573 u32 val; 1797 u32 val;
1574 int divider; 1798 int divider;
1575 unsigned long parent_rate = clk_get_rate(c->parent);
1576 1799
1577 if (c->flags & DIV_U71) { 1800 if (c->flags & DIV_U71) {
1578 divider = clk_div71_get_divider( 1801 divider = clk_div71_get_divider(
@@ -1611,12 +1834,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
1611 return -EINVAL; 1834 return -EINVAL;
1612} 1835}
1613 1836
1614static long tegra30_periph_clk_round_rate(struct clk *c, 1837static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1615 unsigned long rate) 1838 unsigned long *prate)
1616{ 1839{
1840 struct clk_tegra *c = to_clk_tegra(hw);
1841 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1617 int divider; 1842 int divider;
1618 unsigned long parent_rate = clk_get_rate(c->parent); 1843
1619 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1844 if (prate)
1845 parent_rate = *prate;
1620 1846
1621 if (c->flags & DIV_U71) { 1847 if (c->flags & DIV_U71) {
1622 divider = clk_div71_get_divider( 1848 divider = clk_div71_get_divider(
@@ -1634,21 +1860,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
1634 return -EINVAL; 1860 return -EINVAL;
1635} 1861}
1636 1862
1637static struct clk_ops tegra_periph_clk_ops = { 1863static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1638 .init = &tegra30_periph_clk_init, 1864 unsigned long parent_rate)
1865{
1866 struct clk_tegra *c = to_clk_tegra(hw);
1867 u64 rate = parent_rate;
1868 u32 val = clk_readl(c->reg);
1869
1870 if (c->flags & DIV_U71) {
1871 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1872 if ((c->flags & DIV_U71_UART) &&
1873 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1874 divu71 = 0;
1875 }
1876 if (c->flags & DIV_U71_IDLE) {
1877 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1878 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1879 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1880 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1881 clk_writel(val, c->reg);
1882 }
1883 c->div = divu71 + 2;
1884 c->mul = 2;
1885 } else if (c->flags & DIV_U16) {
1886 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1887 c->div = divu16 + 1;
1888 c->mul = 1;
1889 } else {
1890 c->div = 1;
1891 c->mul = 1;
1892 }
1893
1894 if (c->mul != 0 && c->div != 0) {
1895 rate *= c->mul;
1896 rate += c->div - 1; /* round up */
1897 do_div(rate, c->div);
1898 }
1899 return rate;
1900}
1901
1902struct clk_ops tegra30_periph_clk_ops = {
1903 .is_enabled = tegra30_periph_clk_is_enabled,
1904 .enable = tegra30_periph_clk_enable,
1905 .disable = tegra30_periph_clk_disable,
1906 .set_parent = tegra30_periph_clk_set_parent,
1907 .get_parent = tegra30_periph_clk_get_parent,
1908 .set_rate = tegra30_periph_clk_set_rate,
1909 .round_rate = tegra30_periph_clk_round_rate,
1910 .recalc_rate = tegra30_periph_clk_recalc_rate,
1911};
1912
1913static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
1914{
1915 struct clk *d = clk_get_sys(NULL, "pll_d");
1916 /* The DSIB parent selection bit is in PLLD base
1917 register - can not do direct r-m-w, must be
1918 protected by PLLD lock */
1919 tegra_clk_cfg_ex(
1920 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
1921
1922 return 0;
1923}
1924
1925struct clk_ops tegra30_dsib_clk_ops = {
1926 .is_enabled = tegra30_periph_clk_is_enabled,
1639 .enable = &tegra30_periph_clk_enable, 1927 .enable = &tegra30_periph_clk_enable,
1640 .disable = &tegra30_periph_clk_disable, 1928 .disable = &tegra30_periph_clk_disable,
1641 .set_parent = &tegra30_periph_clk_set_parent, 1929 .set_parent = &tegra30_dsib_clk_set_parent,
1930 .get_parent = &tegra30_periph_clk_get_parent,
1642 .set_rate = &tegra30_periph_clk_set_rate, 1931 .set_rate = &tegra30_periph_clk_set_rate,
1643 .round_rate = &tegra30_periph_clk_round_rate, 1932 .round_rate = &tegra30_periph_clk_round_rate,
1644 .reset = &tegra30_periph_clk_reset, 1933 .recalc_rate = &tegra30_periph_clk_recalc_rate,
1645}; 1934};
1646 1935
1647
1648/* Periph extended clock configuration ops */ 1936/* Periph extended clock configuration ops */
1649static int 1937int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
1650tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1938 enum tegra_clk_ex_param p, u32 setting)
1651{ 1939{
1940 struct clk_tegra *c = to_clk_tegra(hw);
1941
1652 if (p == TEGRA_CLK_VI_INP_SEL) { 1942 if (p == TEGRA_CLK_VI_INP_SEL) {
1653 u32 val = clk_readl(c->reg); 1943 u32 val = clk_readl(c->reg);
1654 val &= ~PERIPH_CLK_VI_SEL_EX_MASK; 1944 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1950,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1660 return -EINVAL; 1950 return -EINVAL;
1661} 1951}
1662 1952
1663static struct clk_ops tegra_vi_clk_ops = { 1953int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
1664 .init = &tegra30_periph_clk_init, 1954 enum tegra_clk_ex_param p, u32 setting)
1665 .enable = &tegra30_periph_clk_enable,
1666 .disable = &tegra30_periph_clk_disable,
1667 .set_parent = &tegra30_periph_clk_set_parent,
1668 .set_rate = &tegra30_periph_clk_set_rate,
1669 .round_rate = &tegra30_periph_clk_round_rate,
1670 .clk_cfg_ex = &tegra30_vi_clk_cfg_ex,
1671 .reset = &tegra30_periph_clk_reset,
1672};
1673
1674static int
1675tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1676{ 1955{
1956 struct clk_tegra *c = to_clk_tegra(hw);
1957
1677 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { 1958 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
1678 u32 val = clk_readl(c->reg); 1959 u32 val = clk_readl(c->reg);
1679 if (setting) 1960 if (setting)
@@ -1686,21 +1967,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1686 return -EINVAL; 1967 return -EINVAL;
1687} 1968}
1688 1969
1689static struct clk_ops tegra_nand_clk_ops = { 1970int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
1690 .init = &tegra30_periph_clk_init, 1971 enum tegra_clk_ex_param p, u32 setting)
1691 .enable = &tegra30_periph_clk_enable,
1692 .disable = &tegra30_periph_clk_disable,
1693 .set_parent = &tegra30_periph_clk_set_parent,
1694 .set_rate = &tegra30_periph_clk_set_rate,
1695 .round_rate = &tegra30_periph_clk_round_rate,
1696 .clk_cfg_ex = &tegra30_nand_clk_cfg_ex,
1697 .reset = &tegra30_periph_clk_reset,
1698};
1699
1700
1701static int
1702tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1703{ 1972{
1973 struct clk_tegra *c = to_clk_tegra(hw);
1974
1704 if (p == TEGRA_CLK_DTV_INVERT) { 1975 if (p == TEGRA_CLK_DTV_INVERT) {
1705 u32 val = clk_readl(c->reg); 1976 u32 val = clk_readl(c->reg);
1706 if (setting) 1977 if (setting)
@@ -1713,91 +1984,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1713 return -EINVAL; 1984 return -EINVAL;
1714} 1985}
1715 1986
1716static struct clk_ops tegra_dtv_clk_ops = {
1717 .init = &tegra30_periph_clk_init,
1718 .enable = &tegra30_periph_clk_enable,
1719 .disable = &tegra30_periph_clk_disable,
1720 .set_parent = &tegra30_periph_clk_set_parent,
1721 .set_rate = &tegra30_periph_clk_set_rate,
1722 .round_rate = &tegra30_periph_clk_round_rate,
1723 .clk_cfg_ex = &tegra30_dtv_clk_cfg_ex,
1724 .reset = &tegra30_periph_clk_reset,
1725};
1726
1727static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
1728{
1729 const struct clk_mux_sel *sel;
1730 struct clk *d = tegra_get_clock_by_name("pll_d");
1731
1732 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1733
1734 for (sel = c->inputs; sel->input != NULL; sel++) {
1735 if (sel->input == p) {
1736 if (c->refcnt)
1737 clk_enable(p);
1738
1739 /* The DSIB parent selection bit is in PLLD base
1740 register - can not do direct r-m-w, must be
1741 protected by PLLD lock */
1742 tegra_clk_cfg_ex(
1743 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
1744
1745 if (c->refcnt && c->parent)
1746 clk_disable(c->parent);
1747
1748 clk_reparent(c, p);
1749 return 0;
1750 }
1751 }
1752
1753 return -EINVAL;
1754}
1755
1756static struct clk_ops tegra_dsib_clk_ops = {
1757 .init = &tegra30_periph_clk_init,
1758 .enable = &tegra30_periph_clk_enable,
1759 .disable = &tegra30_periph_clk_disable,
1760 .set_parent = &tegra30_dsib_clk_set_parent,
1761 .set_rate = &tegra30_periph_clk_set_rate,
1762 .round_rate = &tegra30_periph_clk_round_rate,
1763 .reset = &tegra30_periph_clk_reset,
1764};
1765
1766/* pciex clock support only reset function */
1767static struct clk_ops tegra_pciex_clk_ops = {
1768 .reset = tegra30_periph_clk_reset,
1769};
1770
1771/* Output clock ops */ 1987/* Output clock ops */
1772 1988
1773static DEFINE_SPINLOCK(clk_out_lock); 1989static DEFINE_SPINLOCK(clk_out_lock);
1774 1990
1775static void tegra30_clk_out_init(struct clk *c) 1991static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
1776{ 1992{
1777 const struct clk_mux_sel *mux = 0; 1993 struct clk_tegra *c = to_clk_tegra(hw);
1778 const struct clk_mux_sel *sel;
1779 u32 val = pmc_readl(c->reg); 1994 u32 val = pmc_readl(c->reg);
1780 1995
1781 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; 1996 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
1782 c->mul = 1; 1997 c->mul = 1;
1783 c->div = 1; 1998 c->div = 1;
1784 1999 return c->state;
1785 for (sel = c->inputs; sel->input != NULL; sel++) {
1786 if (((val & periph_clk_source_mask(c)) >>
1787 periph_clk_source_shift(c)) == sel->value)
1788 mux = sel;
1789 }
1790 BUG_ON(!mux);
1791 c->parent = mux->input;
1792} 2000}
1793 2001
1794static int tegra30_clk_out_enable(struct clk *c) 2002static int tegra30_clk_out_enable(struct clk_hw *hw)
1795{ 2003{
2004 struct clk_tegra *c = to_clk_tegra(hw);
1796 u32 val; 2005 u32 val;
1797 unsigned long flags; 2006 unsigned long flags;
1798 2007
1799 pr_debug("%s on clock %s\n", __func__, c->name);
1800
1801 spin_lock_irqsave(&clk_out_lock, flags); 2008 spin_lock_irqsave(&clk_out_lock, flags);
1802 val = pmc_readl(c->reg); 2009 val = pmc_readl(c->reg);
1803 val |= (0x1 << c->u.periph.clk_num); 2010 val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2014,12 @@ static int tegra30_clk_out_enable(struct clk *c)
1807 return 0; 2014 return 0;
1808} 2015}
1809 2016
1810static void tegra30_clk_out_disable(struct clk *c) 2017static void tegra30_clk_out_disable(struct clk_hw *hw)
1811{ 2018{
2019 struct clk_tegra *c = to_clk_tegra(hw);
1812 u32 val; 2020 u32 val;
1813 unsigned long flags; 2021 unsigned long flags;
1814 2022
1815 pr_debug("%s on clock %s\n", __func__, c->name);
1816
1817 spin_lock_irqsave(&clk_out_lock, flags); 2023 spin_lock_irqsave(&clk_out_lock, flags);
1818 val = pmc_readl(c->reg); 2024 val = pmc_readl(c->reg);
1819 val &= ~(0x1 << c->u.periph.clk_num); 2025 val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2027,59 @@ static void tegra30_clk_out_disable(struct clk *c)
1821 spin_unlock_irqrestore(&clk_out_lock, flags); 2027 spin_unlock_irqrestore(&clk_out_lock, flags);
1822} 2028}
1823 2029
1824static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p) 2030static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
1825{ 2031{
2032 struct clk_tegra *c = to_clk_tegra(hw);
1826 u32 val; 2033 u32 val;
1827 unsigned long flags; 2034 unsigned long flags;
1828 const struct clk_mux_sel *sel;
1829 2035
1830 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 2036 spin_lock_irqsave(&clk_out_lock, flags);
1831 2037 val = pmc_readl(c->reg);
1832 for (sel = c->inputs; sel->input != NULL; sel++) { 2038 val &= ~periph_clk_source_mask(c);
1833 if (sel->input == p) { 2039 val |= (index << periph_clk_source_shift(c));
1834 if (c->refcnt) 2040 pmc_writel(val, c->reg);
1835 clk_enable(p); 2041 spin_unlock_irqrestore(&clk_out_lock, flags);
1836 2042
1837 spin_lock_irqsave(&clk_out_lock, flags); 2043 return 0;
1838 val = pmc_readl(c->reg); 2044}
1839 val &= ~periph_clk_source_mask(c);
1840 val |= (sel->value << periph_clk_source_shift(c));
1841 pmc_writel(val, c->reg);
1842 spin_unlock_irqrestore(&clk_out_lock, flags);
1843 2045
1844 if (c->refcnt && c->parent) 2046static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
1845 clk_disable(c->parent); 2047{
2048 struct clk_tegra *c = to_clk_tegra(hw);
2049 u32 val = pmc_readl(c->reg);
2050 int source;
1846 2051
1847 clk_reparent(c, p); 2052 source = (val & periph_clk_source_mask(c)) >>
1848 return 0; 2053 periph_clk_source_shift(c);
1849 } 2054 return source;
1850 }
1851 return -EINVAL;
1852} 2055}
1853 2056
1854static struct clk_ops tegra_clk_out_ops = { 2057struct clk_ops tegra_clk_out_ops = {
1855 .init = &tegra30_clk_out_init, 2058 .is_enabled = tegra30_clk_out_is_enabled,
1856 .enable = &tegra30_clk_out_enable, 2059 .enable = tegra30_clk_out_enable,
1857 .disable = &tegra30_clk_out_disable, 2060 .disable = tegra30_clk_out_disable,
1858 .set_parent = &tegra30_clk_out_set_parent, 2061 .set_parent = tegra30_clk_out_set_parent,
2062 .get_parent = tegra30_clk_out_get_parent,
2063 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1859}; 2064};
1860 2065
1861
1862/* Clock doubler ops */ 2066/* Clock doubler ops */
1863static void tegra30_clk_double_init(struct clk *c) 2067static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
1864{ 2068{
1865 u32 val = clk_readl(c->reg); 2069 struct clk_tegra *c = to_clk_tegra(hw);
1866 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; 2070
1867 c->div = 1;
1868 c->state = ON; 2071 c->state = ON;
1869 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 2072 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1870 c->state = OFF; 2073 c->state = OFF;
2074 return c->state;
1871}; 2075};
1872 2076
1873static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate) 2077static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2078 unsigned long parent_rate)
1874{ 2079{
2080 struct clk_tegra *c = to_clk_tegra(hw);
1875 u32 val; 2081 u32 val;
1876 unsigned long parent_rate = clk_get_rate(c->parent); 2082
1877 if (rate == parent_rate) { 2083 if (rate == parent_rate) {
1878 val = clk_readl(c->reg) | (0x1 << c->reg_shift); 2084 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
1879 clk_writel(val, c->reg); 2085 clk_writel(val, c->reg);
@@ -1890,1215 +2096,200 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
1890 return -EINVAL; 2096 return -EINVAL;
1891} 2097}
1892 2098
1893static struct clk_ops tegra_clk_double_ops = { 2099static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
1894 .init = &tegra30_clk_double_init, 2100 unsigned long parent_rate)
1895 .enable = &tegra30_periph_clk_enable, 2101{
1896 .disable = &tegra30_periph_clk_disable, 2102 struct clk_tegra *c = to_clk_tegra(hw);
1897 .set_rate = &tegra30_clk_double_set_rate, 2103 u64 rate = parent_rate;
1898};
1899 2104
1900/* Audio sync clock ops */ 2105 u32 val = clk_readl(c->reg);
1901static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate) 2106 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2107 c->div = 1;
2108
2109 if (c->mul != 0 && c->div != 0) {
2110 rate *= c->mul;
2111 rate += c->div - 1; /* round up */
2112 do_div(rate, c->div);
2113 }
2114
2115 return rate;
2116}
2117
2118static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2119 unsigned long *prate)
1902{ 2120{
1903 c->rate = rate; 2121 unsigned long output_rate = *prate;
1904 return 0; 2122
2123 do_div(output_rate, 2);
2124 return output_rate;
1905} 2125}
1906 2126
1907static struct clk_ops tegra_sync_source_ops = { 2127struct clk_ops tegra30_clk_double_ops = {
1908 .set_rate = &tegra30_sync_source_set_rate, 2128 .is_enabled = tegra30_clk_double_is_enabled,
2129 .enable = tegra30_periph_clk_enable,
2130 .disable = tegra30_periph_clk_disable,
2131 .recalc_rate = tegra30_clk_double_recalc_rate,
2132 .round_rate = tegra30_clk_double_round_rate,
2133 .set_rate = tegra30_clk_double_set_rate,
2134};
2135
2136/* Audio sync clock ops */
2137struct clk_ops tegra_sync_source_ops = {
2138 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1909}; 2139};
1910 2140
1911static void tegra30_audio_sync_clk_init(struct clk *c) 2141static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
1912{ 2142{
1913 int source; 2143 struct clk_tegra *c = to_clk_tegra(hw);
1914 const struct clk_mux_sel *sel;
1915 u32 val = clk_readl(c->reg); 2144 u32 val = clk_readl(c->reg);
1916 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; 2145 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
1917 source = val & AUDIO_SYNC_SOURCE_MASK; 2146 return c->state;
1918 for (sel = c->inputs; sel->input != NULL; sel++)
1919 if (sel->value == source)
1920 break;
1921 BUG_ON(sel->input == NULL);
1922 c->parent = sel->input;
1923} 2147}
1924 2148
1925static int tegra30_audio_sync_clk_enable(struct clk *c) 2149static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
1926{ 2150{
2151 struct clk_tegra *c = to_clk_tegra(hw);
1927 u32 val = clk_readl(c->reg); 2152 u32 val = clk_readl(c->reg);
1928 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); 2153 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
1929 return 0; 2154 return 0;
1930} 2155}
1931 2156
1932static void tegra30_audio_sync_clk_disable(struct clk *c) 2157static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
1933{ 2158{
2159 struct clk_tegra *c = to_clk_tegra(hw);
1934 u32 val = clk_readl(c->reg); 2160 u32 val = clk_readl(c->reg);
1935 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); 2161 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
1936} 2162}
1937 2163
1938static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p) 2164static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1939{ 2165{
2166 struct clk_tegra *c = to_clk_tegra(hw);
1940 u32 val; 2167 u32 val;
1941 const struct clk_mux_sel *sel;
1942 for (sel = c->inputs; sel->input != NULL; sel++) {
1943 if (sel->input == p) {
1944 val = clk_readl(c->reg);
1945 val &= ~AUDIO_SYNC_SOURCE_MASK;
1946 val |= sel->value;
1947
1948 if (c->refcnt)
1949 clk_enable(p);
1950 2168
1951 clk_writel(val, c->reg); 2169 val = clk_readl(c->reg);
2170 val &= ~AUDIO_SYNC_SOURCE_MASK;
2171 val |= index;
1952 2172
1953 if (c->refcnt && c->parent) 2173 clk_writel(val, c->reg);
1954 clk_disable(c->parent); 2174 return 0;
2175}
1955 2176
1956 clk_reparent(c, p); 2177static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
1957 return 0; 2178{
1958 } 2179 struct clk_tegra *c = to_clk_tegra(hw);
1959 } 2180 u32 val = clk_readl(c->reg);
2181 int source;
1960 2182
1961 return -EINVAL; 2183 source = val & AUDIO_SYNC_SOURCE_MASK;
2184 return source;
1962} 2185}
1963 2186
1964static struct clk_ops tegra_audio_sync_clk_ops = { 2187struct clk_ops tegra30_audio_sync_clk_ops = {
1965 .init = tegra30_audio_sync_clk_init, 2188 .is_enabled = tegra30_audio_sync_clk_is_enabled,
1966 .enable = tegra30_audio_sync_clk_enable, 2189 .enable = tegra30_audio_sync_clk_enable,
1967 .disable = tegra30_audio_sync_clk_disable, 2190 .disable = tegra30_audio_sync_clk_disable,
1968 .set_parent = tegra30_audio_sync_clk_set_parent, 2191 .set_parent = tegra30_audio_sync_clk_set_parent,
2192 .get_parent = tegra30_audio_sync_clk_get_parent,
2193 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1969}; 2194};
1970 2195
1971/* cml0 (pcie), and cml1 (sata) clock ops */ 2196/* cml0 (pcie), and cml1 (sata) clock ops */
1972static void tegra30_cml_clk_init(struct clk *c) 2197static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
1973{ 2198{
2199 struct clk_tegra *c = to_clk_tegra(hw);
1974 u32 val = clk_readl(c->reg); 2200 u32 val = clk_readl(c->reg);
1975 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; 2201 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2202 return c->state;
1976} 2203}
1977 2204
1978static int tegra30_cml_clk_enable(struct clk *c) 2205static int tegra30_cml_clk_enable(struct clk_hw *hw)
1979{ 2206{
2207 struct clk_tegra *c = to_clk_tegra(hw);
2208
1980 u32 val = clk_readl(c->reg); 2209 u32 val = clk_readl(c->reg);
1981 val |= (0x1 << c->u.periph.clk_num); 2210 val |= (0x1 << c->u.periph.clk_num);
1982 clk_writel(val, c->reg); 2211 clk_writel(val, c->reg);
2212
1983 return 0; 2213 return 0;
1984} 2214}
1985 2215
1986static void tegra30_cml_clk_disable(struct clk *c) 2216static void tegra30_cml_clk_disable(struct clk_hw *hw)
1987{ 2217{
2218 struct clk_tegra *c = to_clk_tegra(hw);
2219
1988 u32 val = clk_readl(c->reg); 2220 u32 val = clk_readl(c->reg);
1989 val &= ~(0x1 << c->u.periph.clk_num); 2221 val &= ~(0x1 << c->u.periph.clk_num);
1990 clk_writel(val, c->reg); 2222 clk_writel(val, c->reg);
1991} 2223}
1992 2224
1993static struct clk_ops tegra_cml_clk_ops = { 2225struct clk_ops tegra_cml_clk_ops = {
1994 .init = &tegra30_cml_clk_init, 2226 .is_enabled = tegra30_cml_clk_is_enabled,
1995 .enable = &tegra30_cml_clk_enable, 2227 .enable = tegra30_cml_clk_enable,
1996 .disable = &tegra30_cml_clk_disable, 2228 .disable = tegra30_cml_clk_disable,
1997}; 2229 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1998
1999/* Clock definitions */
2000static struct clk tegra_clk_32k = {
2001 .name = "clk_32k",
2002 .rate = 32768,
2003 .ops = NULL,
2004 .max_rate = 32768,
2005};
2006
2007static struct clk tegra_clk_m = {
2008 .name = "clk_m",
2009 .flags = ENABLE_ON_INIT,
2010 .ops = &tegra_clk_m_ops,
2011 .reg = 0x1fc,
2012 .reg_shift = 28,
2013 .max_rate = 48000000,
2014};
2015
2016static struct clk tegra_clk_m_div2 = {
2017 .name = "clk_m_div2",
2018 .ops = &tegra_clk_m_div_ops,
2019 .parent = &tegra_clk_m,
2020 .mul = 1,
2021 .div = 2,
2022 .state = ON,
2023 .max_rate = 24000000,
2024};
2025
2026static struct clk tegra_clk_m_div4 = {
2027 .name = "clk_m_div4",
2028 .ops = &tegra_clk_m_div_ops,
2029 .parent = &tegra_clk_m,
2030 .mul = 1,
2031 .div = 4,
2032 .state = ON,
2033 .max_rate = 12000000,
2034};
2035
2036static struct clk tegra_pll_ref = {
2037 .name = "pll_ref",
2038 .flags = ENABLE_ON_INIT,
2039 .ops = &tegra_pll_ref_ops,
2040 .parent = &tegra_clk_m,
2041 .max_rate = 26000000,
2042};
2043
2044static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
2045 { 12000000, 1040000000, 520, 6, 1, 8},
2046 { 13000000, 1040000000, 480, 6, 1, 8},
2047 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
2048 { 19200000, 1040000000, 325, 6, 1, 6},
2049 { 26000000, 1040000000, 520, 13, 1, 8},
2050
2051 { 12000000, 832000000, 416, 6, 1, 8},
2052 { 13000000, 832000000, 832, 13, 1, 8},
2053 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
2054 { 19200000, 832000000, 260, 6, 1, 8},
2055 { 26000000, 832000000, 416, 13, 1, 8},
2056
2057 { 12000000, 624000000, 624, 12, 1, 8},
2058 { 13000000, 624000000, 624, 13, 1, 8},
2059 { 16800000, 600000000, 520, 14, 1, 8},
2060 { 19200000, 624000000, 520, 16, 1, 8},
2061 { 26000000, 624000000, 624, 26, 1, 8},
2062
2063 { 12000000, 600000000, 600, 12, 1, 8},
2064 { 13000000, 600000000, 600, 13, 1, 8},
2065 { 16800000, 600000000, 500, 14, 1, 8},
2066 { 19200000, 600000000, 375, 12, 1, 6},
2067 { 26000000, 600000000, 600, 26, 1, 8},
2068
2069 { 12000000, 520000000, 520, 12, 1, 8},
2070 { 13000000, 520000000, 520, 13, 1, 8},
2071 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
2072 { 19200000, 520000000, 325, 12, 1, 6},
2073 { 26000000, 520000000, 520, 26, 1, 8},
2074
2075 { 12000000, 416000000, 416, 12, 1, 8},
2076 { 13000000, 416000000, 416, 13, 1, 8},
2077 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
2078 { 19200000, 416000000, 260, 12, 1, 6},
2079 { 26000000, 416000000, 416, 26, 1, 8},
2080 { 0, 0, 0, 0, 0, 0 },
2081};
2082
2083static struct clk tegra_pll_c = {
2084 .name = "pll_c",
2085 .flags = PLL_HAS_CPCON,
2086 .ops = &tegra_pll_ops,
2087 .reg = 0x80,
2088 .parent = &tegra_pll_ref,
2089 .max_rate = 1400000000,
2090 .u.pll = {
2091 .input_min = 2000000,
2092 .input_max = 31000000,
2093 .cf_min = 1000000,
2094 .cf_max = 6000000,
2095 .vco_min = 20000000,
2096 .vco_max = 1400000000,
2097 .freq_table = tegra_pll_c_freq_table,
2098 .lock_delay = 300,
2099 },
2100};
2101
2102static struct clk tegra_pll_c_out1 = {
2103 .name = "pll_c_out1",
2104 .ops = &tegra_pll_div_ops,
2105 .flags = DIV_U71,
2106 .parent = &tegra_pll_c,
2107 .reg = 0x84,
2108 .reg_shift = 0,
2109 .max_rate = 700000000,
2110};
2111
2112static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
2113 { 12000000, 666000000, 666, 12, 1, 8},
2114 { 13000000, 666000000, 666, 13, 1, 8},
2115 { 16800000, 666000000, 555, 14, 1, 8},
2116 { 19200000, 666000000, 555, 16, 1, 8},
2117 { 26000000, 666000000, 666, 26, 1, 8},
2118 { 12000000, 600000000, 600, 12, 1, 8},
2119 { 13000000, 600000000, 600, 13, 1, 8},
2120 { 16800000, 600000000, 500, 14, 1, 8},
2121 { 19200000, 600000000, 375, 12, 1, 6},
2122 { 26000000, 600000000, 600, 26, 1, 8},
2123 { 0, 0, 0, 0, 0, 0 },
2124};
2125
2126static struct clk tegra_pll_m = {
2127 .name = "pll_m",
2128 .flags = PLL_HAS_CPCON | PLLM,
2129 .ops = &tegra_pll_ops,
2130 .reg = 0x90,
2131 .parent = &tegra_pll_ref,
2132 .max_rate = 800000000,
2133 .u.pll = {
2134 .input_min = 2000000,
2135 .input_max = 31000000,
2136 .cf_min = 1000000,
2137 .cf_max = 6000000,
2138 .vco_min = 20000000,
2139 .vco_max = 1200000000,
2140 .freq_table = tegra_pll_m_freq_table,
2141 .lock_delay = 300,
2142 },
2143};
2144
2145static struct clk tegra_pll_m_out1 = {
2146 .name = "pll_m_out1",
2147 .ops = &tegra_pll_div_ops,
2148 .flags = DIV_U71,
2149 .parent = &tegra_pll_m,
2150 .reg = 0x94,
2151 .reg_shift = 0,
2152 .max_rate = 600000000,
2153};
2154
2155static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
2156 { 12000000, 216000000, 432, 12, 2, 8},
2157 { 13000000, 216000000, 432, 13, 2, 8},
2158 { 16800000, 216000000, 360, 14, 2, 8},
2159 { 19200000, 216000000, 360, 16, 2, 8},
2160 { 26000000, 216000000, 432, 26, 2, 8},
2161 { 0, 0, 0, 0, 0, 0 },
2162};
2163
2164static struct clk tegra_pll_p = {
2165 .name = "pll_p",
2166 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
2167 .ops = &tegra_pll_ops,
2168 .reg = 0xa0,
2169 .parent = &tegra_pll_ref,
2170 .max_rate = 432000000,
2171 .u.pll = {
2172 .input_min = 2000000,
2173 .input_max = 31000000,
2174 .cf_min = 1000000,
2175 .cf_max = 6000000,
2176 .vco_min = 20000000,
2177 .vco_max = 1400000000,
2178 .freq_table = tegra_pll_p_freq_table,
2179 .lock_delay = 300,
2180 .fixed_rate = 408000000,
2181 },
2182};
2183
2184static struct clk tegra_pll_p_out1 = {
2185 .name = "pll_p_out1",
2186 .ops = &tegra_pll_div_ops,
2187 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2188 .parent = &tegra_pll_p,
2189 .reg = 0xa4,
2190 .reg_shift = 0,
2191 .max_rate = 432000000,
2192};
2193
2194static struct clk tegra_pll_p_out2 = {
2195 .name = "pll_p_out2",
2196 .ops = &tegra_pll_div_ops,
2197 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2198 .parent = &tegra_pll_p,
2199 .reg = 0xa4,
2200 .reg_shift = 16,
2201 .max_rate = 432000000,
2202};
2203
2204static struct clk tegra_pll_p_out3 = {
2205 .name = "pll_p_out3",
2206 .ops = &tegra_pll_div_ops,
2207 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2208 .parent = &tegra_pll_p,
2209 .reg = 0xa8,
2210 .reg_shift = 0,
2211 .max_rate = 432000000,
2212};
2213
2214static struct clk tegra_pll_p_out4 = {
2215 .name = "pll_p_out4",
2216 .ops = &tegra_pll_div_ops,
2217 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2218 .parent = &tegra_pll_p,
2219 .reg = 0xa8,
2220 .reg_shift = 16,
2221 .max_rate = 432000000,
2222};
2223
2224static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
2225 { 9600000, 564480000, 294, 5, 1, 4},
2226 { 9600000, 552960000, 288, 5, 1, 4},
2227 { 9600000, 24000000, 5, 2, 1, 1},
2228
2229 { 28800000, 56448000, 49, 25, 1, 1},
2230 { 28800000, 73728000, 64, 25, 1, 1},
2231 { 28800000, 24000000, 5, 6, 1, 1},
2232 { 0, 0, 0, 0, 0, 0 },
2233};
2234
2235static struct clk tegra_pll_a = {
2236 .name = "pll_a",
2237 .flags = PLL_HAS_CPCON,
2238 .ops = &tegra_pll_ops,
2239 .reg = 0xb0,
2240 .parent = &tegra_pll_p_out1,
2241 .max_rate = 700000000,
2242 .u.pll = {
2243 .input_min = 2000000,
2244 .input_max = 31000000,
2245 .cf_min = 1000000,
2246 .cf_max = 6000000,
2247 .vco_min = 20000000,
2248 .vco_max = 1400000000,
2249 .freq_table = tegra_pll_a_freq_table,
2250 .lock_delay = 300,
2251 },
2252};
2253
2254static struct clk tegra_pll_a_out0 = {
2255 .name = "pll_a_out0",
2256 .ops = &tegra_pll_div_ops,
2257 .flags = DIV_U71,
2258 .parent = &tegra_pll_a,
2259 .reg = 0xb4,
2260 .reg_shift = 0,
2261 .max_rate = 100000000,
2262};
2263
2264static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
2265 { 12000000, 216000000, 216, 12, 1, 4},
2266 { 13000000, 216000000, 216, 13, 1, 4},
2267 { 16800000, 216000000, 180, 14, 1, 4},
2268 { 19200000, 216000000, 180, 16, 1, 4},
2269 { 26000000, 216000000, 216, 26, 1, 4},
2270
2271 { 12000000, 594000000, 594, 12, 1, 8},
2272 { 13000000, 594000000, 594, 13, 1, 8},
2273 { 16800000, 594000000, 495, 14, 1, 8},
2274 { 19200000, 594000000, 495, 16, 1, 8},
2275 { 26000000, 594000000, 594, 26, 1, 8},
2276
2277 { 12000000, 1000000000, 1000, 12, 1, 12},
2278 { 13000000, 1000000000, 1000, 13, 1, 12},
2279 { 19200000, 1000000000, 625, 12, 1, 8},
2280 { 26000000, 1000000000, 1000, 26, 1, 12},
2281
2282 { 0, 0, 0, 0, 0, 0 },
2283};
2284
2285static struct clk tegra_pll_d = {
2286 .name = "pll_d",
2287 .flags = PLL_HAS_CPCON | PLLD,
2288 .ops = &tegra_plld_ops,
2289 .reg = 0xd0,
2290 .parent = &tegra_pll_ref,
2291 .max_rate = 1000000000,
2292 .u.pll = {
2293 .input_min = 2000000,
2294 .input_max = 40000000,
2295 .cf_min = 1000000,
2296 .cf_max = 6000000,
2297 .vco_min = 40000000,
2298 .vco_max = 1000000000,
2299 .freq_table = tegra_pll_d_freq_table,
2300 .lock_delay = 1000,
2301 },
2302};
2303
2304static struct clk tegra_pll_d_out0 = {
2305 .name = "pll_d_out0",
2306 .ops = &tegra_pll_div_ops,
2307 .flags = DIV_2 | PLLD,
2308 .parent = &tegra_pll_d,
2309 .max_rate = 500000000,
2310};
2311
2312static struct clk tegra_pll_d2 = {
2313 .name = "pll_d2",
2314 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
2315 .ops = &tegra_plld_ops,
2316 .reg = 0x4b8,
2317 .parent = &tegra_pll_ref,
2318 .max_rate = 1000000000,
2319 .u.pll = {
2320 .input_min = 2000000,
2321 .input_max = 40000000,
2322 .cf_min = 1000000,
2323 .cf_max = 6000000,
2324 .vco_min = 40000000,
2325 .vco_max = 1000000000,
2326 .freq_table = tegra_pll_d_freq_table,
2327 .lock_delay = 1000,
2328 },
2329};
2330
2331static struct clk tegra_pll_d2_out0 = {
2332 .name = "pll_d2_out0",
2333 .ops = &tegra_pll_div_ops,
2334 .flags = DIV_2 | PLLD,
2335 .parent = &tegra_pll_d2,
2336 .max_rate = 500000000,
2337};
2338
2339static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
2340 { 12000000, 480000000, 960, 12, 2, 12},
2341 { 13000000, 480000000, 960, 13, 2, 12},
2342 { 16800000, 480000000, 400, 7, 2, 5},
2343 { 19200000, 480000000, 200, 4, 2, 3},
2344 { 26000000, 480000000, 960, 26, 2, 12},
2345 { 0, 0, 0, 0, 0, 0 },
2346};
2347
2348static struct clk tegra_pll_u = {
2349 .name = "pll_u",
2350 .flags = PLL_HAS_CPCON | PLLU,
2351 .ops = &tegra_pll_ops,
2352 .reg = 0xc0,
2353 .parent = &tegra_pll_ref,
2354 .max_rate = 480000000,
2355 .u.pll = {
2356 .input_min = 2000000,
2357 .input_max = 40000000,
2358 .cf_min = 1000000,
2359 .cf_max = 6000000,
2360 .vco_min = 480000000,
2361 .vco_max = 960000000,
2362 .freq_table = tegra_pll_u_freq_table,
2363 .lock_delay = 1000,
2364 },
2365};
2366
2367static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
2368 /* 1.7 GHz */
2369 { 12000000, 1700000000, 850, 6, 1, 8},
2370 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
2371 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
2372 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
2373 { 26000000, 1700000000, 850, 13, 1, 8},
2374
2375 /* 1.6 GHz */
2376 { 12000000, 1600000000, 800, 6, 1, 8},
2377 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
2378 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
2379 { 19200000, 1600000000, 500, 6, 1, 8},
2380 { 26000000, 1600000000, 800, 13, 1, 8},
2381
2382 /* 1.5 GHz */
2383 { 12000000, 1500000000, 750, 6, 1, 8},
2384 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
2385 { 16800000, 1500000000, 625, 7, 1, 8},
2386 { 19200000, 1500000000, 625, 8, 1, 8},
2387 { 26000000, 1500000000, 750, 13, 1, 8},
2388
2389 /* 1.4 GHz */
2390 { 12000000, 1400000000, 700, 6, 1, 8},
2391 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
2392 { 16800000, 1400000000, 1000, 12, 1, 8},
2393 { 19200000, 1400000000, 875, 12, 1, 8},
2394 { 26000000, 1400000000, 700, 13, 1, 8},
2395
2396 /* 1.3 GHz */
2397 { 12000000, 1300000000, 975, 9, 1, 8},
2398 { 13000000, 1300000000, 1000, 10, 1, 8},
2399 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
2400 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
2401 { 26000000, 1300000000, 650, 13, 1, 8},
2402
2403 /* 1.2 GHz */
2404 { 12000000, 1200000000, 1000, 10, 1, 8},
2405 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
2406 { 16800000, 1200000000, 1000, 14, 1, 8},
2407 { 19200000, 1200000000, 1000, 16, 1, 8},
2408 { 26000000, 1200000000, 600, 13, 1, 8},
2409
2410 /* 1.1 GHz */
2411 { 12000000, 1100000000, 825, 9, 1, 8},
2412 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
2413 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
2414 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
2415 { 26000000, 1100000000, 550, 13, 1, 8},
2416
2417 /* 1 GHz */
2418 { 12000000, 1000000000, 1000, 12, 1, 8},
2419 { 13000000, 1000000000, 1000, 13, 1, 8},
2420 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
2421 { 19200000, 1000000000, 625, 12, 1, 8},
2422 { 26000000, 1000000000, 1000, 26, 1, 8},
2423
2424 { 0, 0, 0, 0, 0, 0 },
2425};
2426
2427static struct clk tegra_pll_x = {
2428 .name = "pll_x",
2429 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
2430 .ops = &tegra_pll_ops,
2431 .reg = 0xe0,
2432 .parent = &tegra_pll_ref,
2433 .max_rate = 1700000000,
2434 .u.pll = {
2435 .input_min = 2000000,
2436 .input_max = 31000000,
2437 .cf_min = 1000000,
2438 .cf_max = 6000000,
2439 .vco_min = 20000000,
2440 .vco_max = 1700000000,
2441 .freq_table = tegra_pll_x_freq_table,
2442 .lock_delay = 300,
2443 },
2444};
2445
2446static struct clk tegra_pll_x_out0 = {
2447 .name = "pll_x_out0",
2448 .ops = &tegra_pll_div_ops,
2449 .flags = DIV_2 | PLLX,
2450 .parent = &tegra_pll_x,
2451 .max_rate = 850000000,
2452};
2453
2454
2455static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
2456 /* PLLE special case: use cpcon field to store cml divider value */
2457 { 12000000, 100000000, 150, 1, 18, 11},
2458 { 216000000, 100000000, 200, 18, 24, 13},
2459 { 0, 0, 0, 0, 0, 0 },
2460};
2461
2462static struct clk tegra_pll_e = {
2463 .name = "pll_e",
2464 .flags = PLL_ALT_MISC_REG,
2465 .ops = &tegra_plle_ops,
2466 .reg = 0xe8,
2467 .max_rate = 100000000,
2468 .u.pll = {
2469 .input_min = 12000000,
2470 .input_max = 216000000,
2471 .cf_min = 12000000,
2472 .cf_max = 12000000,
2473 .vco_min = 1200000000,
2474 .vco_max = 2400000000U,
2475 .freq_table = tegra_pll_e_freq_table,
2476 .lock_delay = 300,
2477 .fixed_rate = 100000000,
2478 },
2479};
2480
2481static struct clk tegra_cml0_clk = {
2482 .name = "cml0",
2483 .parent = &tegra_pll_e,
2484 .ops = &tegra_cml_clk_ops,
2485 .reg = PLLE_AUX,
2486 .max_rate = 100000000,
2487 .u.periph = {
2488 .clk_num = 0,
2489 },
2490};
2491
2492static struct clk tegra_cml1_clk = {
2493 .name = "cml1",
2494 .parent = &tegra_pll_e,
2495 .ops = &tegra_cml_clk_ops,
2496 .reg = PLLE_AUX,
2497 .max_rate = 100000000,
2498 .u.periph = {
2499 .clk_num = 1,
2500 },
2501};
2502
2503static struct clk tegra_pciex_clk = {
2504 .name = "pciex",
2505 .parent = &tegra_pll_e,
2506 .ops = &tegra_pciex_clk_ops,
2507 .max_rate = 100000000,
2508 .u.periph = {
2509 .clk_num = 74,
2510 },
2511};
2512
2513/* Audio sync clocks */
2514#define SYNC_SOURCE(_id) \
2515 { \
2516 .name = #_id "_sync", \
2517 .rate = 24000000, \
2518 .max_rate = 24000000, \
2519 .ops = &tegra_sync_source_ops \
2520 }
2521static struct clk tegra_sync_source_list[] = {
2522 SYNC_SOURCE(spdif_in),
2523 SYNC_SOURCE(i2s0),
2524 SYNC_SOURCE(i2s1),
2525 SYNC_SOURCE(i2s2),
2526 SYNC_SOURCE(i2s3),
2527 SYNC_SOURCE(i2s4),
2528 SYNC_SOURCE(vimclk),
2529};
2530
2531static struct clk_mux_sel mux_audio_sync_clk[] = {
2532 { .input = &tegra_sync_source_list[0], .value = 0},
2533 { .input = &tegra_sync_source_list[1], .value = 1},
2534 { .input = &tegra_sync_source_list[2], .value = 2},
2535 { .input = &tegra_sync_source_list[3], .value = 3},
2536 { .input = &tegra_sync_source_list[4], .value = 4},
2537 { .input = &tegra_sync_source_list[5], .value = 5},
2538 { .input = &tegra_pll_a_out0, .value = 6},
2539 { .input = &tegra_sync_source_list[6], .value = 7},
2540 { 0, 0 }
2541}; 2230};
2542 2231
2543#define AUDIO_SYNC_CLK(_id, _index) \ 2232struct clk_ops tegra_pciex_clk_ops = {
2544 { \ 2233 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2545 .name = #_id, \
2546 .inputs = mux_audio_sync_clk, \
2547 .reg = 0x4A0 + (_index) * 4, \
2548 .max_rate = 24000000, \
2549 .ops = &tegra_audio_sync_clk_ops \
2550 }
2551static struct clk tegra_clk_audio_list[] = {
2552 AUDIO_SYNC_CLK(audio0, 0),
2553 AUDIO_SYNC_CLK(audio1, 1),
2554 AUDIO_SYNC_CLK(audio2, 2),
2555 AUDIO_SYNC_CLK(audio3, 3),
2556 AUDIO_SYNC_CLK(audio4, 4),
2557 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
2558}; 2234};
2559 2235
2560#define AUDIO_SYNC_2X_CLK(_id, _index) \ 2236/* Tegra30 CPU clock and reset control functions */
2561 { \ 2237static void tegra30_wait_cpu_in_reset(u32 cpu)
2562 .name = #_id "_2x", \ 2238{
2563 .flags = PERIPH_NO_RESET, \ 2239 unsigned int reg;
2564 .max_rate = 48000000, \
2565 .ops = &tegra_clk_double_ops, \
2566 .reg = 0x49C, \
2567 .reg_shift = 24 + (_index), \
2568 .parent = &tegra_clk_audio_list[(_index)], \
2569 .u.periph = { \
2570 .clk_num = 113 + (_index), \
2571 }, \
2572 }
2573static struct clk tegra_clk_audio_2x_list[] = {
2574 AUDIO_SYNC_2X_CLK(audio0, 0),
2575 AUDIO_SYNC_2X_CLK(audio1, 1),
2576 AUDIO_SYNC_2X_CLK(audio2, 2),
2577 AUDIO_SYNC_2X_CLK(audio3, 3),
2578 AUDIO_SYNC_2X_CLK(audio4, 4),
2579 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
2580};
2581 2240
2582#define MUX_I2S_SPDIF(_id, _index) \ 2241 do {
2583static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ 2242 reg = readl(reg_clk_base +
2584 {.input = &tegra_pll_a_out0, .value = 0}, \ 2243 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2585 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ 2244 cpu_relax();
2586 {.input = &tegra_pll_p, .value = 2}, \ 2245 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2587 {.input = &tegra_clk_m, .value = 3}, \
2588 { 0, 0}, \
2589}
2590MUX_I2S_SPDIF(audio0, 0);
2591MUX_I2S_SPDIF(audio1, 1);
2592MUX_I2S_SPDIF(audio2, 2);
2593MUX_I2S_SPDIF(audio3, 3);
2594MUX_I2S_SPDIF(audio4, 4);
2595MUX_I2S_SPDIF(audio, 5); /* SPDIF */
2596
2597/* External clock outputs (through PMC) */
2598#define MUX_EXTERN_OUT(_id) \
2599static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
2600 {.input = &tegra_clk_m, .value = 0}, \
2601 {.input = &tegra_clk_m_div2, .value = 1}, \
2602 {.input = &tegra_clk_m_div4, .value = 2}, \
2603 {.input = NULL, .value = 3}, /* placeholder */ \
2604 { 0, 0}, \
2605}
2606MUX_EXTERN_OUT(1);
2607MUX_EXTERN_OUT(2);
2608MUX_EXTERN_OUT(3);
2609
2610static struct clk_mux_sel *mux_extern_out_list[] = {
2611 mux_clkm_clkm2_clkm4_extern1,
2612 mux_clkm_clkm2_clkm4_extern2,
2613 mux_clkm_clkm2_clkm4_extern3,
2614};
2615 2246
2616#define CLK_OUT_CLK(_id) \ 2247 return;
2617 { \ 2248}
2618 .name = "clk_out_" #_id, \
2619 .lookup = { \
2620 .dev_id = "clk_out_" #_id, \
2621 .con_id = "extern" #_id, \
2622 }, \
2623 .ops = &tegra_clk_out_ops, \
2624 .reg = 0x1a8, \
2625 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
2626 .flags = MUX_CLK_OUT, \
2627 .max_rate = 216000000, \
2628 .u.periph = { \
2629 .clk_num = (_id - 1) * 8 + 2, \
2630 }, \
2631 }
2632static struct clk tegra_clk_out_list[] = {
2633 CLK_OUT_CLK(1),
2634 CLK_OUT_CLK(2),
2635 CLK_OUT_CLK(3),
2636};
2637 2249
2638/* called after peripheral external clocks are initialized */ 2250static void tegra30_put_cpu_in_reset(u32 cpu)
2639static void init_clk_out_mux(void)
2640{ 2251{
2641 int i; 2252 writel(CPU_RESET(cpu),
2642 struct clk *c; 2253 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
2643 2254 dmb();
2644 /* output clock con_id is the name of peripheral
2645 external clock connected to input 3 of the output mux */
2646 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
2647 c = tegra_get_clock_by_name(
2648 tegra_clk_out_list[i].lookup.con_id);
2649 if (!c)
2650 pr_err("%s: could not find clk %s\n", __func__,
2651 tegra_clk_out_list[i].lookup.con_id);
2652 mux_extern_out_list[i][3].input = c;
2653 }
2654} 2255}
2655 2256
2656/* Peripheral muxes */ 2257static void tegra30_cpu_out_of_reset(u32 cpu)
2657static struct clk_mux_sel mux_sclk[] = {
2658 { .input = &tegra_clk_m, .value = 0},
2659 { .input = &tegra_pll_c_out1, .value = 1},
2660 { .input = &tegra_pll_p_out4, .value = 2},
2661 { .input = &tegra_pll_p_out3, .value = 3},
2662 { .input = &tegra_pll_p_out2, .value = 4},
2663 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
2664 { .input = &tegra_clk_32k, .value = 6},
2665 { .input = &tegra_pll_m_out1, .value = 7},
2666 { 0, 0},
2667};
2668
2669static struct clk tegra_clk_sclk = {
2670 .name = "sclk",
2671 .inputs = mux_sclk,
2672 .reg = 0x28,
2673 .ops = &tegra_super_ops,
2674 .max_rate = 334000000,
2675 .min_rate = 40000000,
2676};
2677
2678static struct clk tegra_clk_blink = {
2679 .name = "blink",
2680 .parent = &tegra_clk_32k,
2681 .reg = 0x40,
2682 .ops = &tegra_blink_clk_ops,
2683 .max_rate = 32768,
2684};
2685
2686static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2687 { .input = &tegra_pll_m, .value = 0},
2688 { .input = &tegra_pll_c, .value = 1},
2689 { .input = &tegra_pll_p, .value = 2},
2690 { .input = &tegra_pll_a_out0, .value = 3},
2691 { 0, 0},
2692};
2693
2694static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2695 { .input = &tegra_pll_p, .value = 0},
2696 { .input = &tegra_pll_c, .value = 1},
2697 { .input = &tegra_pll_m, .value = 2},
2698 { .input = &tegra_clk_m, .value = 3},
2699 { 0, 0},
2700};
2701
2702static struct clk_mux_sel mux_pllp_clkm[] = {
2703 { .input = &tegra_pll_p, .value = 0},
2704 { .input = &tegra_clk_m, .value = 3},
2705 { 0, 0},
2706};
2707
2708static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2709 {.input = &tegra_pll_p, .value = 0},
2710 {.input = &tegra_pll_d_out0, .value = 1},
2711 {.input = &tegra_pll_c, .value = 2},
2712 {.input = &tegra_clk_m, .value = 3},
2713 { 0, 0},
2714};
2715
2716static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
2717 {.input = &tegra_pll_p, .value = 0},
2718 {.input = &tegra_pll_m, .value = 1},
2719 {.input = &tegra_pll_d_out0, .value = 2},
2720 {.input = &tegra_pll_a_out0, .value = 3},
2721 {.input = &tegra_pll_c, .value = 4},
2722 {.input = &tegra_pll_d2_out0, .value = 5},
2723 {.input = &tegra_clk_m, .value = 6},
2724 { 0, 0},
2725};
2726
2727static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
2728 { .input = &tegra_pll_a_out0, .value = 0},
2729 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
2730 { .input = &tegra_pll_p, .value = 2},
2731 { .input = &tegra_clk_m, .value = 3},
2732 { 0, 0},
2733};
2734
2735static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
2736 {.input = &tegra_pll_p, .value = 0},
2737 {.input = &tegra_pll_c, .value = 1},
2738 {.input = &tegra_clk_32k, .value = 2},
2739 {.input = &tegra_clk_m, .value = 3},
2740 { 0, 0},
2741};
2742
2743static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
2744 {.input = &tegra_pll_p, .value = 0},
2745 {.input = &tegra_pll_c, .value = 1},
2746 {.input = &tegra_clk_m, .value = 2},
2747 {.input = &tegra_clk_32k, .value = 3},
2748 { 0, 0},
2749};
2750
2751static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2752 {.input = &tegra_pll_p, .value = 0},
2753 {.input = &tegra_pll_c, .value = 1},
2754 {.input = &tegra_pll_m, .value = 2},
2755 { 0, 0},
2756};
2757
2758static struct clk_mux_sel mux_clk_m[] = {
2759 { .input = &tegra_clk_m, .value = 0},
2760 { 0, 0},
2761};
2762
2763static struct clk_mux_sel mux_pllp_out3[] = {
2764 { .input = &tegra_pll_p_out3, .value = 0},
2765 { 0, 0},
2766};
2767
2768static struct clk_mux_sel mux_plld_out0[] = {
2769 { .input = &tegra_pll_d_out0, .value = 0},
2770 { 0, 0},
2771};
2772
2773static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
2774 { .input = &tegra_pll_d_out0, .value = 0},
2775 { .input = &tegra_pll_d2_out0, .value = 1},
2776 { 0, 0},
2777};
2778
2779static struct clk_mux_sel mux_clk_32k[] = {
2780 { .input = &tegra_clk_32k, .value = 0},
2781 { 0, 0},
2782};
2783
2784static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
2785 { .input = &tegra_pll_a_out0, .value = 0},
2786 { .input = &tegra_clk_32k, .value = 1},
2787 { .input = &tegra_pll_p, .value = 2},
2788 { .input = &tegra_clk_m, .value = 3},
2789 { .input = &tegra_pll_e, .value = 4},
2790 { 0, 0},
2791};
2792
2793static struct clk_mux_sel mux_cclk_g[] = {
2794 { .input = &tegra_clk_m, .value = 0},
2795 { .input = &tegra_pll_c, .value = 1},
2796 { .input = &tegra_clk_32k, .value = 2},
2797 { .input = &tegra_pll_m, .value = 3},
2798 { .input = &tegra_pll_p, .value = 4},
2799 { .input = &tegra_pll_p_out4, .value = 5},
2800 { .input = &tegra_pll_p_out3, .value = 6},
2801 { .input = &tegra_pll_x, .value = 8},
2802 { 0, 0},
2803};
2804
2805static struct clk tegra_clk_cclk_g = {
2806 .name = "cclk_g",
2807 .flags = DIV_U71 | DIV_U71_INT,
2808 .inputs = mux_cclk_g,
2809 .reg = 0x368,
2810 .ops = &tegra_super_ops,
2811 .max_rate = 1700000000,
2812};
2813
2814static struct clk tegra30_clk_twd = {
2815 .parent = &tegra_clk_cclk_g,
2816 .name = "twd",
2817 .ops = &tegra30_twd_ops,
2818 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
2819 .mul = 1,
2820 .div = 2,
2821};
2822
2823#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2824 { \
2825 .name = _name, \
2826 .lookup = { \
2827 .dev_id = _dev, \
2828 .con_id = _con, \
2829 }, \
2830 .ops = &tegra_periph_clk_ops, \
2831 .reg = _reg, \
2832 .inputs = _inputs, \
2833 .flags = _flags, \
2834 .max_rate = _max, \
2835 .u.periph = { \
2836 .clk_num = _clk_num, \
2837 }, \
2838 }
2839
2840#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
2841 _flags, _ops) \
2842 { \
2843 .name = _name, \
2844 .lookup = { \
2845 .dev_id = _dev, \
2846 .con_id = _con, \
2847 }, \
2848 .ops = _ops, \
2849 .reg = _reg, \
2850 .inputs = _inputs, \
2851 .flags = _flags, \
2852 .max_rate = _max, \
2853 .u.periph = { \
2854 .clk_num = _clk_num, \
2855 }, \
2856 }
2857
2858#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
2859 { \
2860 .name = _name, \
2861 .lookup = { \
2862 .dev_id = _dev, \
2863 .con_id = _con, \
2864 }, \
2865 .ops = &tegra_clk_shared_bus_ops, \
2866 .parent = _parent, \
2867 .u.shared_bus_user = { \
2868 .client_id = _id, \
2869 .client_div = _div, \
2870 .mode = _mode, \
2871 }, \
2872 }
2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2878 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
2879 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2880 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2881 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
2882 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2883 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2884 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2885 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2893 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2894 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2895 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2896 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
2897 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2898 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2899 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2900 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2901 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2902 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2903 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2904 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2905 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
2906 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
2907 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2908 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2909 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2910 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2911 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2912 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2913 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2914 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2915 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2916 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2917 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2918 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2919 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2920 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2921 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
2922 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2923 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2933 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2934 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2935 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
2936 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
2937 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2938 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2939 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2940 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2941 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2942 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
2943 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
2944 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2945 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2946 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2947 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2948 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2949 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2950 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
2951 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
2952 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
2953 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2954 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2955
2956 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
2957 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
2958 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2959 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2960 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2961 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2962 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
2963 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
2964 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2965};
2966
2967#define CLK_DUPLICATE(_name, _dev, _con) \
2968 { \
2969 .name = _name, \
2970 .lookup = { \
2971 .dev_id = _dev, \
2972 .con_id = _con, \
2973 }, \
2974 }
2975
2976/* Some clocks may be used by different drivers depending on the board
2977 * configuration. List those here to register them twice in the clock lookup
2978 * table under two names.
2979 */
2980struct clk_duplicate tegra_clk_duplicates[] = {
2981 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2982 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2983 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2984 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2985 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2989 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2994 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2995 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2996 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
2997 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
2998 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
2999 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
3000 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
3001 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
3002 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
3003 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
3004 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
3005 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
3006 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
3007 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
3008 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
3009 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
3010 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
3011 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
3012 CLK_DUPLICATE("twd", "smp_twd", NULL),
3013 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
3014 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
3015 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
3016 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
3017 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
3018 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
3019 CLK_DUPLICATE("dam0", NULL, "dam0"),
3020 CLK_DUPLICATE("dam1", NULL, "dam1"),
3021 CLK_DUPLICATE("dam2", NULL, "dam2"),
3022 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
3023};
3024
3025struct clk *tegra_ptr_clks[] = {
3026 &tegra_clk_32k,
3027 &tegra_clk_m,
3028 &tegra_clk_m_div2,
3029 &tegra_clk_m_div4,
3030 &tegra_pll_ref,
3031 &tegra_pll_m,
3032 &tegra_pll_m_out1,
3033 &tegra_pll_c,
3034 &tegra_pll_c_out1,
3035 &tegra_pll_p,
3036 &tegra_pll_p_out1,
3037 &tegra_pll_p_out2,
3038 &tegra_pll_p_out3,
3039 &tegra_pll_p_out4,
3040 &tegra_pll_a,
3041 &tegra_pll_a_out0,
3042 &tegra_pll_d,
3043 &tegra_pll_d_out0,
3044 &tegra_pll_d2,
3045 &tegra_pll_d2_out0,
3046 &tegra_pll_u,
3047 &tegra_pll_x,
3048 &tegra_pll_x_out0,
3049 &tegra_pll_e,
3050 &tegra_clk_cclk_g,
3051 &tegra_cml0_clk,
3052 &tegra_cml1_clk,
3053 &tegra_pciex_clk,
3054 &tegra_clk_sclk,
3055 &tegra_clk_blink,
3056 &tegra30_clk_twd,
3057};
3058
3059
3060static void tegra30_init_one_clock(struct clk *c)
3061{ 2258{
3062 clk_init(c); 2259 writel(CPU_RESET(cpu),
3063 INIT_LIST_HEAD(&c->shared_bus_list); 2260 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
3064 if (!c->lookup.dev_id && !c->lookup.con_id) 2261 wmb();
3065 c->lookup.con_id = c->name;
3066 c->lookup.clk = c;
3067 clkdev_add(&c->lookup);
3068} 2262}
3069 2263
3070void __init tegra30_init_clocks(void) 2264static void tegra30_enable_cpu_clock(u32 cpu)
3071{ 2265{
3072 int i; 2266 unsigned int reg;
3073 struct clk *c;
3074 2267
3075 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) 2268 writel(CPU_CLOCK(cpu),
3076 tegra30_init_one_clock(tegra_ptr_clks[i]); 2269 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
3077 2270 reg = readl(reg_clk_base +
3078 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) 2271 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
3079 tegra30_init_one_clock(&tegra_list_clks[i]); 2272}
3080 2273
3081 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { 2274static void tegra30_disable_cpu_clock(u32 cpu)
3082 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); 2275{
3083 if (!c) {
3084 pr_err("%s: Unknown duplicate clock %s\n", __func__,
3085 tegra_clk_duplicates[i].name);
3086 continue;
3087 }
3088 2276
3089 tegra_clk_duplicates[i].lookup.clk = c; 2277 unsigned int reg;
3090 clkdev_add(&tegra_clk_duplicates[i].lookup);
3091 }
3092 2278
3093 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) 2279 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
3094 tegra30_init_one_clock(&tegra_sync_source_list[i]); 2280 writel(reg | CPU_CLOCK(cpu),
3095 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) 2281 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
3096 tegra30_init_one_clock(&tegra_clk_audio_list[i]); 2282}
3097 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
3098 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
3099 2283
3100 init_clk_out_mux(); 2284static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
3101 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) 2285 .wait_for_reset = tegra30_wait_cpu_in_reset,
3102 tegra30_init_one_clock(&tegra_clk_out_list[i]); 2286 .put_in_reset = tegra30_put_cpu_in_reset,
2287 .out_of_reset = tegra30_cpu_out_of_reset,
2288 .enable_clock = tegra30_enable_cpu_clock,
2289 .disable_clock = tegra30_disable_cpu_clock,
2290};
3103 2291
2292void __init tegra30_cpu_car_ops_init(void)
2293{
2294 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
3104} 2295}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 000000000000..f2f88fef6b8b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA30_CLOCK_H
18#define __MACH_TEGRA30_CLOCK_H
19
20extern struct clk_ops tegra30_clk_32k_ops;
21extern struct clk_ops tegra30_clk_m_ops;
22extern struct clk_ops tegra_clk_m_div_ops;
23extern struct clk_ops tegra_pll_ref_ops;
24extern struct clk_ops tegra30_pll_ops;
25extern struct clk_ops tegra30_pll_div_ops;
26extern struct clk_ops tegra_plld_ops;
27extern struct clk_ops tegra30_plle_ops;
28extern struct clk_ops tegra_cml_clk_ops;
29extern struct clk_ops tegra_pciex_clk_ops;
30extern struct clk_ops tegra_sync_source_ops;
31extern struct clk_ops tegra30_audio_sync_clk_ops;
32extern struct clk_ops tegra30_clk_double_ops;
33extern struct clk_ops tegra_clk_out_ops;
34extern struct clk_ops tegra30_super_ops;
35extern struct clk_ops tegra30_blink_clk_ops;
36extern struct clk_ops tegra30_twd_ops;
37extern struct clk_ops tegra30_periph_clk_ops;
38extern struct clk_ops tegra30_dsib_clk_ops;
39extern struct clk_ops tegra_nand_clk_ops;
40extern struct clk_ops tegra_vi_clk_ops;
41extern struct clk_ops tegra_dtv_clk_ops;
42extern struct clk_ops tegra_clk_shared_bus_ops;
43
44int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
45 enum tegra_clk_ex_param p, u32 setting);
46void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
47int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
48 enum tegra_clk_ex_param p, u32 setting);
49int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
50 enum tegra_clk_ex_param p, u32 setting);
51int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
52 enum tegra_clk_ex_param p, u32 setting);
53#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 000000000000..c10449603df0
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1372 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/cpufreq.h>
31
32#include "clock.h"
33#include "fuse.h"
34#include "tegra30_clocks.h"
35#include "tegra_cpu_car.h"
36
37#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
38 _parent_names, _parents, _parent) \
39 static struct clk tegra_##_name = { \
40 .hw = &tegra_##_name##_hw.hw, \
41 .name = #_name, \
42 .rate = _rate, \
43 .ops = _ops, \
44 .flags = _flags, \
45 .parent_names = _parent_names, \
46 .parents = _parents, \
47 .num_parents = ARRAY_SIZE(_parent_names), \
48 .parent = _parent, \
49 };
50
51static struct clk tegra_clk_32k;
52static struct clk_tegra tegra_clk_32k_hw = {
53 .hw = {
54 .clk = &tegra_clk_32k,
55 },
56 .fixed_rate = 32768,
57};
58static struct clk tegra_clk_32k = {
59 .name = "clk_32k",
60 .hw = &tegra_clk_32k_hw.hw,
61 .ops = &tegra30_clk_32k_ops,
62 .flags = CLK_IS_ROOT,
63};
64
65static struct clk tegra_clk_m;
66static struct clk_tegra tegra_clk_m_hw = {
67 .hw = {
68 .clk = &tegra_clk_m,
69 },
70 .flags = ENABLE_ON_INIT,
71 .reg = 0x1fc,
72 .reg_shift = 28,
73 .max_rate = 48000000,
74};
75static struct clk tegra_clk_m = {
76 .name = "clk_m",
77 .hw = &tegra_clk_m_hw.hw,
78 .ops = &tegra30_clk_m_ops,
79 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
80};
81
82static const char *clk_m_div_parent_names[] = {
83 "clk_m",
84};
85
86static struct clk *clk_m_div_parents[] = {
87 &tegra_clk_m,
88};
89
90static struct clk tegra_clk_m_div2;
91static struct clk_tegra tegra_clk_m_div2_hw = {
92 .hw = {
93 .clk = &tegra_clk_m_div2,
94 },
95 .mul = 1,
96 .div = 2,
97 .max_rate = 24000000,
98};
99DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
100 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
101
102static struct clk tegra_clk_m_div4;
103static struct clk_tegra tegra_clk_m_div4_hw = {
104 .hw = {
105 .clk = &tegra_clk_m_div4,
106 },
107 .mul = 1,
108 .div = 4,
109 .max_rate = 12000000,
110};
111DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
112 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
113
114static struct clk tegra_pll_ref;
115static struct clk_tegra tegra_pll_ref_hw = {
116 .hw = {
117 .clk = &tegra_pll_ref,
118 },
119 .flags = ENABLE_ON_INIT,
120 .max_rate = 26000000,
121};
122DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
123 clk_m_div_parents, &tegra_clk_m);
124
125#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
126 _input_max, _cf_min, _cf_max, _vco_min, \
127 _vco_max, _freq_table, _lock_delay, _ops, \
128 _fixed_rate, _clk_cfg_ex, _parent) \
129 static struct clk tegra_##_name; \
130 static const char *_name##_parent_names[] = { \
131 #_parent, \
132 }; \
133 static struct clk *_name##_parents[] = { \
134 &tegra_##_parent, \
135 }; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .u.pll = { \
144 .input_min = _input_min, \
145 .input_max = _input_max, \
146 .cf_min = _cf_min, \
147 .cf_max = _cf_max, \
148 .vco_min = _vco_min, \
149 .vco_max = _vco_max, \
150 .freq_table = _freq_table, \
151 .lock_delay = _lock_delay, \
152 .fixed_rate = _fixed_rate, \
153 }, \
154 .clk_cfg_ex = _clk_cfg_ex, \
155 }; \
156 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
157 _name##_parent_names, _name##_parents, \
158 &tegra_##_parent);
159
160#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
161 _max_rate, _ops, _parent, _clk_flags) \
162 static const char *_name##_parent_names[] = { \
163 #_parent, \
164 }; \
165 static struct clk *_name##_parents[] = { \
166 &tegra_##_parent, \
167 }; \
168 static struct clk tegra_##_name; \
169 static struct clk_tegra tegra_##_name##_hw = { \
170 .hw = { \
171 .clk = &tegra_##_name, \
172 }, \
173 .flags = _flags, \
174 .reg = _reg, \
175 .max_rate = _max_rate, \
176 .reg_shift = _reg_shift, \
177 }; \
178 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
179 _clk_flags, _name##_parent_names, \
180 _name##_parents, &tegra_##_parent);
181
182static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
183 { 12000000, 1040000000, 520, 6, 1, 8},
184 { 13000000, 1040000000, 480, 6, 1, 8},
185 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
186 { 19200000, 1040000000, 325, 6, 1, 6},
187 { 26000000, 1040000000, 520, 13, 1, 8},
188
189 { 12000000, 832000000, 416, 6, 1, 8},
190 { 13000000, 832000000, 832, 13, 1, 8},
191 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
192 { 19200000, 832000000, 260, 6, 1, 8},
193 { 26000000, 832000000, 416, 13, 1, 8},
194
195 { 12000000, 624000000, 624, 12, 1, 8},
196 { 13000000, 624000000, 624, 13, 1, 8},
197 { 16800000, 600000000, 520, 14, 1, 8},
198 { 19200000, 624000000, 520, 16, 1, 8},
199 { 26000000, 624000000, 624, 26, 1, 8},
200
201 { 12000000, 600000000, 600, 12, 1, 8},
202 { 13000000, 600000000, 600, 13, 1, 8},
203 { 16800000, 600000000, 500, 14, 1, 8},
204 { 19200000, 600000000, 375, 12, 1, 6},
205 { 26000000, 600000000, 600, 26, 1, 8},
206
207 { 12000000, 520000000, 520, 12, 1, 8},
208 { 13000000, 520000000, 520, 13, 1, 8},
209 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
210 { 19200000, 520000000, 325, 12, 1, 6},
211 { 26000000, 520000000, 520, 26, 1, 8},
212
213 { 12000000, 416000000, 416, 12, 1, 8},
214 { 13000000, 416000000, 416, 13, 1, 8},
215 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
216 { 19200000, 416000000, 260, 12, 1, 6},
217 { 26000000, 416000000, 416, 26, 1, 8},
218 { 0, 0, 0, 0, 0, 0 },
219};
220
221DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
222 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
223 tegra30_pll_ops, 0, NULL, pll_ref);
224
225DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
226 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
227
228static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
229 { 12000000, 666000000, 666, 12, 1, 8},
230 { 13000000, 666000000, 666, 13, 1, 8},
231 { 16800000, 666000000, 555, 14, 1, 8},
232 { 19200000, 666000000, 555, 16, 1, 8},
233 { 26000000, 666000000, 666, 26, 1, 8},
234 { 12000000, 600000000, 600, 12, 1, 8},
235 { 13000000, 600000000, 600, 13, 1, 8},
236 { 16800000, 600000000, 500, 14, 1, 8},
237 { 19200000, 600000000, 375, 12, 1, 6},
238 { 26000000, 600000000, 600, 26, 1, 8},
239 { 0, 0, 0, 0, 0, 0 },
240};
241
242DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
243 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
244 300, tegra30_pll_ops, 0, NULL, pll_ref);
245
246DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
247 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
248
249static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
250 { 12000000, 216000000, 432, 12, 2, 8},
251 { 13000000, 216000000, 432, 13, 2, 8},
252 { 16800000, 216000000, 360, 14, 2, 8},
253 { 19200000, 216000000, 360, 16, 2, 8},
254 { 26000000, 216000000, 432, 26, 2, 8},
255 { 0, 0, 0, 0, 0, 0 },
256};
257
258DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
259 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
260 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
261 pll_ref);
262
263DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
264 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
265DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
266 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
267DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
268 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
269DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
270 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
271
272static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
273 { 9600000, 564480000, 294, 5, 1, 4},
274 { 9600000, 552960000, 288, 5, 1, 4},
275 { 9600000, 24000000, 5, 2, 1, 1},
276
277 { 28800000, 56448000, 49, 25, 1, 1},
278 { 28800000, 73728000, 64, 25, 1, 1},
279 { 28800000, 24000000, 5, 6, 1, 1},
280 { 0, 0, 0, 0, 0, 0 },
281};
282
283DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
284 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
285 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
286
287DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
288 pll_a, CLK_IGNORE_UNUSED);
289
290static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
291 { 12000000, 216000000, 216, 12, 1, 4},
292 { 13000000, 216000000, 216, 13, 1, 4},
293 { 16800000, 216000000, 180, 14, 1, 4},
294 { 19200000, 216000000, 180, 16, 1, 4},
295 { 26000000, 216000000, 216, 26, 1, 4},
296
297 { 12000000, 594000000, 594, 12, 1, 8},
298 { 13000000, 594000000, 594, 13, 1, 8},
299 { 16800000, 594000000, 495, 14, 1, 8},
300 { 19200000, 594000000, 495, 16, 1, 8},
301 { 26000000, 594000000, 594, 26, 1, 8},
302
303 { 12000000, 1000000000, 1000, 12, 1, 12},
304 { 13000000, 1000000000, 1000, 13, 1, 12},
305 { 19200000, 1000000000, 625, 12, 1, 8},
306 { 26000000, 1000000000, 1000, 26, 1, 12},
307
308 { 0, 0, 0, 0, 0, 0 },
309};
310
311DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
312 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
313 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
314
315DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
316 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
317
318DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
319 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
320 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
321 pll_ref);
322
323DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
324 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
325
326static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
327 { 12000000, 480000000, 960, 12, 2, 12},
328 { 13000000, 480000000, 960, 13, 2, 12},
329 { 16800000, 480000000, 400, 7, 2, 5},
330 { 19200000, 480000000, 200, 4, 2, 3},
331 { 26000000, 480000000, 960, 26, 2, 12},
332 { 0, 0, 0, 0, 0, 0 },
333};
334
335DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
336 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
337 1000, tegra30_pll_ops, 0, NULL, pll_ref);
338
339static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
340 /* 1.7 GHz */
341 { 12000000, 1700000000, 850, 6, 1, 8},
342 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
343 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
344 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
345 { 26000000, 1700000000, 850, 13, 1, 8},
346
347 /* 1.6 GHz */
348 { 12000000, 1600000000, 800, 6, 1, 8},
349 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
350 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
351 { 19200000, 1600000000, 500, 6, 1, 8},
352 { 26000000, 1600000000, 800, 13, 1, 8},
353
354 /* 1.5 GHz */
355 { 12000000, 1500000000, 750, 6, 1, 8},
356 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
357 { 16800000, 1500000000, 625, 7, 1, 8},
358 { 19200000, 1500000000, 625, 8, 1, 8},
359 { 26000000, 1500000000, 750, 13, 1, 8},
360
361 /* 1.4 GHz */
362 { 12000000, 1400000000, 700, 6, 1, 8},
363 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
364 { 16800000, 1400000000, 1000, 12, 1, 8},
365 { 19200000, 1400000000, 875, 12, 1, 8},
366 { 26000000, 1400000000, 700, 13, 1, 8},
367
368 /* 1.3 GHz */
369 { 12000000, 1300000000, 975, 9, 1, 8},
370 { 13000000, 1300000000, 1000, 10, 1, 8},
371 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
372 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
373 { 26000000, 1300000000, 650, 13, 1, 8},
374
375 /* 1.2 GHz */
376 { 12000000, 1200000000, 1000, 10, 1, 8},
377 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
378 { 16800000, 1200000000, 1000, 14, 1, 8},
379 { 19200000, 1200000000, 1000, 16, 1, 8},
380 { 26000000, 1200000000, 600, 13, 1, 8},
381
382 /* 1.1 GHz */
383 { 12000000, 1100000000, 825, 9, 1, 8},
384 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
385 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
386 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
387 { 26000000, 1100000000, 550, 13, 1, 8},
388
389 /* 1 GHz */
390 { 12000000, 1000000000, 1000, 12, 1, 8},
391 { 13000000, 1000000000, 1000, 13, 1, 8},
392 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
393 { 19200000, 1000000000, 625, 12, 1, 8},
394 { 26000000, 1000000000, 1000, 26, 1, 8},
395
396 { 0, 0, 0, 0, 0, 0 },
397};
398
399DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
400 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
401 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
402
403DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
404 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
405
406static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
407 /* PLLE special case: use cpcon field to store cml divider value */
408 { 12000000, 100000000, 150, 1, 18, 11},
409 { 216000000, 100000000, 200, 18, 24, 13},
410 { 0, 0, 0, 0, 0, 0 },
411};
412
413DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
414 12000000, 12000000, 1200000000, 2400000000U,
415 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
416 pll_ref);
417
418static const char *mux_plle[] = {
419 "pll_e",
420};
421
422static struct clk *mux_plle_p[] = {
423 &tegra_pll_e,
424};
425
426static struct clk tegra_cml0;
427static struct clk_tegra tegra_cml0_hw = {
428 .hw = {
429 .clk = &tegra_cml0,
430 },
431 .reg = 0x48c,
432 .fixed_rate = 100000000,
433 .u.periph = {
434 .clk_num = 0,
435 },
436};
437DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
438 mux_plle_p, &tegra_pll_e);
439
440static struct clk tegra_cml1;
441static struct clk_tegra tegra_cml1_hw = {
442 .hw = {
443 .clk = &tegra_cml1,
444 },
445 .reg = 0x48c,
446 .fixed_rate = 100000000,
447 .u.periph = {
448 .clk_num = 1,
449 },
450};
451DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
452 mux_plle_p, &tegra_pll_e);
453
454static struct clk tegra_pciex;
455static struct clk_tegra tegra_pciex_hw = {
456 .hw = {
457 .clk = &tegra_pciex,
458 },
459 .reg = 0x48c,
460 .fixed_rate = 100000000,
461 .reset = tegra30_periph_clk_reset,
462 .u.periph = {
463 .clk_num = 74,
464 },
465};
466DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
467 mux_plle_p, &tegra_pll_e);
468
469#define SYNC_SOURCE(_name) \
470 static struct clk tegra_##_name##_sync; \
471 static struct clk_tegra tegra_##_name##_sync_hw = { \
472 .hw = { \
473 .clk = &tegra_##_name##_sync, \
474 }, \
475 .max_rate = 24000000, \
476 .fixed_rate = 24000000, \
477 }; \
478 static struct clk tegra_##_name##_sync = { \
479 .name = #_name "_sync", \
480 .hw = &tegra_##_name##_sync_hw.hw, \
481 .ops = &tegra_sync_source_ops, \
482 .flags = CLK_IS_ROOT, \
483 };
484
485SYNC_SOURCE(spdif_in);
486SYNC_SOURCE(i2s0);
487SYNC_SOURCE(i2s1);
488SYNC_SOURCE(i2s2);
489SYNC_SOURCE(i2s3);
490SYNC_SOURCE(i2s4);
491SYNC_SOURCE(vimclk);
492
493static struct clk *tegra_sync_source_list[] = {
494 &tegra_spdif_in_sync,
495 &tegra_i2s0_sync,
496 &tegra_i2s1_sync,
497 &tegra_i2s2_sync,
498 &tegra_i2s3_sync,
499 &tegra_i2s4_sync,
500 &tegra_vimclk_sync,
501};
502
503static const char *mux_audio_sync_clk[] = {
504 "spdif_in_sync",
505 "i2s0_sync",
506 "i2s1_sync",
507 "i2s2_sync",
508 "i2s3_sync",
509 "i2s4_sync",
510 "vimclk_sync",
511};
512
513#define AUDIO_SYNC_CLK(_name, _index) \
514 static struct clk tegra_##_name; \
515 static struct clk_tegra tegra_##_name##_hw = { \
516 .hw = { \
517 .clk = &tegra_##_name, \
518 }, \
519 .max_rate = 24000000, \
520 .reg = 0x4A0 + (_index) * 4, \
521 }; \
522 static struct clk tegra_##_name = { \
523 .name = #_name, \
524 .ops = &tegra30_audio_sync_clk_ops, \
525 .hw = &tegra_##_name##_hw.hw, \
526 .parent_names = mux_audio_sync_clk, \
527 .parents = tegra_sync_source_list, \
528 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
529 };
530
531AUDIO_SYNC_CLK(audio0, 0);
532AUDIO_SYNC_CLK(audio1, 1);
533AUDIO_SYNC_CLK(audio2, 2);
534AUDIO_SYNC_CLK(audio3, 3);
535AUDIO_SYNC_CLK(audio4, 4);
536AUDIO_SYNC_CLK(audio5, 5);
537
538static struct clk *tegra_clk_audio_list[] = {
539 &tegra_audio0,
540 &tegra_audio1,
541 &tegra_audio2,
542 &tegra_audio3,
543 &tegra_audio4,
544 &tegra_audio5, /* SPDIF */
545};
546
547#define AUDIO_SYNC_2X_CLK(_name, _index) \
548 static const char *_name##_parent_names[] = { \
549 "tegra_" #_name, \
550 }; \
551 static struct clk *_name##_parents[] = { \
552 &tegra_##_name, \
553 }; \
554 static struct clk tegra_##_name##_2x; \
555 static struct clk_tegra tegra_##_name##_2x_hw = { \
556 .hw = { \
557 .clk = &tegra_##_name##_2x, \
558 }, \
559 .flags = PERIPH_NO_RESET, \
560 .max_rate = 48000000, \
561 .reg = 0x49C, \
562 .reg_shift = 24 + (_index), \
563 .u.periph = { \
564 .clk_num = 113 + (_index), \
565 }, \
566 }; \
567 static struct clk tegra_##_name##_2x = { \
568 .name = #_name "_2x", \
569 .ops = &tegra30_clk_double_ops, \
570 .hw = &tegra_##_name##_2x_hw.hw, \
571 .parent_names = _name##_parent_names, \
572 .parents = _name##_parents, \
573 .parent = &tegra_##_name, \
574 .num_parents = 1, \
575 };
576
577AUDIO_SYNC_2X_CLK(audio0, 0);
578AUDIO_SYNC_2X_CLK(audio1, 1);
579AUDIO_SYNC_2X_CLK(audio2, 2);
580AUDIO_SYNC_2X_CLK(audio3, 3);
581AUDIO_SYNC_2X_CLK(audio4, 4);
582AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
583
584static struct clk *tegra_clk_audio_2x_list[] = {
585 &tegra_audio0_2x,
586 &tegra_audio1_2x,
587 &tegra_audio2_2x,
588 &tegra_audio3_2x,
589 &tegra_audio4_2x,
590 &tegra_audio5_2x, /* SPDIF */
591};
592
593#define MUX_I2S_SPDIF(_id) \
594static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
595 "pll_a_out0", \
596 #_id "_2x", \
597 "pll_p", \
598 "clk_m", \
599}; \
600static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
601 &tegra_pll_a_out0, \
602 &tegra_##_id##_2x, \
603 &tegra_pll_p, \
604 &tegra_clk_m, \
605};
606
607MUX_I2S_SPDIF(audio0);
608MUX_I2S_SPDIF(audio1);
609MUX_I2S_SPDIF(audio2);
610MUX_I2S_SPDIF(audio3);
611MUX_I2S_SPDIF(audio4);
612MUX_I2S_SPDIF(audio5); /* SPDIF */
613
614static struct clk tegra_extern1;
615static struct clk tegra_extern2;
616static struct clk tegra_extern3;
617
618/* External clock outputs (through PMC) */
619#define MUX_EXTERN_OUT(_id) \
620static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
621 "clk_m", \
622 "clk_m_div2", \
623 "clk_m_div4", \
624 "extern" #_id, \
625}; \
626static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
627 &tegra_clk_m, \
628 &tegra_clk_m_div2, \
629 &tegra_clk_m_div4, \
630 &tegra_extern##_id, \
631};
632
633MUX_EXTERN_OUT(1);
634MUX_EXTERN_OUT(2);
635MUX_EXTERN_OUT(3);
636
637#define CLK_OUT_CLK(_name, _index) \
638 static struct clk tegra_##_name; \
639 static struct clk_tegra tegra_##_name##_hw = { \
640 .hw = { \
641 .clk = &tegra_##_name, \
642 }, \
643 .lookup = { \
644 .dev_id = #_name, \
645 .con_id = "extern" #_index, \
646 }, \
647 .flags = MUX_CLK_OUT, \
648 .fixed_rate = 216000000, \
649 .reg = 0x1a8, \
650 .u.periph = { \
651 .clk_num = (_index - 1) * 8 + 2, \
652 }, \
653 }; \
654 static struct clk tegra_##_name = { \
655 .name = #_name, \
656 .ops = &tegra_clk_out_ops, \
657 .hw = &tegra_##_name##_hw.hw, \
658 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
659 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
660 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
661 };
662
663CLK_OUT_CLK(clk_out_1, 1);
664CLK_OUT_CLK(clk_out_2, 2);
665CLK_OUT_CLK(clk_out_3, 3);
666
667static struct clk *tegra_clk_out_list[] = {
668 &tegra_clk_out_1,
669 &tegra_clk_out_2,
670 &tegra_clk_out_3,
671};
672
673static const char *mux_sclk[] = {
674 "clk_m",
675 "pll_c_out1",
676 "pll_p_out4",
677 "pll_p_out3",
678 "pll_p_out2",
679 "dummy",
680 "clk_32k",
681 "pll_m_out1",
682};
683
684static struct clk *mux_sclk_p[] = {
685 &tegra_clk_m,
686 &tegra_pll_c_out1,
687 &tegra_pll_p_out4,
688 &tegra_pll_p_out3,
689 &tegra_pll_p_out2,
690 NULL,
691 &tegra_clk_32k,
692 &tegra_pll_m_out1,
693};
694
695static struct clk tegra_clk_sclk;
696static struct clk_tegra tegra_clk_sclk_hw = {
697 .hw = {
698 .clk = &tegra_clk_sclk,
699 },
700 .reg = 0x28,
701 .max_rate = 334000000,
702 .min_rate = 40000000,
703};
704
705static struct clk tegra_clk_sclk = {
706 .name = "sclk",
707 .ops = &tegra30_super_ops,
708 .hw = &tegra_clk_sclk_hw.hw,
709 .parent_names = mux_sclk,
710 .parents = mux_sclk_p,
711 .num_parents = ARRAY_SIZE(mux_sclk),
712};
713
714static const char *mux_blink[] = {
715 "clk_32k",
716};
717
718static struct clk *mux_blink_p[] = {
719 &tegra_clk_32k,
720};
721
722static struct clk tegra_clk_blink;
723static struct clk_tegra tegra_clk_blink_hw = {
724 .hw = {
725 .clk = &tegra_clk_blink,
726 },
727 .reg = 0x40,
728 .max_rate = 32768,
729};
730static struct clk tegra_clk_blink = {
731 .name = "blink",
732 .ops = &tegra30_blink_clk_ops,
733 .hw = &tegra_clk_blink_hw.hw,
734 .parent = &tegra_clk_32k,
735 .parent_names = mux_blink,
736 .parents = mux_blink_p,
737 .num_parents = ARRAY_SIZE(mux_blink),
738};
739
740static const char *mux_pllm_pllc_pllp_plla[] = {
741 "pll_m",
742 "pll_c",
743 "pll_p",
744 "pll_a_out0",
745};
746
747static const char *mux_pllp_pllc_pllm_clkm[] = {
748 "pll_p",
749 "pll_c",
750 "pll_m",
751 "clk_m",
752};
753
754static const char *mux_pllp_clkm[] = {
755 "pll_p",
756 "dummy",
757 "dummy",
758 "clk_m",
759};
760
761static const char *mux_pllp_plld_pllc_clkm[] = {
762 "pll_p",
763 "pll_d_out0",
764 "pll_c",
765 "clk_m",
766};
767
768static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
769 "pll_p",
770 "pll_m",
771 "pll_d_out0",
772 "pll_a_out0",
773 "pll_c",
774 "pll_d2_out0",
775 "clk_m",
776};
777
778static const char *mux_plla_pllc_pllp_clkm[] = {
779 "pll_a_out0",
780 "dummy",
781 "pll_p",
782 "clk_m"
783};
784
785static const char *mux_pllp_pllc_clk32_clkm[] = {
786 "pll_p",
787 "pll_c",
788 "clk_32k",
789 "clk_m",
790};
791
792static const char *mux_pllp_pllc_clkm_clk32[] = {
793 "pll_p",
794 "pll_c",
795 "clk_m",
796 "clk_32k",
797};
798
799static const char *mux_pllp_pllc_pllm[] = {
800 "pll_p",
801 "pll_c",
802 "pll_m",
803};
804
805static const char *mux_clk_m[] = {
806 "clk_m",
807};
808
809static const char *mux_pllp_out3[] = {
810 "pll_p_out3",
811};
812
813static const char *mux_plld_out0[] = {
814 "pll_d_out0",
815};
816
817static const char *mux_plld_out0_plld2_out0[] = {
818 "pll_d_out0",
819 "pll_d2_out0",
820};
821
822static const char *mux_clk_32k[] = {
823 "clk_32k",
824};
825
826static const char *mux_plla_clk32_pllp_clkm_plle[] = {
827 "pll_a_out0",
828 "clk_32k",
829 "pll_p",
830 "clk_m",
831 "pll_e",
832};
833
834static const char *mux_cclk_g[] = {
835 "clk_m",
836 "pll_c",
837 "clk_32k",
838 "pll_m",
839 "pll_p",
840 "pll_p_out4",
841 "pll_p_out3",
842 "dummy",
843 "pll_x",
844};
845
846static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
847 &tegra_pll_m,
848 &tegra_pll_c,
849 &tegra_pll_p,
850 &tegra_pll_a_out0,
851};
852
853static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
854 &tegra_pll_p,
855 &tegra_pll_c,
856 &tegra_pll_m,
857 &tegra_clk_m,
858};
859
860static struct clk *mux_pllp_clkm_p[] = {
861 &tegra_pll_p,
862 NULL,
863 NULL,
864 &tegra_clk_m,
865};
866
867static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
868 &tegra_pll_p,
869 &tegra_pll_d_out0,
870 &tegra_pll_c,
871 &tegra_clk_m,
872};
873
874static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
875 &tegra_pll_p,
876 &tegra_pll_m,
877 &tegra_pll_d_out0,
878 &tegra_pll_a_out0,
879 &tegra_pll_c,
880 &tegra_pll_d2_out0,
881 &tegra_clk_m,
882};
883
884static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
885 &tegra_pll_a_out0,
886 NULL,
887 &tegra_pll_p,
888 &tegra_clk_m,
889};
890
891static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
892 &tegra_pll_p,
893 &tegra_pll_c,
894 &tegra_clk_32k,
895 &tegra_clk_m,
896};
897
898static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
899 &tegra_pll_p,
900 &tegra_pll_c,
901 &tegra_clk_m,
902 &tegra_clk_32k,
903};
904
905static struct clk *mux_pllp_pllc_pllm_p[] = {
906 &tegra_pll_p,
907 &tegra_pll_c,
908 &tegra_pll_m,
909};
910
911static struct clk *mux_clk_m_p[] = {
912 &tegra_clk_m,
913};
914
915static struct clk *mux_pllp_out3_p[] = {
916 &tegra_pll_p_out3,
917};
918
919static struct clk *mux_plld_out0_p[] = {
920 &tegra_pll_d_out0,
921};
922
923static struct clk *mux_plld_out0_plld2_out0_p[] = {
924 &tegra_pll_d_out0,
925 &tegra_pll_d2_out0,
926};
927
928static struct clk *mux_clk_32k_p[] = {
929 &tegra_clk_32k,
930};
931
932static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
933 &tegra_pll_a_out0,
934 &tegra_clk_32k,
935 &tegra_pll_p,
936 &tegra_clk_m,
937 &tegra_pll_e,
938};
939
940static struct clk *mux_cclk_g_p[] = {
941 &tegra_clk_m,
942 &tegra_pll_c,
943 &tegra_clk_32k,
944 &tegra_pll_m,
945 &tegra_pll_p,
946 &tegra_pll_p_out4,
947 &tegra_pll_p_out3,
948 NULL,
949 &tegra_pll_x,
950};
951
952static struct clk tegra_clk_cclk_g;
953static struct clk_tegra tegra_clk_cclk_g_hw = {
954 .hw = {
955 .clk = &tegra_clk_cclk_g,
956 },
957 .flags = DIV_U71 | DIV_U71_INT,
958 .reg = 0x368,
959 .max_rate = 1700000000,
960};
961static struct clk tegra_clk_cclk_g = {
962 .name = "cclk_g",
963 .ops = &tegra30_super_ops,
964 .hw = &tegra_clk_cclk_g_hw.hw,
965 .parent_names = mux_cclk_g,
966 .parents = mux_cclk_g_p,
967 .num_parents = ARRAY_SIZE(mux_cclk_g),
968};
969
970static const char *mux_twd[] = {
971 "cclk_g",
972};
973
974static struct clk *mux_twd_p[] = {
975 &tegra_clk_cclk_g,
976};
977
978static struct clk tegra30_clk_twd;
979static struct clk_tegra tegra30_clk_twd_hw = {
980 .hw = {
981 .clk = &tegra30_clk_twd,
982 },
983 .max_rate = 1400000000,
984 .mul = 1,
985 .div = 2,
986};
987
988static struct clk tegra30_clk_twd = {
989 .name = "twd",
990 .ops = &tegra30_twd_ops,
991 .hw = &tegra30_clk_twd_hw.hw,
992 .parent = &tegra_clk_cclk_g,
993 .parent_names = mux_twd,
994 .parents = mux_twd_p,
995 .num_parents = ARRAY_SIZE(mux_twd),
996};
997
998#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
999 _max, _inputs, _flags) \
1000 static struct clk tegra_##_name; \
1001 static struct clk_tegra tegra_##_name##_hw = { \
1002 .hw = { \
1003 .clk = &tegra_##_name, \
1004 }, \
1005 .lookup = { \
1006 .dev_id = _dev, \
1007 .con_id = _con, \
1008 }, \
1009 .reg = _reg, \
1010 .flags = _flags, \
1011 .max_rate = _max, \
1012 .u.periph = { \
1013 .clk_num = _clk_num, \
1014 }, \
1015 .reset = &tegra30_periph_clk_reset, \
1016 }; \
1017 static struct clk tegra_##_name = { \
1018 .name = #_name, \
1019 .ops = &tegra30_periph_clk_ops, \
1020 .hw = &tegra_##_name##_hw.hw, \
1021 .parent_names = _inputs, \
1022 .parents = _inputs##_p, \
1023 .num_parents = ARRAY_SIZE(_inputs), \
1024 };
1025
1026PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1027PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1028PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1029PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1030PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1031PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1032PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1033PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1034PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1035PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1036PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1037PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1038PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1039PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1040PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1041PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1042PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1043PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1044PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1045PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1046PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1047PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1048PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1049PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1050PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1051PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1052PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1053PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1054PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1055PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1056PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1057PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1058PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1059PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1060PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1061PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1062PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1063PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1064PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1065PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1066PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1067PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1068PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1069PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1070PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1071PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1072PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1073PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1074PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1075PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1076PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1077PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1078PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1079PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1080PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1081PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1082PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1083PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1084PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1085PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1086PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1087PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1088PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1089PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1090PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1091PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1092PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1093PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1094PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1095PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1096PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1097PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1098PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1099PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1100PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1101PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1102PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1103PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1104PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1105PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1106PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1107PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1108PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1109PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1110PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1111PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1112PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1113PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1114PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1115
1116static struct clk tegra_dsib;
1117static struct clk_tegra tegra_dsib_hw = {
1118 .hw = {
1119 .clk = &tegra_dsib,
1120 },
1121 .lookup = {
1122 .dev_id = "tegradc.1",
1123 .con_id = "dsib",
1124 },
1125 .reg = 0xd0,
1126 .flags = MUX | PLLD,
1127 .max_rate = 500000000,
1128 .u.periph = {
1129 .clk_num = 82,
1130 },
1131 .reset = &tegra30_periph_clk_reset,
1132};
1133static struct clk tegra_dsib = {
1134 .name = "dsib",
1135 .ops = &tegra30_dsib_clk_ops,
1136 .hw = &tegra_dsib_hw.hw,
1137 .parent_names = mux_plld_out0_plld2_out0,
1138 .parents = mux_plld_out0_plld2_out0_p,
1139 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1140};
1141
1142struct clk *tegra_list_clks[] = {
1143 &tegra_apbdma,
1144 &tegra_rtc,
1145 &tegra_kbc,
1146 &tegra_kfuse,
1147 &tegra_fuse,
1148 &tegra_fuse_burn,
1149 &tegra_apbif,
1150 &tegra_i2s0,
1151 &tegra_i2s1,
1152 &tegra_i2s2,
1153 &tegra_i2s3,
1154 &tegra_i2s4,
1155 &tegra_spdif_out,
1156 &tegra_spdif_in,
1157 &tegra_pwm,
1158 &tegra_d_audio,
1159 &tegra_dam0,
1160 &tegra_dam1,
1161 &tegra_dam2,
1162 &tegra_hda,
1163 &tegra_hda2codec_2x,
1164 &tegra_hda2hdmi,
1165 &tegra_sbc1,
1166 &tegra_sbc2,
1167 &tegra_sbc3,
1168 &tegra_sbc4,
1169 &tegra_sbc5,
1170 &tegra_sbc6,
1171 &tegra_sata_oob,
1172 &tegra_sata,
1173 &tegra_sata_cold,
1174 &tegra_ndflash,
1175 &tegra_ndspeed,
1176 &tegra_vfir,
1177 &tegra_sdmmc1,
1178 &tegra_sdmmc2,
1179 &tegra_sdmmc3,
1180 &tegra_sdmmc4,
1181 &tegra_vcp,
1182 &tegra_bsea,
1183 &tegra_bsev,
1184 &tegra_vde,
1185 &tegra_csite,
1186 &tegra_la,
1187 &tegra_owr,
1188 &tegra_nor,
1189 &tegra_mipi,
1190 &tegra_i2c1,
1191 &tegra_i2c2,
1192 &tegra_i2c3,
1193 &tegra_i2c4,
1194 &tegra_i2c5,
1195 &tegra_uarta,
1196 &tegra_uartb,
1197 &tegra_uartc,
1198 &tegra_uartd,
1199 &tegra_uarte,
1200 &tegra_vi,
1201 &tegra_3d,
1202 &tegra_3d2,
1203 &tegra_2d,
1204 &tegra_vi_sensor,
1205 &tegra_epp,
1206 &tegra_mpe,
1207 &tegra_host1x,
1208 &tegra_cve,
1209 &tegra_tvo,
1210 &tegra_dtv,
1211 &tegra_hdmi,
1212 &tegra_tvdac,
1213 &tegra_disp1,
1214 &tegra_disp2,
1215 &tegra_usbd,
1216 &tegra_usb2,
1217 &tegra_usb3,
1218 &tegra_dsia,
1219 &tegra_dsib,
1220 &tegra_csi,
1221 &tegra_isp,
1222 &tegra_csus,
1223 &tegra_tsensor,
1224 &tegra_actmon,
1225 &tegra_extern1,
1226 &tegra_extern2,
1227 &tegra_extern3,
1228 &tegra_i2cslow,
1229 &tegra_pcie,
1230 &tegra_afi,
1231 &tegra_se,
1232};
1233
1234#define CLK_DUPLICATE(_name, _dev, _con) \
1235 { \
1236 .name = _name, \
1237 .lookup = { \
1238 .dev_id = _dev, \
1239 .con_id = _con, \
1240 }, \
1241 }
1242
1243/* Some clocks may be used by different drivers depending on the board
1244 * configuration. List those here to register them twice in the clock lookup
1245 * table under two names.
1246 */
1247struct clk_duplicate tegra_clk_duplicates[] = {
1248 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1249 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1250 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1251 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1252 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1253 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1254 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1255 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1256 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1257 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1258 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1259 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1260 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1261 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1262 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1263 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1264 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1265 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1266 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1267 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1268 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1269 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1270 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1271 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1272 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1273 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1274 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1275 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1276 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1277 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1278 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1279 CLK_DUPLICATE("twd", "smp_twd", NULL),
1280 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1281 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1282 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1283 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1284 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1285 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1286 CLK_DUPLICATE("dam0", NULL, "dam0"),
1287 CLK_DUPLICATE("dam1", NULL, "dam1"),
1288 CLK_DUPLICATE("dam2", NULL, "dam2"),
1289 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1290};
1291
1292struct clk *tegra_ptr_clks[] = {
1293 &tegra_clk_32k,
1294 &tegra_clk_m,
1295 &tegra_clk_m_div2,
1296 &tegra_clk_m_div4,
1297 &tegra_pll_ref,
1298 &tegra_pll_m,
1299 &tegra_pll_m_out1,
1300 &tegra_pll_c,
1301 &tegra_pll_c_out1,
1302 &tegra_pll_p,
1303 &tegra_pll_p_out1,
1304 &tegra_pll_p_out2,
1305 &tegra_pll_p_out3,
1306 &tegra_pll_p_out4,
1307 &tegra_pll_a,
1308 &tegra_pll_a_out0,
1309 &tegra_pll_d,
1310 &tegra_pll_d_out0,
1311 &tegra_pll_d2,
1312 &tegra_pll_d2_out0,
1313 &tegra_pll_u,
1314 &tegra_pll_x,
1315 &tegra_pll_x_out0,
1316 &tegra_pll_e,
1317 &tegra_clk_cclk_g,
1318 &tegra_cml0,
1319 &tegra_cml1,
1320 &tegra_pciex,
1321 &tegra_clk_sclk,
1322 &tegra_clk_blink,
1323 &tegra30_clk_twd,
1324};
1325
1326static void tegra30_init_one_clock(struct clk *c)
1327{
1328 struct clk_tegra *clk = to_clk_tegra(c->hw);
1329 __clk_init(NULL, c);
1330 INIT_LIST_HEAD(&clk->shared_bus_list);
1331 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1332 clk->lookup.con_id = c->name;
1333 clk->lookup.clk = c;
1334 clkdev_add(&clk->lookup);
1335 tegra_clk_add(c);
1336}
1337
1338void __init tegra30_init_clocks(void)
1339{
1340 int i;
1341 struct clk *c;
1342
1343 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1344 tegra30_init_one_clock(tegra_ptr_clks[i]);
1345
1346 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1347 tegra30_init_one_clock(tegra_list_clks[i]);
1348
1349 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1350 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1351 if (!c) {
1352 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1353 tegra_clk_duplicates[i].name);
1354 continue;
1355 }
1356
1357 tegra_clk_duplicates[i].lookup.clk = c;
1358 clkdev_add(&tegra_clk_duplicates[i].lookup);
1359 }
1360
1361 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1362 tegra30_init_one_clock(tegra_sync_source_list[i]);
1363 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1364 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1365 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1366 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1367
1368 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1369 tegra30_init_one_clock(tegra_clk_out_list[i]);
1370
1371 tegra30_cpu_car_ops_init();
1372}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 000000000000..30d063ad2bef
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA_CPU_CAR_H
18#define __MACH_TEGRA_CPU_CAR_H
19
20/*
21 * Tegra CPU clock and reset control ops
22 *
23 * wait_for_reset:
24 * keep waiting until the CPU in reset state
25 * put_in_reset:
26 * put the CPU in reset state
27 * out_of_reset:
28 * release the CPU from reset state
29 * enable_clock:
30 * CPU clock un-gate
31 * disable_clock:
32 * CPU clock gate
33 */
34struct tegra_cpu_car_ops {
35 void (*wait_for_reset)(u32 cpu);
36 void (*put_in_reset)(u32 cpu);
37 void (*out_of_reset)(u32 cpu);
38 void (*enable_clock)(u32 cpu);
39 void (*disable_clock)(u32 cpu);
40};
41
42extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
43
44static inline void tegra_wait_cpu_in_reset(u32 cpu)
45{
46 if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
47 return;
48
49 tegra_cpu_car_ops->wait_for_reset(cpu);
50}
51
52static inline void tegra_put_cpu_in_reset(u32 cpu)
53{
54 if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
55 return;
56
57 tegra_cpu_car_ops->put_in_reset(cpu);
58}
59
60static inline void tegra_cpu_out_of_reset(u32 cpu)
61{
62 if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
63 return;
64
65 tegra_cpu_car_ops->out_of_reset(cpu);
66}
67
68static inline void tegra_enable_cpu_clock(u32 cpu)
69{
70 if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
71 return;
72
73 tegra_cpu_car_ops->enable_clock(cpu);
74}
75
76static inline void tegra_disable_cpu_clock(u32 cpu)
77{
78 if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
79 return;
80
81 tegra_cpu_car_ops->disable_clock(cpu);
82}
83
84void tegra20_cpu_car_ops_init(void);
85void tegra30_cpu_car_ops_init(void);
86
87#endif /* __MACH_TEGRA_CPU_CAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 07:51:16 -0500