diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-19 08:44:41 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-29 19:48:51 -0400 |
commit | 36bccb11a4ac7cc9d190c3062945f1c911a62801 (patch) | |
tree | 499ae758e459a3334a96ab82084c9fd15f5208ea /arch/arm/mach-tegra | |
parent | 4374d64933b1d0f0ebbad064289ef44b869d77c1 (diff) |
ARM: l2c: remove platforms/SoCs setting early BRESP
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r-- | arch/arm/mach-tegra/tegra.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 6191603379e1..ecbb5411a104 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
@@ -89,9 +89,9 @@ static void __init tegra_init_cache(void) | |||
89 | 89 | ||
90 | cache_type = readl(p + L2X0_CACHE_TYPE); | 90 | cache_type = readl(p + L2X0_CACHE_TYPE); |
91 | aux_ctrl = (cache_type & 0x700) << (17-8); | 91 | aux_ctrl = (cache_type & 0x700) << (17-8); |
92 | aux_ctrl |= 0x7C400001; | 92 | aux_ctrl |= 0x3c400001; |
93 | 93 | ||
94 | ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); | 94 | ret = l2x0_of_init(aux_ctrl, 0xc200c3fe); |
95 | if (!ret) | 95 | if (!ret) |
96 | l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); | 96 | l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); |
97 | #endif | 97 | #endif |