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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 08:25:22 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:57 -0400
commit6845664a6a7d443f03883db59d10749d38d98b8e (patch)
tree4b4499f4d41f24152190220d93ea186fbf991fca /arch/arm/mach-tegra
parent25a5662a13e604d86b0a9fd71703582a7393d8ec (diff)
arm: Cleanup the irq namespace
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/gpio.c18
-rw-r--r--arch/arm/mach-tegra/irq.c6
2 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 8ab2131f41d4..4148048c4191 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -208,9 +208,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
208 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 208 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
209 209
210 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 210 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
211 __set_irq_handler_unlocked(d->irq, handle_level_irq); 211 __irq_set_handler_locked(d->irq, handle_level_irq);
212 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 212 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
213 __set_irq_handler_unlocked(d->irq, handle_edge_irq); 213 __irq_set_handler_locked(d->irq, handle_edge_irq);
214 214
215 return 0; 215 return 0;
216} 216}
@@ -224,7 +224,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
224 224
225 desc->irq_data.chip->irq_ack(&desc->irq_data); 225 desc->irq_data.chip->irq_ack(&desc->irq_data);
226 226
227 bank = get_irq_data(irq); 227 bank = irq_get_handler_data(irq);
228 228
229 for (port = 0; port < 4; port++) { 229 for (port = 0; port < 4; port++) {
230 int gpio = tegra_gpio_compose(bank->bank, port, 0); 230 int gpio = tegra_gpio_compose(bank->bank, port, 0);
@@ -301,7 +301,7 @@ void tegra_gpio_suspend(void)
301static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) 301static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
302{ 302{
303 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 303 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
304 return set_irq_wake(bank->irq, enable); 304 return irq_set_irq_wake(bank->irq, enable);
305} 305}
306#endif 306#endif
307 307
@@ -341,17 +341,17 @@ static int __init tegra_gpio_init(void)
341 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; 341 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
342 342
343 irq_set_lockdep_class(i, &gpio_lock_class); 343 irq_set_lockdep_class(i, &gpio_lock_class);
344 set_irq_chip_data(i, bank); 344 irq_set_chip_data(i, bank);
345 set_irq_chip(i, &tegra_gpio_irq_chip); 345 irq_set_chip(i, &tegra_gpio_irq_chip);
346 set_irq_handler(i, handle_simple_irq); 346 irq_set_handler(i, handle_simple_irq);
347 set_irq_flags(i, IRQF_VALID); 347 set_irq_flags(i, IRQF_VALID);
348 } 348 }
349 349
350 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { 350 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
351 bank = &tegra_gpio_banks[i]; 351 bank = &tegra_gpio_banks[i];
352 352
353 set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); 353 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
354 set_irq_data(bank->irq, bank); 354 irq_set_handler_data(bank->irq, bank);
355 355
356 for (j = 0; j < 4; j++) 356 for (j = 0; j < 4; j++)
357 spin_lock_init(&bank->lvl_lock[j]); 357 spin_lock_init(&bank->lvl_lock[j]);
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index dfbc219ea492..6b5c8b8abe02 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -144,7 +144,7 @@ void __init tegra_init_irq(void)
144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146 146
147 gic = get_irq_chip(29); 147 gic = irq_get_chip(29);
148 tegra_gic_unmask_irq = gic->irq_unmask; 148 tegra_gic_unmask_irq = gic->irq_unmask;
149 tegra_gic_mask_irq = gic->irq_mask; 149 tegra_gic_mask_irq = gic->irq_mask;
150 tegra_gic_ack_irq = gic->irq_ack; 150 tegra_gic_ack_irq = gic->irq_ack;
@@ -154,8 +154,8 @@ void __init tegra_init_irq(void)
154 154
155 for (i = 0; i < INT_MAIN_NR; i++) { 155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i; 156 irq = INT_PRI_BASE + i;
157 set_irq_chip(irq, &tegra_irq); 157 irq_set_chip(irq, &tegra_irq);
158 set_irq_handler(irq, handle_level_irq); 158 irq_set_handler(irq, handle_level_irq);
159 set_irq_flags(irq, IRQF_VALID); 159 set_irq_flags(irq, IRQF_VALID);
160 } 160 }
161} 161}