diff options
author | Hiroshi Doyu <hdoyu@nvidia.com> | 2013-01-03 01:27:05 -0500 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 12:21:28 -0500 |
commit | deeb8d194814c98be379a284e07d938c6af066f4 (patch) | |
tree | 0ced7fa5bf9faa3d1ab8db5e01d45d13ab6ceefb /arch/arm/mach-tegra | |
parent | 37340866fb659f955489bd0742788135156a4d3c (diff) |
ARM: tegra: Make variables static
No need to be public. Checked with:
$ touch arch/arm/mach-tegra/*[ch] && make C=1
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r-- | arch/arm/mach-tegra/apbio.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-dt-tegra20.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-dt-tegra30.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/flowctrl.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30_clocks_data.c | 6 |
5 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index d091675ba376..d7aa52ea6cfc 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c | |||
@@ -38,7 +38,7 @@ static void tegra_apb_writel_direct(u32 value, unsigned long offset); | |||
38 | static struct dma_chan *tegra_apb_dma_chan; | 38 | static struct dma_chan *tegra_apb_dma_chan; |
39 | static struct dma_slave_config dma_sconfig; | 39 | static struct dma_slave_config dma_sconfig; |
40 | 40 | ||
41 | bool tegra_apb_dma_init(void) | 41 | static bool tegra_apb_dma_init(void) |
42 | { | 42 | { |
43 | dma_cap_mask_t mask; | 43 | dma_cap_mask_t mask; |
44 | 44 | ||
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 8e35aaea5845..e1f87dd314ef 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c | |||
@@ -46,31 +46,31 @@ | |||
46 | #include "common.h" | 46 | #include "common.h" |
47 | #include "iomap.h" | 47 | #include "iomap.h" |
48 | 48 | ||
49 | struct tegra_ehci_platform_data tegra_ehci1_pdata = { | 49 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { |
50 | .operating_mode = TEGRA_USB_OTG, | 50 | .operating_mode = TEGRA_USB_OTG, |
51 | .power_down_on_bus_suspend = 1, | 51 | .power_down_on_bus_suspend = 1, |
52 | .vbus_gpio = -1, | 52 | .vbus_gpio = -1, |
53 | }; | 53 | }; |
54 | 54 | ||
55 | struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { | 55 | static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { |
56 | .reset_gpio = -1, | 56 | .reset_gpio = -1, |
57 | .clk = "cdev2", | 57 | .clk = "cdev2", |
58 | }; | 58 | }; |
59 | 59 | ||
60 | struct tegra_ehci_platform_data tegra_ehci2_pdata = { | 60 | static struct tegra_ehci_platform_data tegra_ehci2_pdata = { |
61 | .phy_config = &tegra_ehci2_ulpi_phy_config, | 61 | .phy_config = &tegra_ehci2_ulpi_phy_config, |
62 | .operating_mode = TEGRA_USB_HOST, | 62 | .operating_mode = TEGRA_USB_HOST, |
63 | .power_down_on_bus_suspend = 1, | 63 | .power_down_on_bus_suspend = 1, |
64 | .vbus_gpio = -1, | 64 | .vbus_gpio = -1, |
65 | }; | 65 | }; |
66 | 66 | ||
67 | struct tegra_ehci_platform_data tegra_ehci3_pdata = { | 67 | static struct tegra_ehci_platform_data tegra_ehci3_pdata = { |
68 | .operating_mode = TEGRA_USB_HOST, | 68 | .operating_mode = TEGRA_USB_HOST, |
69 | .power_down_on_bus_suspend = 1, | 69 | .power_down_on_bus_suspend = 1, |
70 | .vbus_gpio = -1, | 70 | .vbus_gpio = -1, |
71 | }; | 71 | }; |
72 | 72 | ||
73 | struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { | 73 | static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { |
74 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), | 74 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), |
75 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), | 75 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), |
76 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), | 76 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), |
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index a9ed15dcc3ed..cfe5fc02be77 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c | |||
@@ -39,7 +39,7 @@ | |||
39 | #include "common.h" | 39 | #include "common.h" |
40 | #include "iomap.h" | 40 | #include "iomap.h" |
41 | 41 | ||
42 | struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { | 42 | static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { |
43 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), | 43 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), |
44 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL), | 44 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL), |
45 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL), | 45 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL), |
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index a2250ddae797..5393eb2cae21 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c | |||
@@ -26,14 +26,14 @@ | |||
26 | #include "flowctrl.h" | 26 | #include "flowctrl.h" |
27 | #include "iomap.h" | 27 | #include "iomap.h" |
28 | 28 | ||
29 | u8 flowctrl_offset_halt_cpu[] = { | 29 | static u8 flowctrl_offset_halt_cpu[] = { |
30 | FLOW_CTRL_HALT_CPU0_EVENTS, | 30 | FLOW_CTRL_HALT_CPU0_EVENTS, |
31 | FLOW_CTRL_HALT_CPU1_EVENTS, | 31 | FLOW_CTRL_HALT_CPU1_EVENTS, |
32 | FLOW_CTRL_HALT_CPU1_EVENTS + 8, | 32 | FLOW_CTRL_HALT_CPU1_EVENTS + 8, |
33 | FLOW_CTRL_HALT_CPU1_EVENTS + 16, | 33 | FLOW_CTRL_HALT_CPU1_EVENTS + 16, |
34 | }; | 34 | }; |
35 | 35 | ||
36 | u8 flowctrl_offset_cpu_csr[] = { | 36 | static u8 flowctrl_offset_cpu_csr[] = { |
37 | FLOW_CTRL_CPU0_CSR, | 37 | FLOW_CTRL_CPU0_CSR, |
38 | FLOW_CTRL_CPU1_CSR, | 38 | FLOW_CTRL_CPU1_CSR, |
39 | FLOW_CTRL_CPU1_CSR + 8, | 39 | FLOW_CTRL_CPU1_CSR + 8, |
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c index 6942c7add3bb..741d264d5ecb 100644 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c | |||
@@ -1183,7 +1183,7 @@ static struct clk tegra_dsib = { | |||
1183 | .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0), | 1183 | .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0), |
1184 | }; | 1184 | }; |
1185 | 1185 | ||
1186 | struct clk *tegra_list_clks[] = { | 1186 | static struct clk *tegra_list_clks[] = { |
1187 | &tegra_apbdma, | 1187 | &tegra_apbdma, |
1188 | &tegra_rtc, | 1188 | &tegra_rtc, |
1189 | &tegra_kbc, | 1189 | &tegra_kbc, |
@@ -1289,7 +1289,7 @@ struct clk *tegra_list_clks[] = { | |||
1289 | * configuration. List those here to register them twice in the clock lookup | 1289 | * configuration. List those here to register them twice in the clock lookup |
1290 | * table under two names. | 1290 | * table under two names. |
1291 | */ | 1291 | */ |
1292 | struct clk_duplicate tegra_clk_duplicates[] = { | 1292 | static struct clk_duplicate tegra_clk_duplicates[] = { |
1293 | CLK_DUPLICATE("uarta", "serial8250.0", NULL), | 1293 | CLK_DUPLICATE("uarta", "serial8250.0", NULL), |
1294 | CLK_DUPLICATE("uartb", "serial8250.1", NULL), | 1294 | CLK_DUPLICATE("uartb", "serial8250.1", NULL), |
1295 | CLK_DUPLICATE("uartc", "serial8250.2", NULL), | 1295 | CLK_DUPLICATE("uartc", "serial8250.2", NULL), |
@@ -1340,7 +1340,7 @@ struct clk_duplicate tegra_clk_duplicates[] = { | |||
1340 | CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"), | 1340 | CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"), |
1341 | }; | 1341 | }; |
1342 | 1342 | ||
1343 | struct clk *tegra_ptr_clks[] = { | 1343 | static struct clk *tegra_ptr_clks[] = { |
1344 | &tegra_clk_32k, | 1344 | &tegra_clk_32k, |
1345 | &tegra_clk_m, | 1345 | &tegra_clk_m, |
1346 | &tegra_clk_m_div2, | 1346 | &tegra_clk_m_div2, |