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authorPrashant Gaikwad <pgaikwad@nvidia.com>2012-08-06 02:27:43 -0400
committerStephen Warren <swarren@nvidia.com>2012-09-06 13:47:20 -0400
commit92fe58f07f6e51185497785aed632d0e676afe6e (patch)
tree3791468579de25fa4ada69abacdaf9666a8b7657 /arch/arm/mach-tegra
parent96a1bd1e11ade7be969d275edd4c06749684cdba (diff)
ARM: tegra: Port tegra to generic clock framework
This patch converts tegra clock code to generic clock framework in following way: - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c) - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk. - Initialize all clock data statically. (tegraXX_clocks_data.c) Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions. Removed init function. It's functionality is splitted into recalc_rate and is_enabled. Static initialization is used since slab is not up in .init_early and clock is needed to be initialized before clockevent/clocksource initialization. Macros redefined for clk_tegra. Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This is to move quickly to generic common clock framework so that other dependent features will not be blocked (such as DT binding). Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20 and Tegra30. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/clock.h1
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c1062
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.h4
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c1300
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c1332
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h14
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1688
7 files changed, 3056 insertions, 2345 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index f4d32ba56027..be69ae1156c2 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -233,6 +233,7 @@ int clk_set_rate_locked(struct clk *c, unsigned long rate);
233int clk_reparent(struct clk *c, struct clk *parent); 233int clk_reparent(struct clk *c, struct clk *parent);
234#endif /* !CONFIG_COMMON_CLK */ 234#endif /* !CONFIG_COMMON_CLK */
235 235
236void tegra_clk_add(struct clk *c);
236void tegra2_init_clocks(void); 237void tegra2_init_clocks(void);
237void tegra30_init_clocks(void); 238void tegra30_init_clocks(void);
238struct clk *tegra_get_clock_by_name(const char *name); 239struct clk *tegra_get_clock_by_name(const char *name);
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 4a32030a4d96..a1e0f8a26b3d 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c 2 * arch/arm/mach-tegra/tegra20_clocks.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * Author: 7 * Author:
7 * Colin Cross <ccross@google.com> 8 * Colin Cross <ccross@google.com>
@@ -98,7 +99,7 @@
98#define PLL_OUT_CLKEN (1<<1) 99#define PLL_OUT_CLKEN (1<<1)
99#define PLL_OUT_RESET_DISABLE (1<<0) 100#define PLL_OUT_RESET_DISABLE (1<<0)
100 101
101#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) 102#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
102 103
103#define PLL_MISC_DCCON_SHIFT 20 104#define PLL_MISC_DCCON_SHIFT 20
104#define PLL_MISC_CPCON_SHIFT 8 105#define PLL_MISC_CPCON_SHIFT 8
@@ -191,7 +192,8 @@ static unsigned long clk_measure_input_freq(void)
191 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { 192 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
192 return 26000000; 193 return 26000000;
193 } else { 194 } else {
194 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect); 195 pr_err("%s: Unexpected clock autodetect value %d",
196 __func__, clock_autodetect);
195 BUG(); 197 BUG();
196 return 0; 198 return 0;
197 } 199 }
@@ -230,12 +232,21 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
230} 232}
231 233
232/* clk_m functions */ 234/* clk_m functions */
233static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) 235static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
236 unsigned long prate)
234{ 237{
235 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK; 238 if (!to_clk_tegra(hw)->fixed_rate)
239 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
240 return to_clk_tegra(hw)->fixed_rate;
241}
242
243static void tegra20_clk_m_init(struct clk_hw *hw)
244{
245 struct clk_tegra *c = to_clk_tegra(hw);
246 u32 osc_ctrl = clk_readl(OSC_CTRL);
247 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
236 248
237 c->rate = clk_measure_input_freq(); 249 switch (c->fixed_rate) {
238 switch (c->rate) {
239 case 12000000: 250 case 12000000:
240 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; 251 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
241 break; 252 break;
@@ -249,35 +260,14 @@ static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
249 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; 260 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
250 break; 261 break;
251 default: 262 default:
252 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
253 BUG(); 263 BUG();
254 } 264 }
255 clk_writel(auto_clock_control, OSC_CTRL); 265 clk_writel(auto_clock_control, OSC_CTRL);
256 return c->rate;
257}
258
259static void tegra2_clk_m_init(struct clk *c)
260{
261 pr_debug("%s on clock %s\n", __func__, c->name);
262 tegra2_clk_m_autodetect_rate(c);
263}
264
265static int tegra2_clk_m_enable(struct clk *c)
266{
267 pr_debug("%s on clock %s\n", __func__, c->name);
268 return 0;
269}
270
271static void tegra2_clk_m_disable(struct clk *c)
272{
273 pr_debug("%s on clock %s\n", __func__, c->name);
274 BUG();
275} 266}
276 267
277struct clk_ops tegra_clk_m_ops = { 268struct clk_ops tegra_clk_m_ops = {
278 .init = tegra2_clk_m_init, 269 .init = tegra20_clk_m_init,
279 .enable = tegra2_clk_m_enable, 270 .recalc_rate = tegra20_clk_m_recalc_rate,
280 .disable = tegra2_clk_m_disable,
281}; 271};
282 272
283/* super clock functions */ 273/* super clock functions */
@@ -286,161 +276,108 @@ struct clk_ops tegra_clk_m_ops = {
286 * can't lower the voltage when using the clock skip, but we can if we 276 * can't lower the voltage when using the clock skip, but we can if we
287 * lower the PLL frequency. 277 * lower the PLL frequency.
288 */ 278 */
289static void tegra2_super_clk_init(struct clk *c) 279static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
290{ 280{
281 struct clk_tegra *c = to_clk_tegra(hw);
291 u32 val; 282 u32 val;
292 int source; 283
293 int shift;
294 const struct clk_mux_sel *sel;
295 val = clk_readl(c->reg + SUPER_CLK_MUX); 284 val = clk_readl(c->reg + SUPER_CLK_MUX);
296 c->state = ON;
297 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && 285 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
298 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 286 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
299 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 287 c->state = ON;
300 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; 288 return c->state;
301 source = (val >> shift) & SUPER_SOURCE_MASK;
302 for (sel = c->inputs; sel->input != NULL; sel++) {
303 if (sel->value == source)
304 break;
305 }
306 BUG_ON(sel->input == NULL);
307 c->parent = sel->input;
308} 289}
309 290
310static int tegra2_super_clk_enable(struct clk *c) 291static int tegra20_super_clk_enable(struct clk_hw *hw)
311{ 292{
293 struct clk_tegra *c = to_clk_tegra(hw);
312 clk_writel(0, c->reg + SUPER_CLK_DIVIDER); 294 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
313 return 0; 295 return 0;
314} 296}
315 297
316static void tegra2_super_clk_disable(struct clk *c) 298static void tegra20_super_clk_disable(struct clk_hw *hw)
317{ 299{
318 pr_debug("%s on clock %s\n", __func__, c->name); 300 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
319 301
320 /* oops - don't disable the CPU clock! */ 302 /* oops - don't disable the CPU clock! */
321 BUG(); 303 BUG();
322} 304}
323 305
324static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) 306static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
325{ 307{
326 u32 val; 308 struct clk_tegra *c = to_clk_tegra(hw);
327 const struct clk_mux_sel *sel; 309 int val = clk_readl(c->reg + SUPER_CLK_MUX);
310 int source;
328 int shift; 311 int shift;
329 312
330 val = clk_readl(c->reg + SUPER_CLK_MUX);
331 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && 313 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
332 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 314 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
333 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 315 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
334 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; 316 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
335 for (sel = c->inputs; sel->input != NULL; sel++) { 317 source = (val >> shift) & SUPER_SOURCE_MASK;
336 if (sel->input == p) { 318 return source;
337 val &= ~(SUPER_SOURCE_MASK << shift); 319}
338 val |= sel->value << shift;
339 320
340 if (c->refcnt) 321static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
341 clk_enable(p); 322{
323 struct clk_tegra *c = to_clk_tegra(hw);
324 u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
325 int shift;
342 326
343 clk_writel(val, c->reg); 327 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
328 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
329 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
330 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
331 val &= ~(SUPER_SOURCE_MASK << shift);
332 val |= index << shift;
344 333
345 if (c->refcnt && c->parent) 334 clk_writel(val, c->reg);
346 clk_disable(c->parent);
347 335
348 clk_reparent(c, p); 336 return 0;
349 return 0;
350 }
351 }
352 return -EINVAL;
353} 337}
354 338
355/* 339/* FIX ME: Need to switch parents to change the source PLL rate */
356 * Super clocks have "clock skippers" instead of dividers. Dividing using 340static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
357 * a clock skipper does not allow the voltage to be scaled down, so instead 341 unsigned long prate)
358 * adjust the rate of the parent clock. This requires that the parent of a
359 * super clock have no other children, otherwise the rate will change
360 * underneath the other children.
361 */
362static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
363{ 342{
364 return clk_set_rate(c->parent, rate); 343 return prate;
365} 344}
366 345
367struct clk_ops tegra_super_ops = { 346static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
368 .init = tegra2_super_clk_init, 347 unsigned long *prate)
369 .enable = tegra2_super_clk_enable,
370 .disable = tegra2_super_clk_disable,
371 .set_parent = tegra2_super_clk_set_parent,
372 .set_rate = tegra2_super_clk_set_rate,
373};
374
375/* virtual cpu clock functions */
376/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
377 To change the frequency of these clocks, the parent pll may need to be
378 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
379 and then the clock moved back to the pll. To hide this sequence, a virtual
380 clock handles it.
381 */
382static void tegra2_cpu_clk_init(struct clk *c)
383{ 348{
349 return *prate;
384} 350}
385 351
386static int tegra2_cpu_clk_enable(struct clk *c) 352static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
353 unsigned long parent_rate)
387{ 354{
388 return 0; 355 return 0;
389} 356}
390 357
391static void tegra2_cpu_clk_disable(struct clk *c) 358struct clk_ops tegra_super_ops = {
392{ 359 .is_enabled = tegra20_super_clk_is_enabled,
393 pr_debug("%s on clock %s\n", __func__, c->name); 360 .enable = tegra20_super_clk_enable,
394 361 .disable = tegra20_super_clk_disable,
395 /* oops - don't disable the CPU clock! */ 362 .set_parent = tegra20_super_clk_set_parent,
396 BUG(); 363 .get_parent = tegra20_super_clk_get_parent,
397} 364 .set_rate = tegra20_super_clk_set_rate,
365 .round_rate = tegra20_super_clk_round_rate,
366 .recalc_rate = tegra20_super_clk_recalc_rate,
367};
398 368
399static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate) 369static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
400{ 370{
401 int ret; 371 return 0;
402 /*
403 * Take an extra reference to the main pll so it doesn't turn
404 * off when we move the cpu off of it
405 */
406 clk_enable(c->u.cpu.main);
407
408 ret = clk_set_parent(c->parent, c->u.cpu.backup);
409 if (ret) {
410 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
411 goto out;
412 }
413
414 if (rate == clk_get_rate(c->u.cpu.backup))
415 goto out;
416
417 ret = clk_set_rate(c->u.cpu.main, rate);
418 if (ret) {
419 pr_err("Failed to change cpu pll to %lu\n", rate);
420 goto out;
421 }
422
423 ret = clk_set_parent(c->parent, c->u.cpu.main);
424 if (ret) {
425 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
426 goto out;
427 }
428
429out:
430 clk_disable(c->u.cpu.main);
431 return ret;
432} 372}
433 373
434struct clk_ops tegra_cpu_ops = { 374struct clk_ops tegra_cop_ops = {
435 .init = tegra2_cpu_clk_init, 375 .get_parent = tegra20_cop_clk_get_parent,
436 .enable = tegra2_cpu_clk_enable,
437 .disable = tegra2_cpu_clk_disable,
438 .set_rate = tegra2_cpu_clk_set_rate,
439}; 376};
440 377
441/* virtual cop clock functions. Used to acquire the fake 'cop' clock to 378/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
442 * reset the COP block (i.e. AVP) */ 379 * reset the COP block (i.e. AVP) */
443static void tegra2_cop_clk_reset(struct clk *c, bool assert) 380void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
444{ 381{
445 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; 382 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
446 383
@@ -448,23 +385,21 @@ static void tegra2_cop_clk_reset(struct clk *c, bool assert)
448 clk_writel(1 << 1, reg); 385 clk_writel(1 << 1, reg);
449} 386}
450 387
451struct clk_ops tegra_cop_ops = {
452 .reset = tegra2_cop_clk_reset,
453};
454
455/* bus clock functions */ 388/* bus clock functions */
456static void tegra2_bus_clk_init(struct clk *c) 389static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
457{ 390{
391 struct clk_tegra *c = to_clk_tegra(hw);
458 u32 val = clk_readl(c->reg); 392 u32 val = clk_readl(c->reg);
393
459 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; 394 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
460 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; 395 return c->state;
461 c->mul = 1;
462} 396}
463 397
464static int tegra2_bus_clk_enable(struct clk *c) 398static int tegra20_bus_clk_enable(struct clk_hw *hw)
465{ 399{
466 u32 val; 400 struct clk_tegra *c = to_clk_tegra(hw);
467 unsigned long flags; 401 unsigned long flags;
402 u32 val;
468 403
469 spin_lock_irqsave(&clock_register_lock, flags); 404 spin_lock_irqsave(&clock_register_lock, flags);
470 405
@@ -477,10 +412,11 @@ static int tegra2_bus_clk_enable(struct clk *c)
477 return 0; 412 return 0;
478} 413}
479 414
480static void tegra2_bus_clk_disable(struct clk *c) 415static void tegra20_bus_clk_disable(struct clk_hw *hw)
481{ 416{
482 u32 val; 417 struct clk_tegra *c = to_clk_tegra(hw);
483 unsigned long flags; 418 unsigned long flags;
419 u32 val;
484 420
485 spin_lock_irqsave(&clock_register_lock, flags); 421 spin_lock_irqsave(&clock_register_lock, flags);
486 422
@@ -491,12 +427,31 @@ static void tegra2_bus_clk_disable(struct clk *c)
491 spin_unlock_irqrestore(&clock_register_lock, flags); 427 spin_unlock_irqrestore(&clock_register_lock, flags);
492} 428}
493 429
494static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) 430static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
431 unsigned long prate)
495{ 432{
496 u32 val; 433 struct clk_tegra *c = to_clk_tegra(hw);
497 unsigned long parent_rate = clk_get_rate(c->parent); 434 u32 val = clk_readl(c->reg);
498 unsigned long flags; 435 u64 rate = prate;
436
437 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
438 c->mul = 1;
439
440 if (c->mul != 0 && c->div != 0) {
441 rate *= c->mul;
442 rate += c->div - 1; /* round up */
443 do_div(rate, c->div);
444 }
445 return rate;
446}
447
448static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
449 unsigned long parent_rate)
450{
451 struct clk_tegra *c = to_clk_tegra(hw);
499 int ret = -EINVAL; 452 int ret = -EINVAL;
453 unsigned long flags;
454 u32 val;
500 int i; 455 int i;
501 456
502 spin_lock_irqsave(&clock_register_lock, flags); 457 spin_lock_irqsave(&clock_register_lock, flags);
@@ -519,21 +474,56 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
519 return ret; 474 return ret;
520} 475}
521 476
477static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
478 unsigned long *prate)
479{
480 unsigned long parent_rate = *prate;
481 s64 divider;
482
483 if (rate >= parent_rate)
484 return rate;
485
486 divider = parent_rate;
487 divider += rate - 1;
488 do_div(divider, rate);
489
490 if (divider < 0)
491 return divider;
492
493 if (divider > 4)
494 divider = 4;
495 do_div(parent_rate, divider);
496
497 return parent_rate;
498}
499
522struct clk_ops tegra_bus_ops = { 500struct clk_ops tegra_bus_ops = {
523 .init = tegra2_bus_clk_init, 501 .is_enabled = tegra20_bus_clk_is_enabled,
524 .enable = tegra2_bus_clk_enable, 502 .enable = tegra20_bus_clk_enable,
525 .disable = tegra2_bus_clk_disable, 503 .disable = tegra20_bus_clk_disable,
526 .set_rate = tegra2_bus_clk_set_rate, 504 .set_rate = tegra20_bus_clk_set_rate,
505 .round_rate = tegra20_bus_clk_round_rate,
506 .recalc_rate = tegra20_bus_clk_recalc_rate,
527}; 507};
528 508
529/* Blink output functions */ 509/* Blink output functions */
530 510static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
531static void tegra2_blink_clk_init(struct clk *c)
532{ 511{
512 struct clk_tegra *c = to_clk_tegra(hw);
533 u32 val; 513 u32 val;
534 514
535 val = pmc_readl(PMC_CTRL); 515 val = pmc_readl(PMC_CTRL);
536 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; 516 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
517 return c->state;
518}
519
520static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
521 unsigned long prate)
522{
523 struct clk_tegra *c = to_clk_tegra(hw);
524 u64 rate = prate;
525 u32 val;
526
537 c->mul = 1; 527 c->mul = 1;
538 val = pmc_readl(c->reg); 528 val = pmc_readl(c->reg);
539 529
@@ -550,9 +540,16 @@ static void tegra2_blink_clk_init(struct clk *c)
550 } else { 540 } else {
551 c->div = 1; 541 c->div = 1;
552 } 542 }
543
544 if (c->mul != 0 && c->div != 0) {
545 rate *= c->mul;
546 rate += c->div - 1; /* round up */
547 do_div(rate, c->div);
548 }
549 return rate;
553} 550}
554 551
555static int tegra2_blink_clk_enable(struct clk *c) 552static int tegra20_blink_clk_enable(struct clk_hw *hw)
556{ 553{
557 u32 val; 554 u32 val;
558 555
@@ -565,7 +562,7 @@ static int tegra2_blink_clk_enable(struct clk *c)
565 return 0; 562 return 0;
566} 563}
567 564
568static void tegra2_blink_clk_disable(struct clk *c) 565static void tegra20_blink_clk_disable(struct clk_hw *hw)
569{ 566{
570 u32 val; 567 u32 val;
571 568
@@ -576,9 +573,11 @@ static void tegra2_blink_clk_disable(struct clk *c)
576 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); 573 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
577} 574}
578 575
579static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate) 576static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
577 unsigned long parent_rate)
580{ 578{
581 unsigned long parent_rate = clk_get_rate(c->parent); 579 struct clk_tegra *c = to_clk_tegra(hw);
580
582 if (rate >= parent_rate) { 581 if (rate >= parent_rate) {
583 c->div = 1; 582 c->div = 1;
584 pmc_writel(0, c->reg); 583 pmc_writel(0, c->reg);
@@ -601,31 +600,74 @@ static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
601 return 0; 600 return 0;
602} 601}
603 602
603static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
604 unsigned long *prate)
605{
606 int div;
607 int mul;
608 long round_rate = *prate;
609
610 mul = 1;
611
612 if (rate >= *prate) {
613 div = 1;
614 } else {
615 div = DIV_ROUND_UP(*prate / 8, rate);
616 div *= 8;
617 }
618
619 round_rate *= mul;
620 round_rate += div - 1;
621 do_div(round_rate, div);
622
623 return round_rate;
624}
625
604struct clk_ops tegra_blink_clk_ops = { 626struct clk_ops tegra_blink_clk_ops = {
605 .init = &tegra2_blink_clk_init, 627 .is_enabled = tegra20_blink_clk_is_enabled,
606 .enable = &tegra2_blink_clk_enable, 628 .enable = tegra20_blink_clk_enable,
607 .disable = &tegra2_blink_clk_disable, 629 .disable = tegra20_blink_clk_disable,
608 .set_rate = &tegra2_blink_clk_set_rate, 630 .set_rate = tegra20_blink_clk_set_rate,
631 .round_rate = tegra20_blink_clk_round_rate,
632 .recalc_rate = tegra20_blink_clk_recalc_rate,
609}; 633};
610 634
611/* PLL Functions */ 635/* PLL Functions */
612static int tegra2_pll_clk_wait_for_lock(struct clk *c) 636static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
613{ 637{
614 udelay(c->u.pll.lock_delay); 638 udelay(c->u.pll.lock_delay);
615
616 return 0; 639 return 0;
617} 640}
618 641
619static void tegra2_pll_clk_init(struct clk *c) 642static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
620{ 643{
644 struct clk_tegra *c = to_clk_tegra(hw);
621 u32 val = clk_readl(c->reg + PLL_BASE); 645 u32 val = clk_readl(c->reg + PLL_BASE);
622 646
623 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; 647 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
648 return c->state;
649}
650
651static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
652 unsigned long prate)
653{
654 struct clk_tegra *c = to_clk_tegra(hw);
655 u32 val = clk_readl(c->reg + PLL_BASE);
656 u64 rate = prate;
624 657
625 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { 658 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
626 pr_warning("Clock %s has unknown fixed frequency\n", c->name); 659 const struct clk_pll_freq_table *sel;
627 c->mul = 1; 660 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
628 c->div = 1; 661 if (sel->input_rate == prate &&
662 sel->output_rate == c->u.pll.fixed_rate) {
663 c->mul = sel->n;
664 c->div = sel->m * sel->p;
665 break;
666 }
667 }
668 pr_err("Clock %s has unknown fixed frequency\n",
669 __clk_get_name(hw->clk));
670 BUG();
629 } else if (val & PLL_BASE_BYPASS) { 671 } else if (val & PLL_BASE_BYPASS) {
630 c->mul = 1; 672 c->mul = 1;
631 c->div = 1; 673 c->div = 1;
@@ -637,42 +679,63 @@ static void tegra2_pll_clk_init(struct clk *c)
637 else 679 else
638 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1; 680 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
639 } 681 }
682
683 if (c->mul != 0 && c->div != 0) {
684 rate *= c->mul;
685 rate += c->div - 1; /* round up */
686 do_div(rate, c->div);
687 }
688 return rate;
640} 689}
641 690
642static int tegra2_pll_clk_enable(struct clk *c) 691static int tegra20_pll_clk_enable(struct clk_hw *hw)
643{ 692{
693 struct clk_tegra *c = to_clk_tegra(hw);
644 u32 val; 694 u32 val;
645 pr_debug("%s on clock %s\n", __func__, c->name); 695 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
646 696
647 val = clk_readl(c->reg + PLL_BASE); 697 val = clk_readl(c->reg + PLL_BASE);
648 val &= ~PLL_BASE_BYPASS; 698 val &= ~PLL_BASE_BYPASS;
649 val |= PLL_BASE_ENABLE; 699 val |= PLL_BASE_ENABLE;
650 clk_writel(val, c->reg + PLL_BASE); 700 clk_writel(val, c->reg + PLL_BASE);
651 701
652 tegra2_pll_clk_wait_for_lock(c); 702 tegra20_pll_clk_wait_for_lock(c);
653 703
654 return 0; 704 return 0;
655} 705}
656 706
657static void tegra2_pll_clk_disable(struct clk *c) 707static void tegra20_pll_clk_disable(struct clk_hw *hw)
658{ 708{
709 struct clk_tegra *c = to_clk_tegra(hw);
659 u32 val; 710 u32 val;
660 pr_debug("%s on clock %s\n", __func__, c->name); 711 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
661 712
662 val = clk_readl(c->reg); 713 val = clk_readl(c->reg);
663 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 714 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
664 clk_writel(val, c->reg); 715 clk_writel(val, c->reg);
665} 716}
666 717
667static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) 718static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
719 unsigned long parent_rate)
668{ 720{
669 u32 val; 721 struct clk_tegra *c = to_clk_tegra(hw);
670 unsigned long input_rate; 722 unsigned long input_rate = parent_rate;
671 const struct clk_pll_freq_table *sel; 723 const struct clk_pll_freq_table *sel;
724 u32 val;
672 725
673 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 726 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
727
728 if (c->flags & PLL_FIXED) {
729 int ret = 0;
730 if (rate != c->u.pll.fixed_rate) {
731 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
732 __func__, __clk_get_name(hw->clk),
733 c->u.pll.fixed_rate, rate);
734 ret = -EINVAL;
735 }
736 return ret;
737 }
674 738
675 input_rate = clk_get_rate(c->parent);
676 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 739 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
677 if (sel->input_rate == input_rate && sel->output_rate == rate) { 740 if (sel->input_rate == input_rate && sel->output_rate == rate) {
678 c->mul = sel->n; 741 c->mul = sel->n;
@@ -703,41 +766,76 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
703 } 766 }
704 767
705 if (c->state == ON) 768 if (c->state == ON)
706 tegra2_pll_clk_enable(c); 769 tegra20_pll_clk_enable(hw);
707
708 return 0; 770 return 0;
709 } 771 }
710 } 772 }
711 return -EINVAL; 773 return -EINVAL;
712} 774}
713 775
776static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
777 unsigned long *prate)
778{
779 struct clk_tegra *c = to_clk_tegra(hw);
780 const struct clk_pll_freq_table *sel;
781 unsigned long input_rate = *prate;
782 unsigned long output_rate = *prate;
783 int mul;
784 int div;
785
786 if (c->flags & PLL_FIXED)
787 return c->u.pll.fixed_rate;
788
789 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
790 if (sel->input_rate == input_rate && sel->output_rate == rate) {
791 mul = sel->n;
792 div = sel->m * sel->p;
793 break;
794 }
795
796 if (sel->input_rate == 0)
797 return -EINVAL;
798
799 output_rate *= mul;
800 output_rate += div - 1; /* round up */
801 do_div(output_rate, div);
802
803 return output_rate;
804}
805
714struct clk_ops tegra_pll_ops = { 806struct clk_ops tegra_pll_ops = {
715 .init = tegra2_pll_clk_init, 807 .is_enabled = tegra20_pll_clk_is_enabled,
716 .enable = tegra2_pll_clk_enable, 808 .enable = tegra20_pll_clk_enable,
717 .disable = tegra2_pll_clk_disable, 809 .disable = tegra20_pll_clk_disable,
718 .set_rate = tegra2_pll_clk_set_rate, 810 .set_rate = tegra20_pll_clk_set_rate,
811 .recalc_rate = tegra20_pll_clk_recalc_rate,
812 .round_rate = tegra20_pll_clk_round_rate,
719}; 813};
720 814
721static void tegra2_pllx_clk_init(struct clk *c) 815static void tegra20_pllx_clk_init(struct clk_hw *hw)
722{ 816{
723 tegra2_pll_clk_init(c); 817 struct clk_tegra *c = to_clk_tegra(hw);
724 818
725 if (tegra_sku_id == 7) 819 if (tegra_sku_id == 7)
726 c->max_rate = 750000000; 820 c->max_rate = 750000000;
727} 821}
728 822
729struct clk_ops tegra_pllx_ops = { 823struct clk_ops tegra_pllx_ops = {
730 .init = tegra2_pllx_clk_init, 824 .init = tegra20_pllx_clk_init,
731 .enable = tegra2_pll_clk_enable, 825 .is_enabled = tegra20_pll_clk_is_enabled,
732 .disable = tegra2_pll_clk_disable, 826 .enable = tegra20_pll_clk_enable,
733 .set_rate = tegra2_pll_clk_set_rate, 827 .disable = tegra20_pll_clk_disable,
828 .set_rate = tegra20_pll_clk_set_rate,
829 .recalc_rate = tegra20_pll_clk_recalc_rate,
830 .round_rate = tegra20_pll_clk_round_rate,
734}; 831};
735 832
736static int tegra2_plle_clk_enable(struct clk *c) 833static int tegra20_plle_clk_enable(struct clk_hw *hw)
737{ 834{
835 struct clk_tegra *c = to_clk_tegra(hw);
738 u32 val; 836 u32 val;
739 837
740 pr_debug("%s on clock %s\n", __func__, c->name); 838 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
741 839
742 mdelay(1); 840 mdelay(1);
743 841
@@ -753,20 +851,35 @@ static int tegra2_plle_clk_enable(struct clk *c)
753} 851}
754 852
755struct clk_ops tegra_plle_ops = { 853struct clk_ops tegra_plle_ops = {
756 .init = tegra2_pll_clk_init, 854 .is_enabled = tegra20_pll_clk_is_enabled,
757 .enable = tegra2_plle_clk_enable, 855 .enable = tegra20_plle_clk_enable,
758 .set_rate = tegra2_pll_clk_set_rate, 856 .set_rate = tegra20_pll_clk_set_rate,
857 .recalc_rate = tegra20_pll_clk_recalc_rate,
858 .round_rate = tegra20_pll_clk_round_rate,
759}; 859};
760 860
761/* Clock divider ops */ 861/* Clock divider ops */
762static void tegra2_pll_div_clk_init(struct clk *c) 862static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
763{ 863{
864 struct clk_tegra *c = to_clk_tegra(hw);
764 u32 val = clk_readl(c->reg); 865 u32 val = clk_readl(c->reg);
765 u32 divu71; 866
766 val >>= c->reg_shift; 867 val >>= c->reg_shift;
767 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; 868 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
768 if (!(val & PLL_OUT_RESET_DISABLE)) 869 if (!(val & PLL_OUT_RESET_DISABLE))
769 c->state = OFF; 870 c->state = OFF;
871 return c->state;
872}
873
874static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
875 unsigned long prate)
876{
877 struct clk_tegra *c = to_clk_tegra(hw);
878 u64 rate = prate;
879 u32 val = clk_readl(c->reg);
880 u32 divu71;
881
882 val >>= c->reg_shift;
770 883
771 if (c->flags & DIV_U71) { 884 if (c->flags & DIV_U71) {
772 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; 885 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
@@ -779,15 +892,23 @@ static void tegra2_pll_div_clk_init(struct clk *c)
779 c->div = 1; 892 c->div = 1;
780 c->mul = 1; 893 c->mul = 1;
781 } 894 }
895
896 rate *= c->mul;
897 rate += c->div - 1; /* round up */
898 do_div(rate, c->div);
899
900 return rate;
782} 901}
783 902
784static int tegra2_pll_div_clk_enable(struct clk *c) 903static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
785{ 904{
786 u32 val; 905 struct clk_tegra *c = to_clk_tegra(hw);
787 u32 new_val;
788 unsigned long flags; 906 unsigned long flags;
907 u32 new_val;
908 u32 val;
909
910 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
789 911
790 pr_debug("%s: %s\n", __func__, c->name);
791 if (c->flags & DIV_U71) { 912 if (c->flags & DIV_U71) {
792 spin_lock_irqsave(&clock_register_lock, flags); 913 spin_lock_irqsave(&clock_register_lock, flags);
793 val = clk_readl(c->reg); 914 val = clk_readl(c->reg);
@@ -813,13 +934,15 @@ static int tegra2_pll_div_clk_enable(struct clk *c)
813 return -EINVAL; 934 return -EINVAL;
814} 935}
815 936
816static void tegra2_pll_div_clk_disable(struct clk *c) 937static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
817{ 938{
818 u32 val; 939 struct clk_tegra *c = to_clk_tegra(hw);
819 u32 new_val;
820 unsigned long flags; 940 unsigned long flags;
941 u32 new_val;
942 u32 val;
943
944 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
821 945
822 pr_debug("%s: %s\n", __func__, c->name);
823 if (c->flags & DIV_U71) { 946 if (c->flags & DIV_U71) {
824 spin_lock_irqsave(&clock_register_lock, flags); 947 spin_lock_irqsave(&clock_register_lock, flags);
825 val = clk_readl(c->reg); 948 val = clk_readl(c->reg);
@@ -842,15 +965,17 @@ static void tegra2_pll_div_clk_disable(struct clk *c)
842 } 965 }
843} 966}
844 967
845static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) 968static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
969 unsigned long parent_rate)
846{ 970{
847 u32 val; 971 struct clk_tegra *c = to_clk_tegra(hw);
848 u32 new_val;
849 int divider_u71;
850 unsigned long parent_rate = clk_get_rate(c->parent);
851 unsigned long flags; 972 unsigned long flags;
973 int divider_u71;
974 u32 new_val;
975 u32 val;
976
977 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
852 978
853 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
854 if (c->flags & DIV_U71) { 979 if (c->flags & DIV_U71) {
855 divider_u71 = clk_div71_get_divider(parent_rate, rate); 980 divider_u71 = clk_div71_get_divider(parent_rate, rate);
856 if (divider_u71 >= 0) { 981 if (divider_u71 >= 0) {
@@ -878,11 +1003,14 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
878 return -EINVAL; 1003 return -EINVAL;
879} 1004}
880 1005
881static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate) 1006static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1007 unsigned long *prate)
882{ 1008{
1009 struct clk_tegra *c = to_clk_tegra(hw);
1010 unsigned long parent_rate = *prate;
883 int divider; 1011 int divider;
884 unsigned long parent_rate = clk_get_rate(c->parent); 1012
885 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1013 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
886 1014
887 if (c->flags & DIV_U71) { 1015 if (c->flags & DIV_U71) {
888 divider = clk_div71_get_divider(parent_rate, rate); 1016 divider = clk_div71_get_divider(parent_rate, rate);
@@ -896,60 +1024,24 @@ static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
896} 1024}
897 1025
898struct clk_ops tegra_pll_div_ops = { 1026struct clk_ops tegra_pll_div_ops = {
899 .init = tegra2_pll_div_clk_init, 1027 .is_enabled = tegra20_pll_div_clk_is_enabled,
900 .enable = tegra2_pll_div_clk_enable, 1028 .enable = tegra20_pll_div_clk_enable,
901 .disable = tegra2_pll_div_clk_disable, 1029 .disable = tegra20_pll_div_clk_disable,
902 .set_rate = tegra2_pll_div_clk_set_rate, 1030 .set_rate = tegra20_pll_div_clk_set_rate,
903 .round_rate = tegra2_pll_div_clk_round_rate, 1031 .round_rate = tegra20_pll_div_clk_round_rate,
1032 .recalc_rate = tegra20_pll_div_clk_recalc_rate,
904}; 1033};
905 1034
906/* Periph clk ops */ 1035/* Periph clk ops */
907 1036
908static void tegra2_periph_clk_init(struct clk *c) 1037static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
909{ 1038{
910 u32 val = clk_readl(c->reg); 1039 struct clk_tegra *c = to_clk_tegra(hw);
911 const struct clk_mux_sel *mux = NULL;
912 const struct clk_mux_sel *sel;
913 u32 shift;
914 u32 mask;
915
916 if (c->flags & MUX_PWM) {
917 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
918 mask = PERIPH_CLK_SOURCE_PWM_MASK;
919 } else {
920 shift = PERIPH_CLK_SOURCE_SHIFT;
921 mask = PERIPH_CLK_SOURCE_MASK;
922 }
923
924 if (c->flags & MUX) {
925 for (sel = c->inputs; sel->input != NULL; sel++) {
926 if ((val & mask) >> shift == sel->value)
927 mux = sel;
928 }
929 BUG_ON(!mux);
930
931 c->parent = mux->input;
932 } else {
933 c->parent = c->inputs[0].input;
934 }
935
936 if (c->flags & DIV_U71) {
937 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
938 c->div = divu71 + 2;
939 c->mul = 2;
940 } else if (c->flags & DIV_U16) {
941 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
942 c->div = divu16 + 1;
943 c->mul = 1;
944 } else {
945 c->div = 1;
946 c->mul = 1;
947 }
948 1040
949 c->state = ON; 1041 c->state = ON;
950 1042
951 if (!c->u.periph.clk_num) 1043 if (!c->u.periph.clk_num)
952 return; 1044 goto out;
953 1045
954 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & 1046 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
955 PERIPH_CLK_TO_ENB_BIT(c))) 1047 PERIPH_CLK_TO_ENB_BIT(c)))
@@ -959,24 +1051,27 @@ static void tegra2_periph_clk_init(struct clk *c)
959 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & 1051 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
960 PERIPH_CLK_TO_ENB_BIT(c)) 1052 PERIPH_CLK_TO_ENB_BIT(c))
961 c->state = OFF; 1053 c->state = OFF;
1054
1055out:
1056 return c->state;
962} 1057}
963 1058
964static int tegra2_periph_clk_enable(struct clk *c) 1059static int tegra20_periph_clk_enable(struct clk_hw *hw)
965{ 1060{
966 u32 val; 1061 struct clk_tegra *c = to_clk_tegra(hw);
967 unsigned long flags; 1062 unsigned long flags;
968 int refcount; 1063 u32 val;
969 pr_debug("%s on clock %s\n", __func__, c->name); 1064
1065 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
970 1066
971 if (!c->u.periph.clk_num) 1067 if (!c->u.periph.clk_num)
972 return 0; 1068 return 0;
973 1069
974 spin_lock_irqsave(&clock_register_lock, flags); 1070 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
975 1071 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
976 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; 1072 return 0;
977 1073
978 if (refcount > 1) 1074 spin_lock_irqsave(&clock_register_lock, flags);
979 goto out;
980 1075
981 clk_writel(PERIPH_CLK_TO_ENB_BIT(c), 1076 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
982 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); 1077 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
@@ -991,39 +1086,41 @@ static int tegra2_periph_clk_enable(struct clk *c)
991 clk_writel(val, c->reg); 1086 clk_writel(val, c->reg);
992 } 1087 }
993 1088
994out:
995 spin_unlock_irqrestore(&clock_register_lock, flags); 1089 spin_unlock_irqrestore(&clock_register_lock, flags);
996 1090
997 return 0; 1091 return 0;
998} 1092}
999 1093
1000static void tegra2_periph_clk_disable(struct clk *c) 1094static void tegra20_periph_clk_disable(struct clk_hw *hw)
1001{ 1095{
1096 struct clk_tegra *c = to_clk_tegra(hw);
1002 unsigned long flags; 1097 unsigned long flags;
1003 1098
1004 pr_debug("%s on clock %s\n", __func__, c->name); 1099 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1005 1100
1006 if (!c->u.periph.clk_num) 1101 if (!c->u.periph.clk_num)
1007 return; 1102 return;
1008 1103
1009 spin_lock_irqsave(&clock_register_lock, flags); 1104 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1010 1105
1011 if (c->refcnt) 1106 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1012 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; 1107 return;
1013 1108
1014 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) 1109 spin_lock_irqsave(&clock_register_lock, flags);
1015 clk_writel(PERIPH_CLK_TO_ENB_BIT(c), 1110
1016 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); 1111 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1112 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1017 1113
1018 spin_unlock_irqrestore(&clock_register_lock, flags); 1114 spin_unlock_irqrestore(&clock_register_lock, flags);
1019} 1115}
1020 1116
1021static void tegra2_periph_clk_reset(struct clk *c, bool assert) 1117void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
1022{ 1118{
1119 struct clk_tegra *c = to_clk_tegra(hw);
1023 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; 1120 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1024 1121
1025 pr_debug("%s %s on clock %s\n", __func__, 1122 pr_debug("%s %s on clock %s\n", __func__,
1026 assert ? "assert" : "deassert", c->name); 1123 assert ? "assert" : "deassert", __clk_get_name(hw->clk));
1027 1124
1028 BUG_ON(!c->u.periph.clk_num); 1125 BUG_ON(!c->u.periph.clk_num);
1029 1126
@@ -1032,13 +1129,14 @@ static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1032 base + PERIPH_CLK_TO_ENB_SET_REG(c)); 1129 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1033} 1130}
1034 1131
1035static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) 1132static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1036{ 1133{
1134 struct clk_tegra *c = to_clk_tegra(hw);
1037 u32 val; 1135 u32 val;
1038 const struct clk_mux_sel *sel; 1136 u32 mask;
1039 u32 mask, shift; 1137 u32 shift;
1040 1138
1041 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 1139 pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
1042 1140
1043 if (c->flags & MUX_PWM) { 1141 if (c->flags & MUX_PWM) {
1044 shift = PERIPH_CLK_SOURCE_PWM_SHIFT; 1142 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
@@ -1048,36 +1146,78 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1048 mask = PERIPH_CLK_SOURCE_MASK; 1146 mask = PERIPH_CLK_SOURCE_MASK;
1049 } 1147 }
1050 1148
1051 for (sel = c->inputs; sel->input != NULL; sel++) { 1149 val = clk_readl(c->reg);
1052 if (sel->input == p) { 1150 val &= ~mask;
1053 val = clk_readl(c->reg); 1151 val |= (index) << shift;
1054 val &= ~mask;
1055 val |= (sel->value) << shift;
1056 1152
1057 if (c->refcnt) 1153 clk_writel(val, c->reg);
1058 clk_enable(p);
1059 1154
1060 clk_writel(val, c->reg); 1155 return 0;
1156}
1061 1157
1062 if (c->refcnt && c->parent) 1158static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
1063 clk_disable(c->parent); 1159{
1160 struct clk_tegra *c = to_clk_tegra(hw);
1161 u32 val = clk_readl(c->reg);
1162 u32 mask;
1163 u32 shift;
1064 1164
1065 clk_reparent(c, p); 1165 if (c->flags & MUX_PWM) {
1066 return 0; 1166 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1067 } 1167 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1168 } else {
1169 shift = PERIPH_CLK_SOURCE_SHIFT;
1170 mask = PERIPH_CLK_SOURCE_MASK;
1068 } 1171 }
1069 1172
1070 return -EINVAL; 1173 if (c->flags & MUX)
1174 return (val & mask) >> shift;
1175 else
1176 return 0;
1071} 1177}
1072 1178
1073static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) 1179static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
1180 unsigned long prate)
1074{ 1181{
1182 struct clk_tegra *c = to_clk_tegra(hw);
1183 unsigned long rate = prate;
1184 u32 val = clk_readl(c->reg);
1185
1186 if (c->flags & DIV_U71) {
1187 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1188 c->div = divu71 + 2;
1189 c->mul = 2;
1190 } else if (c->flags & DIV_U16) {
1191 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1192 c->div = divu16 + 1;
1193 c->mul = 1;
1194 } else {
1195 c->div = 1;
1196 c->mul = 1;
1197 return rate;
1198 }
1199
1200 if (c->mul != 0 && c->div != 0) {
1201 rate *= c->mul;
1202 rate += c->div - 1; /* round up */
1203 do_div(rate, c->div);
1204 }
1205
1206 return rate;
1207}
1208
1209static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1210 unsigned long parent_rate)
1211{
1212 struct clk_tegra *c = to_clk_tegra(hw);
1075 u32 val; 1213 u32 val;
1076 int divider; 1214 int divider;
1077 unsigned long parent_rate = clk_get_rate(c->parent); 1215
1216 val = clk_readl(c->reg);
1078 1217
1079 if (c->flags & DIV_U71) { 1218 if (c->flags & DIV_U71) {
1080 divider = clk_div71_get_divider(parent_rate, rate); 1219 divider = clk_div71_get_divider(parent_rate, rate);
1220
1081 if (divider >= 0) { 1221 if (divider >= 0) {
1082 val = clk_readl(c->reg); 1222 val = clk_readl(c->reg);
1083 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; 1223 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
@@ -1103,15 +1243,21 @@ static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1103 c->mul = 1; 1243 c->mul = 1;
1104 return 0; 1244 return 0;
1105 } 1245 }
1246
1106 return -EINVAL; 1247 return -EINVAL;
1107} 1248}
1108 1249
1109static long tegra2_periph_clk_round_rate(struct clk *c, 1250static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
1110 unsigned long rate) 1251 unsigned long rate, unsigned long *prate)
1111{ 1252{
1253 struct clk_tegra *c = to_clk_tegra(hw);
1254 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1112 int divider; 1255 int divider;
1113 unsigned long parent_rate = clk_get_rate(c->parent); 1256
1114 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1257 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1258
1259 if (prate)
1260 parent_rate = *prate;
1115 1261
1116 if (c->flags & DIV_U71) { 1262 if (c->flags & DIV_U71) {
1117 divider = clk_div71_get_divider(parent_rate, rate); 1263 divider = clk_div71_get_divider(parent_rate, rate);
@@ -1129,44 +1275,27 @@ static long tegra2_periph_clk_round_rate(struct clk *c,
1129} 1275}
1130 1276
1131struct clk_ops tegra_periph_clk_ops = { 1277struct clk_ops tegra_periph_clk_ops = {
1132 .init = &tegra2_periph_clk_init, 1278 .is_enabled = tegra20_periph_clk_is_enabled,
1133 .enable = &tegra2_periph_clk_enable, 1279 .enable = tegra20_periph_clk_enable,
1134 .disable = &tegra2_periph_clk_disable, 1280 .disable = tegra20_periph_clk_disable,
1135 .set_parent = &tegra2_periph_clk_set_parent, 1281 .set_parent = tegra20_periph_clk_set_parent,
1136 .set_rate = &tegra2_periph_clk_set_rate, 1282 .get_parent = tegra20_periph_clk_get_parent,
1137 .round_rate = &tegra2_periph_clk_round_rate, 1283 .set_rate = tegra20_periph_clk_set_rate,
1138 .reset = &tegra2_periph_clk_reset, 1284 .round_rate = tegra20_periph_clk_round_rate,
1285 .recalc_rate = tegra20_periph_clk_recalc_rate,
1139}; 1286};
1140 1287
1141/* The SDMMC controllers have extra bits in the clock source register that
1142 * adjust the delay between the clock and data to compenstate for delays
1143 * on the PCB. */
1144void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1145{
1146 u32 reg;
1147 unsigned long flags;
1148
1149 spin_lock_irqsave(&c->spinlock, flags);
1150
1151 delay = clamp(delay, 0, 15);
1152 reg = clk_readl(c->reg);
1153 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1154 reg |= SDMMC_CLK_INT_FB_SEL;
1155 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1156 clk_writel(reg, c->reg);
1157
1158 spin_unlock_irqrestore(&c->spinlock, flags);
1159}
1160
1161/* External memory controller clock ops */ 1288/* External memory controller clock ops */
1162static void tegra2_emc_clk_init(struct clk *c) 1289static void tegra20_emc_clk_init(struct clk_hw *hw)
1163{ 1290{
1164 tegra2_periph_clk_init(c); 1291 struct clk_tegra *c = to_clk_tegra(hw);
1165 c->max_rate = clk_get_rate_locked(c); 1292 c->max_rate = __clk_get_rate(hw->clk);
1166} 1293}
1167 1294
1168static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate) 1295static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1296 unsigned long *prate)
1169{ 1297{
1298 struct clk_tegra *c = to_clk_tegra(hw);
1170 long emc_rate; 1299 long emc_rate;
1171 long clk_rate; 1300 long clk_rate;
1172 1301
@@ -1182,7 +1311,7 @@ static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1182 * The fastest rate the PLL will generate that is at most the 1311 * The fastest rate the PLL will generate that is at most the
1183 * requested rate. 1312 * requested rate.
1184 */ 1313 */
1185 clk_rate = tegra2_periph_clk_round_rate(c, emc_rate); 1314 clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
1186 1315
1187 /* 1316 /*
1188 * If this fails, and emc_rate > clk_rate, it's because the maximum 1317 * If this fails, and emc_rate > clk_rate, it's because the maximum
@@ -1198,9 +1327,11 @@ static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1198 return emc_rate; 1327 return emc_rate;
1199} 1328}
1200 1329
1201static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate) 1330static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1331 unsigned long parent_rate)
1202{ 1332{
1203 int ret; 1333 int ret;
1334
1204 /* 1335 /*
1205 * The Tegra2 memory controller has an interlock with the clock 1336 * The Tegra2 memory controller has an interlock with the clock
1206 * block that allows memory shadowed registers to be updated, 1337 * block that allows memory shadowed registers to be updated,
@@ -1211,116 +1342,145 @@ static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1211 if (ret < 0) 1342 if (ret < 0)
1212 return ret; 1343 return ret;
1213 1344
1214 ret = tegra2_periph_clk_set_rate(c, rate); 1345 ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
1215 udelay(1); 1346 udelay(1);
1216 1347
1217 return ret; 1348 return ret;
1218} 1349}
1219 1350
1220struct clk_ops tegra_emc_clk_ops = { 1351struct clk_ops tegra_emc_clk_ops = {
1221 .init = &tegra2_emc_clk_init, 1352 .init = tegra20_emc_clk_init,
1222 .enable = &tegra2_periph_clk_enable, 1353 .is_enabled = tegra20_periph_clk_is_enabled,
1223 .disable = &tegra2_periph_clk_disable, 1354 .enable = tegra20_periph_clk_enable,
1224 .set_parent = &tegra2_periph_clk_set_parent, 1355 .disable = tegra20_periph_clk_disable,
1225 .set_rate = &tegra2_emc_clk_set_rate, 1356 .set_parent = tegra20_periph_clk_set_parent,
1226 .round_rate = &tegra2_emc_clk_round_rate, 1357 .get_parent = tegra20_periph_clk_get_parent,
1227 .reset = &tegra2_periph_clk_reset, 1358 .set_rate = tegra20_emc_clk_set_rate,
1359 .round_rate = tegra20_emc_clk_round_rate,
1360 .recalc_rate = tegra20_periph_clk_recalc_rate,
1228}; 1361};
1229 1362
1230/* Clock doubler ops */ 1363/* Clock doubler ops */
1231static void tegra2_clk_double_init(struct clk *c) 1364static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
1232{ 1365{
1233 c->mul = 2; 1366 struct clk_tegra *c = to_clk_tegra(hw);
1234 c->div = 1; 1367
1235 c->state = ON; 1368 c->state = ON;
1236 1369
1237 if (!c->u.periph.clk_num) 1370 if (!c->u.periph.clk_num)
1238 return; 1371 goto out;
1239 1372
1240 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & 1373 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1241 PERIPH_CLK_TO_ENB_BIT(c))) 1374 PERIPH_CLK_TO_ENB_BIT(c)))
1242 c->state = OFF; 1375 c->state = OFF;
1376
1377out:
1378 return c->state;
1243}; 1379};
1244 1380
1245static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate) 1381static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
1382 unsigned long prate)
1246{ 1383{
1247 if (rate != 2 * clk_get_rate(c->parent)) 1384 struct clk_tegra *c = to_clk_tegra(hw);
1248 return -EINVAL; 1385 u64 rate = prate;
1386
1249 c->mul = 2; 1387 c->mul = 2;
1250 c->div = 1; 1388 c->div = 1;
1389
1390 rate *= c->mul;
1391 rate += c->div - 1; /* round up */
1392 do_div(rate, c->div);
1393
1394 return rate;
1395}
1396
1397static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
1398 unsigned long *prate)
1399{
1400 unsigned long output_rate = *prate;
1401
1402 do_div(output_rate, 2);
1403 return output_rate;
1404}
1405
1406static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
1407 unsigned long parent_rate)
1408{
1409 if (rate != 2 * parent_rate)
1410 return -EINVAL;
1251 return 0; 1411 return 0;
1252} 1412}
1253 1413
1254struct clk_ops tegra_clk_double_ops = { 1414struct clk_ops tegra_clk_double_ops = {
1255 .init = &tegra2_clk_double_init, 1415 .is_enabled = tegra20_clk_double_is_enabled,
1256 .enable = &tegra2_periph_clk_enable, 1416 .enable = tegra20_periph_clk_enable,
1257 .disable = &tegra2_periph_clk_disable, 1417 .disable = tegra20_periph_clk_disable,
1258 .set_rate = &tegra2_clk_double_set_rate, 1418 .set_rate = tegra20_clk_double_set_rate,
1419 .recalc_rate = tegra20_clk_double_recalc_rate,
1420 .round_rate = tegra20_clk_double_round_rate,
1259}; 1421};
1260 1422
1261/* Audio sync clock ops */ 1423/* Audio sync clock ops */
1262static void tegra2_audio_sync_clk_init(struct clk *c) 1424static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
1263{ 1425{
1264 int source; 1426 struct clk_tegra *c = to_clk_tegra(hw);
1265 const struct clk_mux_sel *sel;
1266 u32 val = clk_readl(c->reg); 1427 u32 val = clk_readl(c->reg);
1428
1267 c->state = (val & (1<<4)) ? OFF : ON; 1429 c->state = (val & (1<<4)) ? OFF : ON;
1268 source = val & 0xf; 1430 return c->state;
1269 for (sel = c->inputs; sel->input != NULL; sel++)
1270 if (sel->value == source)
1271 break;
1272 BUG_ON(sel->input == NULL);
1273 c->parent = sel->input;
1274} 1431}
1275 1432
1276static int tegra2_audio_sync_clk_enable(struct clk *c) 1433static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
1277{ 1434{
1435 struct clk_tegra *c = to_clk_tegra(hw);
1436
1278 clk_writel(0, c->reg); 1437 clk_writel(0, c->reg);
1279 return 0; 1438 return 0;
1280} 1439}
1281 1440
1282static void tegra2_audio_sync_clk_disable(struct clk *c) 1441static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
1283{ 1442{
1443 struct clk_tegra *c = to_clk_tegra(hw);
1284 clk_writel(1, c->reg); 1444 clk_writel(1, c->reg);
1285} 1445}
1286 1446
1287static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p) 1447static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
1288{ 1448{
1289 u32 val; 1449 struct clk_tegra *c = to_clk_tegra(hw);
1290 const struct clk_mux_sel *sel; 1450 u32 val = clk_readl(c->reg);
1291 for (sel = c->inputs; sel->input != NULL; sel++) { 1451 int source;
1292 if (sel->input == p) {
1293 val = clk_readl(c->reg);
1294 val &= ~0xf;
1295 val |= sel->value;
1296 1452
1297 if (c->refcnt) 1453 source = val & 0xf;
1298 clk_enable(p); 1454 return source;
1455}
1299 1456
1300 clk_writel(val, c->reg); 1457static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1458{
1459 struct clk_tegra *c = to_clk_tegra(hw);
1460 u32 val;
1301 1461
1302 if (c->refcnt && c->parent) 1462 val = clk_readl(c->reg);
1303 clk_disable(c->parent); 1463 val &= ~0xf;
1464 val |= index;
1304 1465
1305 clk_reparent(c, p); 1466 clk_writel(val, c->reg);
1306 return 0;
1307 }
1308 }
1309 1467
1310 return -EINVAL; 1468 return 0;
1311} 1469}
1312 1470
1313struct clk_ops tegra_audio_sync_clk_ops = { 1471struct clk_ops tegra_audio_sync_clk_ops = {
1314 .init = tegra2_audio_sync_clk_init, 1472 .is_enabled = tegra20_audio_sync_clk_is_enabled,
1315 .enable = tegra2_audio_sync_clk_enable, 1473 .enable = tegra20_audio_sync_clk_enable,
1316 .disable = tegra2_audio_sync_clk_disable, 1474 .disable = tegra20_audio_sync_clk_disable,
1317 .set_parent = tegra2_audio_sync_clk_set_parent, 1475 .set_parent = tegra20_audio_sync_clk_set_parent,
1476 .get_parent = tegra20_audio_sync_clk_get_parent,
1318}; 1477};
1319 1478
1320/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */ 1479/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1321 1480
1322static void tegra2_cdev_clk_init(struct clk *c) 1481static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
1323{ 1482{
1483 struct clk_tegra *c = to_clk_tegra(hw);
1324 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is 1484 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1325 * currently done in the pinmux code. */ 1485 * currently done in the pinmux code. */
1326 c->state = ON; 1486 c->state = ON;
@@ -1330,10 +1490,12 @@ static void tegra2_cdev_clk_init(struct clk *c)
1330 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & 1490 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1331 PERIPH_CLK_TO_ENB_BIT(c))) 1491 PERIPH_CLK_TO_ENB_BIT(c)))
1332 c->state = OFF; 1492 c->state = OFF;
1493 return c->state;
1333} 1494}
1334 1495
1335static int tegra2_cdev_clk_enable(struct clk *c) 1496static int tegra20_cdev_clk_enable(struct clk_hw *hw)
1336{ 1497{
1498 struct clk_tegra *c = to_clk_tegra(hw);
1337 BUG_ON(!c->u.periph.clk_num); 1499 BUG_ON(!c->u.periph.clk_num);
1338 1500
1339 clk_writel(PERIPH_CLK_TO_ENB_BIT(c), 1501 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
@@ -1341,118 +1503,24 @@ static int tegra2_cdev_clk_enable(struct clk *c)
1341 return 0; 1503 return 0;
1342} 1504}
1343 1505
1344static void tegra2_cdev_clk_disable(struct clk *c) 1506static void tegra20_cdev_clk_disable(struct clk_hw *hw)
1345{ 1507{
1508 struct clk_tegra *c = to_clk_tegra(hw);
1346 BUG_ON(!c->u.periph.clk_num); 1509 BUG_ON(!c->u.periph.clk_num);
1347 1510
1348 clk_writel(PERIPH_CLK_TO_ENB_BIT(c), 1511 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1349 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); 1512 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1350} 1513}
1351 1514
1352struct clk_ops tegra_cdev_clk_ops = { 1515static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
1353 .init = &tegra2_cdev_clk_init, 1516 unsigned long prate)
1354 .enable = &tegra2_cdev_clk_enable,
1355 .disable = &tegra2_cdev_clk_disable,
1356};
1357
1358/* shared bus ops */
1359/*
1360 * Some clocks may have multiple downstream users that need to request a
1361 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1362 * clock to each user. The frequency of the bus is set to the highest
1363 * enabled shared_bus_user clock, with a minimum value set by the
1364 * shared bus.
1365 */
1366static int tegra_clk_shared_bus_update(struct clk *bus)
1367{
1368 struct clk *c;
1369 unsigned long rate = bus->min_rate;
1370
1371 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1372 if (c->u.shared_bus_user.enabled)
1373 rate = max(c->u.shared_bus_user.rate, rate);
1374
1375 if (rate == clk_get_rate_locked(bus))
1376 return 0;
1377
1378 return clk_set_rate_locked(bus, rate);
1379};
1380
1381static void tegra_clk_shared_bus_init(struct clk *c)
1382{
1383 unsigned long flags;
1384
1385 c->max_rate = c->parent->max_rate;
1386 c->u.shared_bus_user.rate = c->parent->max_rate;
1387 c->state = OFF;
1388 c->set = true;
1389
1390 spin_lock_irqsave(&c->parent->spinlock, flags);
1391
1392 list_add_tail(&c->u.shared_bus_user.node,
1393 &c->parent->shared_bus_list);
1394
1395 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1396}
1397
1398static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1399{ 1517{
1400 unsigned long flags; 1518 return to_clk_tegra(hw)->fixed_rate;
1401 int ret;
1402 long new_rate = rate;
1403
1404 new_rate = clk_round_rate(c->parent, new_rate);
1405 if (new_rate < 0)
1406 return new_rate;
1407
1408 spin_lock_irqsave(&c->parent->spinlock, flags);
1409
1410 c->u.shared_bus_user.rate = new_rate;
1411 ret = tegra_clk_shared_bus_update(c->parent);
1412
1413 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1414
1415 return ret;
1416}
1417
1418static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1419{
1420 return clk_round_rate(c->parent, rate);
1421} 1519}
1422 1520
1423static int tegra_clk_shared_bus_enable(struct clk *c) 1521struct clk_ops tegra_cdev_clk_ops = {
1424{ 1522 .is_enabled = tegra20_cdev_clk_is_enabled,
1425 unsigned long flags; 1523 .enable = tegra20_cdev_clk_enable,
1426 int ret; 1524 .disable = tegra20_cdev_clk_disable,
1427 1525 .recalc_rate = tegra20_cdev_recalc_rate,
1428 spin_lock_irqsave(&c->parent->spinlock, flags);
1429
1430 c->u.shared_bus_user.enabled = true;
1431 ret = tegra_clk_shared_bus_update(c->parent);
1432
1433 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1434
1435 return ret;
1436}
1437
1438static void tegra_clk_shared_bus_disable(struct clk *c)
1439{
1440 unsigned long flags;
1441 int ret;
1442
1443 spin_lock_irqsave(&c->parent->spinlock, flags);
1444
1445 c->u.shared_bus_user.enabled = false;
1446 ret = tegra_clk_shared_bus_update(c->parent);
1447 WARN_ON_ONCE(ret);
1448
1449 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1450}
1451
1452struct clk_ops tegra_clk_shared_bus_ops = {
1453 .init = tegra_clk_shared_bus_init,
1454 .enable = tegra_clk_shared_bus_enable,
1455 .disable = tegra_clk_shared_bus_disable,
1456 .set_rate = tegra_clk_shared_bus_set_rate,
1457 .round_rate = tegra_clk_shared_bus_round_rate,
1458}; 1526};
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
index 167058c02e74..0e42ec065d4a 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -17,6 +17,7 @@
17#ifndef __MACH_TEGRA20_CLOCK_H 17#ifndef __MACH_TEGRA20_CLOCK_H
18#define __MACH_TEGRA20_CLOCK_H 18#define __MACH_TEGRA20_CLOCK_H
19 19
20extern struct clk_ops tegra_clk_32k_ops;
20extern struct clk_ops tegra_pll_ops; 21extern struct clk_ops tegra_pll_ops;
21extern struct clk_ops tegra_clk_m_ops; 22extern struct clk_ops tegra_clk_m_ops;
22extern struct clk_ops tegra_pll_div_ops; 23extern struct clk_ops tegra_pll_div_ops;
@@ -34,4 +35,7 @@ extern struct clk_ops tegra_emc_clk_ops;
34extern struct clk_ops tegra_periph_clk_ops; 35extern struct clk_ops tegra_periph_clk_ops;
35extern struct clk_ops tegra_clk_shared_bus_ops; 36extern struct clk_ops tegra_clk_shared_bus_ops;
36 37
38void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
39void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
40
37#endif 41#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 24f45ff516c3..b5c518ebd50a 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/tegra2_clocks.c 2 * arch/arm/mach-tegra/tegra2_clocks.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * Author: 7 * Author:
7 * Colin Cross <ccross@google.com> 8 * Colin Cross <ccross@google.com>
@@ -17,13 +18,13 @@
17 * 18 *
18 */ 19 */
19 20
21#include <linux/clk-private.h>
20#include <linux/kernel.h> 22#include <linux/kernel.h>
21#include <linux/module.h> 23#include <linux/module.h>
22#include <linux/list.h> 24#include <linux/list.h>
23#include <linux/spinlock.h> 25#include <linux/spinlock.h>
24#include <linux/delay.h> 26#include <linux/delay.h>
25#include <linux/io.h> 27#include <linux/io.h>
26#include <linux/clkdev.h>
27#include <linux/clk.h> 28#include <linux/clk.h>
28 29
29#include <mach/iomap.h> 30#include <mach/iomap.h>
@@ -35,13 +36,126 @@
35#include "tegra20_clocks.h" 36#include "tegra20_clocks.h"
36 37
37/* Clock definitions */ 38/* Clock definitions */
39
40#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
41 _parent_names, _parents, _parent) \
42 static struct clk tegra_##_name = { \
43 .hw = &tegra_##_name##_hw.hw, \
44 .name = #_name, \
45 .rate = _rate, \
46 .ops = _ops, \
47 .flags = _flags, \
48 .parent_names = _parent_names, \
49 .parents = _parents, \
50 .num_parents = ARRAY_SIZE(_parent_names), \
51 .parent = _parent, \
52 };
53
54static struct clk tegra_clk_32k;
55static struct clk_tegra tegra_clk_32k_hw = {
56 .hw = {
57 .clk = &tegra_clk_32k,
58 },
59 .fixed_rate = 32768,
60};
61
38static struct clk tegra_clk_32k = { 62static struct clk tegra_clk_32k = {
39 .name = "clk_32k", 63 .name = "clk_32k",
40 .rate = 32768, 64 .rate = 32768,
41 .ops = NULL, 65 .ops = &tegra_clk_32k_ops,
42 .max_rate = 32768, 66 .hw = &tegra_clk_32k_hw.hw,
67 .flags = CLK_IS_ROOT,
68};
69
70static struct clk tegra_clk_m;
71static struct clk_tegra tegra_clk_m_hw = {
72 .hw = {
73 .clk = &tegra_clk_m,
74 },
75 .flags = ENABLE_ON_INIT,
76 .reg = 0x1fc,
77 .reg_shift = 28,
78 .max_rate = 26000000,
79 .fixed_rate = 0,
80};
81
82static struct clk tegra_clk_m = {
83 .name = "clk_m",
84 .ops = &tegra_clk_m_ops,
85 .hw = &tegra_clk_m_hw.hw,
86 .flags = CLK_IS_ROOT,
43}; 87};
44 88
89#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
90 _input_max, _cf_min, _cf_max, _vco_min, \
91 _vco_max, _freq_table, _lock_delay, _ops, \
92 _fixed_rate, _parent) \
93 static const char *tegra_##_name##_parent_names[] = { \
94 #_parent, \
95 }; \
96 static struct clk *tegra_##_name##_parents[] = { \
97 &tegra_##_parent, \
98 }; \
99 static struct clk tegra_##_name; \
100 static struct clk_tegra tegra_##_name##_hw = { \
101 .hw = { \
102 .clk = &tegra_##_name, \
103 }, \
104 .flags = _flags, \
105 .reg = _reg, \
106 .max_rate = _max_rate, \
107 .u.pll = { \
108 .input_min = _input_min, \
109 .input_max = _input_max, \
110 .cf_min = _cf_min, \
111 .cf_max = _cf_max, \
112 .vco_min = _vco_min, \
113 .vco_max = _vco_max, \
114 .freq_table = _freq_table, \
115 .lock_delay = _lock_delay, \
116 .fixed_rate = _fixed_rate, \
117 }, \
118 }; \
119 static struct clk tegra_##_name = { \
120 .name = #_name, \
121 .ops = &_ops, \
122 .hw = &tegra_##_name##_hw.hw, \
123 .parent = &tegra_##_parent, \
124 .parent_names = tegra_##_name##_parent_names, \
125 .parents = tegra_##_name##_parents, \
126 .num_parents = 1, \
127 };
128
129#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
130 _max_rate, _ops, _parent, _clk_flags) \
131 static const char *tegra_##_name##_parent_names[] = { \
132 #_parent, \
133 }; \
134 static struct clk *tegra_##_name##_parents[] = { \
135 &tegra_##_parent, \
136 }; \
137 static struct clk tegra_##_name; \
138 static struct clk_tegra tegra_##_name##_hw = { \
139 .hw = { \
140 .clk = &tegra_##_name, \
141 }, \
142 .flags = _flags, \
143 .reg = _reg, \
144 .max_rate = _max_rate, \
145 .reg_shift = _reg_shift, \
146 }; \
147 static struct clk tegra_##_name = { \
148 .name = #_name, \
149 .ops = &tegra_pll_div_ops, \
150 .hw = &tegra_##_name##_hw.hw, \
151 .parent = &tegra_##_parent, \
152 .parent_names = tegra_##_name##_parent_names, \
153 .parents = tegra_##_name##_parents, \
154 .num_parents = 1, \
155 .flags = _clk_flags, \
156 };
157
158
45static struct clk_pll_freq_table tegra_pll_s_freq_table[] = { 159static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
46 {32768, 12000000, 366, 1, 1, 0}, 160 {32768, 12000000, 366, 1, 1, 0},
47 {32768, 13000000, 397, 1, 1, 0}, 161 {32768, 13000000, 397, 1, 1, 0},
@@ -50,40 +164,9 @@ static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
50 {0, 0, 0, 0, 0, 0}, 164 {0, 0, 0, 0, 0, 0},
51}; 165};
52 166
53static struct clk tegra_pll_s = { 167DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
54 .name = "pll_s", 168 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
55 .flags = PLL_ALT_MISC_REG, 169 tegra_pll_ops, 0, clk_32k);
56 .ops = &tegra_pll_ops,
57 .parent = &tegra_clk_32k,
58 .max_rate = 26000000,
59 .reg = 0xf0,
60 .u.pll = {
61 .input_min = 32768,
62 .input_max = 32768,
63 .cf_min = 0, /* FIXME */
64 .cf_max = 0, /* FIXME */
65 .vco_min = 12000000,
66 .vco_max = 26000000,
67 .freq_table = tegra_pll_s_freq_table,
68 .lock_delay = 300,
69 },
70};
71
72static struct clk_mux_sel tegra_clk_m_sel[] = {
73 { .input = &tegra_clk_32k, .value = 0},
74 { .input = &tegra_pll_s, .value = 1},
75 { NULL , 0},
76};
77
78static struct clk tegra_clk_m = {
79 .name = "clk_m",
80 .flags = ENABLE_ON_INIT,
81 .ops = &tegra_clk_m_ops,
82 .inputs = tegra_clk_m_sel,
83 .reg = 0x1fc,
84 .reg_shift = 28,
85 .max_rate = 26000000,
86};
87 170
88static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { 171static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
89 { 12000000, 600000000, 600, 12, 1, 8 }, 172 { 12000000, 600000000, 600, 12, 1, 8 },
@@ -93,34 +176,12 @@ static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
93 { 0, 0, 0, 0, 0, 0 }, 176 { 0, 0, 0, 0, 0, 0 },
94}; 177};
95 178
96static struct clk tegra_pll_c = { 179DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
97 .name = "pll_c", 180 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
98 .flags = PLL_HAS_CPCON, 181 tegra_pll_ops, 0, clk_m);
99 .ops = &tegra_pll_ops,
100 .reg = 0x80,
101 .parent = &tegra_clk_m,
102 .max_rate = 600000000,
103 .u.pll = {
104 .input_min = 2000000,
105 .input_max = 31000000,
106 .cf_min = 1000000,
107 .cf_max = 6000000,
108 .vco_min = 20000000,
109 .vco_max = 1400000000,
110 .freq_table = tegra_pll_c_freq_table,
111 .lock_delay = 300,
112 },
113};
114 182
115static struct clk tegra_pll_c_out1 = { 183DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
116 .name = "pll_c_out1", 184 tegra_pll_div_ops, pll_c, 0);
117 .ops = &tegra_pll_div_ops,
118 .flags = DIV_U71,
119 .parent = &tegra_pll_c,
120 .reg = 0x84,
121 .reg_shift = 0,
122 .max_rate = 600000000,
123};
124 185
125static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { 186static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
126 { 12000000, 666000000, 666, 12, 1, 8}, 187 { 12000000, 666000000, 666, 12, 1, 8},
@@ -134,34 +195,12 @@ static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
134 { 0, 0, 0, 0, 0, 0 }, 195 { 0, 0, 0, 0, 0, 0 },
135}; 196};
136 197
137static struct clk tegra_pll_m = { 198DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
138 .name = "pll_m", 199 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
139 .flags = PLL_HAS_CPCON, 200 tegra_pll_ops, 0, clk_m);
140 .ops = &tegra_pll_ops,
141 .reg = 0x90,
142 .parent = &tegra_clk_m,
143 .max_rate = 800000000,
144 .u.pll = {
145 .input_min = 2000000,
146 .input_max = 31000000,
147 .cf_min = 1000000,
148 .cf_max = 6000000,
149 .vco_min = 20000000,
150 .vco_max = 1200000000,
151 .freq_table = tegra_pll_m_freq_table,
152 .lock_delay = 300,
153 },
154};
155 201
156static struct clk tegra_pll_m_out1 = { 202DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
157 .name = "pll_m_out1", 203 tegra_pll_div_ops, pll_m, 0);
158 .ops = &tegra_pll_div_ops,
159 .flags = DIV_U71,
160 .parent = &tegra_pll_m,
161 .reg = 0x94,
162 .reg_shift = 0,
163 .max_rate = 600000000,
164};
165 204
166static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { 205static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
167 { 12000000, 216000000, 432, 12, 2, 8}, 206 { 12000000, 216000000, 432, 12, 2, 8},
@@ -175,64 +214,19 @@ static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
175 { 0, 0, 0, 0, 0, 0 }, 214 { 0, 0, 0, 0, 0, 0 },
176}; 215};
177 216
178static struct clk tegra_pll_p = {
179 .name = "pll_p",
180 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
181 .ops = &tegra_pll_ops,
182 .reg = 0xa0,
183 .parent = &tegra_clk_m,
184 .max_rate = 432000000,
185 .u.pll = {
186 .input_min = 2000000,
187 .input_max = 31000000,
188 .cf_min = 1000000,
189 .cf_max = 6000000,
190 .vco_min = 20000000,
191 .vco_max = 1400000000,
192 .freq_table = tegra_pll_p_freq_table,
193 .lock_delay = 300,
194 },
195};
196
197static struct clk tegra_pll_p_out1 = {
198 .name = "pll_p_out1",
199 .ops = &tegra_pll_div_ops,
200 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
201 .parent = &tegra_pll_p,
202 .reg = 0xa4,
203 .reg_shift = 0,
204 .max_rate = 432000000,
205};
206
207static struct clk tegra_pll_p_out2 = {
208 .name = "pll_p_out2",
209 .ops = &tegra_pll_div_ops,
210 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
211 .parent = &tegra_pll_p,
212 .reg = 0xa4,
213 .reg_shift = 16,
214 .max_rate = 432000000,
215};
216 217
217static struct clk tegra_pll_p_out3 = { 218DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
218 .name = "pll_p_out3", 219 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
219 .ops = &tegra_pll_div_ops, 220 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
220 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
221 .parent = &tegra_pll_p,
222 .reg = 0xa8,
223 .reg_shift = 0,
224 .max_rate = 432000000,
225};
226 221
227static struct clk tegra_pll_p_out4 = { 222DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
228 .name = "pll_p_out4", 223 432000000, tegra_pll_div_ops, pll_p, 0);
229 .ops = &tegra_pll_div_ops, 224DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
230 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 225 432000000, tegra_pll_div_ops, pll_p, 0);
231 .parent = &tegra_pll_p, 226DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
232 .reg = 0xa8, 227 432000000, tegra_pll_div_ops, pll_p, 0);
233 .reg_shift = 16, 228DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
234 .max_rate = 432000000, 229 432000000, tegra_pll_div_ops, pll_p, 0);
235};
236 230
237static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { 231static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
238 { 28800000, 56448000, 49, 25, 1, 1}, 232 { 28800000, 56448000, 49, 25, 1, 1},
@@ -241,34 +235,12 @@ static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
241 { 0, 0, 0, 0, 0, 0 }, 235 { 0, 0, 0, 0, 0, 0 },
242}; 236};
243 237
244static struct clk tegra_pll_a = { 238DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
245 .name = "pll_a", 239 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
246 .flags = PLL_HAS_CPCON, 240 tegra_pll_ops, 0, pll_p_out1);
247 .ops = &tegra_pll_ops,
248 .reg = 0xb0,
249 .parent = &tegra_pll_p_out1,
250 .max_rate = 73728000,
251 .u.pll = {
252 .input_min = 2000000,
253 .input_max = 31000000,
254 .cf_min = 1000000,
255 .cf_max = 6000000,
256 .vco_min = 20000000,
257 .vco_max = 1400000000,
258 .freq_table = tegra_pll_a_freq_table,
259 .lock_delay = 300,
260 },
261};
262 241
263static struct clk tegra_pll_a_out0 = { 242DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
264 .name = "pll_a_out0", 243 tegra_pll_div_ops, pll_a, 0);
265 .ops = &tegra_pll_div_ops,
266 .flags = DIV_U71,
267 .parent = &tegra_pll_a,
268 .reg = 0xb4,
269 .reg_shift = 0,
270 .max_rate = 73728000,
271};
272 244
273static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { 245static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
274 { 12000000, 216000000, 216, 12, 1, 4}, 246 { 12000000, 216000000, 216, 12, 1, 4},
@@ -289,32 +261,12 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
289 { 0, 0, 0, 0, 0, 0 }, 261 { 0, 0, 0, 0, 0, 0 },
290}; 262};
291 263
292static struct clk tegra_pll_d = { 264DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
293 .name = "pll_d", 265 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
294 .flags = PLL_HAS_CPCON | PLLD, 266 1000, tegra_pll_ops, 0, clk_m);
295 .ops = &tegra_pll_ops,
296 .reg = 0xd0,
297 .parent = &tegra_clk_m,
298 .max_rate = 1000000000,
299 .u.pll = {
300 .input_min = 2000000,
301 .input_max = 40000000,
302 .cf_min = 1000000,
303 .cf_max = 6000000,
304 .vco_min = 40000000,
305 .vco_max = 1000000000,
306 .freq_table = tegra_pll_d_freq_table,
307 .lock_delay = 1000,
308 },
309};
310 267
311static struct clk tegra_pll_d_out0 = { 268DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
312 .name = "pll_d_out0", 269 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
313 .ops = &tegra_pll_div_ops,
314 .flags = DIV_2 | PLLD,
315 .parent = &tegra_pll_d,
316 .max_rate = 500000000,
317};
318 270
319static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { 271static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
320 { 12000000, 480000000, 960, 12, 2, 0}, 272 { 12000000, 480000000, 960, 12, 2, 0},
@@ -324,24 +276,9 @@ static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
324 { 0, 0, 0, 0, 0, 0 }, 276 { 0, 0, 0, 0, 0, 0 },
325}; 277};
326 278
327static struct clk tegra_pll_u = { 279DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
328 .name = "pll_u", 280 48000000, 960000000, tegra_pll_u_freq_table, 1000,
329 .flags = PLLU, 281 tegra_pll_ops, 0, clk_m);
330 .ops = &tegra_pll_ops,
331 .reg = 0xc0,
332 .parent = &tegra_clk_m,
333 .max_rate = 480000000,
334 .u.pll = {
335 .input_min = 2000000,
336 .input_max = 40000000,
337 .cf_min = 1000000,
338 .cf_max = 6000000,
339 .vco_min = 480000000,
340 .vco_max = 960000000,
341 .freq_table = tegra_pll_u_freq_table,
342 .lock_delay = 1000,
343 },
344};
345 282
346static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { 283static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
347 /* 1 GHz */ 284 /* 1 GHz */
@@ -395,78 +332,84 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
395 { 0, 0, 0, 0, 0, 0 }, 332 { 0, 0, 0, 0, 0, 0 },
396}; 333};
397 334
398static struct clk tegra_pll_x = { 335DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
399 .name = "pll_x", 336 31000000, 1000000, 6000000, 20000000, 1200000000,
400 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, 337 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
401 .ops = &tegra_pllx_ops,
402 .reg = 0xe0,
403 .parent = &tegra_clk_m,
404 .max_rate = 1000000000,
405 .u.pll = {
406 .input_min = 2000000,
407 .input_max = 31000000,
408 .cf_min = 1000000,
409 .cf_max = 6000000,
410 .vco_min = 20000000,
411 .vco_max = 1200000000,
412 .freq_table = tegra_pll_x_freq_table,
413 .lock_delay = 300,
414 },
415};
416 338
417static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { 339static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
418 { 12000000, 100000000, 200, 24, 1, 0 }, 340 { 12000000, 100000000, 200, 24, 1, 0 },
419 { 0, 0, 0, 0, 0, 0 }, 341 { 0, 0, 0, 0, 0, 0 },
420}; 342};
421 343
422static struct clk tegra_pll_e = { 344DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
423 .name = "pll_e", 345 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
424 .flags = PLL_ALT_MISC_REG, 346
425 .ops = &tegra_plle_ops, 347static const char *tegra_common_parent_names[] = {
426 .parent = &tegra_clk_m, 348 "clk_m",
427 .reg = 0xe8,
428 .max_rate = 100000000,
429 .u.pll = {
430 .input_min = 12000000,
431 .input_max = 12000000,
432 .freq_table = tegra_pll_e_freq_table,
433 },
434}; 349};
435 350
436static struct clk tegra_clk_d = { 351static struct clk *tegra_common_parents[] = {
437 .name = "clk_d", 352 &tegra_clk_m,
438 .flags = PERIPH_NO_RESET, 353};
439 .ops = &tegra_clk_double_ops, 354
440 .reg = 0x34, 355static struct clk tegra_clk_d;
356static struct clk_tegra tegra_clk_d_hw = {
357 .hw = {
358 .clk = &tegra_clk_d,
359 },
360 .flags = PERIPH_NO_RESET,
361 .reg = 0x34,
441 .reg_shift = 12, 362 .reg_shift = 12,
442 .parent = &tegra_clk_m, 363 .max_rate = 52000000,
443 .max_rate = 52000000, 364 .u.periph = {
444 .u.periph = {
445 .clk_num = 90, 365 .clk_num = 90,
446 }, 366 },
447}; 367};
448 368
449/* dap_mclk1, belongs to the cdev1 pingroup. */ 369static struct clk tegra_clk_d = {
450static struct clk tegra_clk_cdev1 = { 370 .name = "clk_d",
451 .name = "cdev1", 371 .hw = &tegra_clk_d_hw.hw,
452 .ops = &tegra_cdev_clk_ops, 372 .ops = &tegra_clk_double_ops,
453 .rate = 26000000, 373 .parent = &tegra_clk_m,
454 .max_rate = 26000000, 374 .parent_names = tegra_common_parent_names,
455 .u.periph = { 375 .parents = tegra_common_parents,
376 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
377};
378
379static struct clk tegra_cdev1;
380static struct clk_tegra tegra_cdev1_hw = {
381 .hw = {
382 .clk = &tegra_cdev1,
383 },
384 .fixed_rate = 26000000,
385 .u.periph = {
456 .clk_num = 94, 386 .clk_num = 94,
457 }, 387 },
458}; 388};
389static struct clk tegra_cdev1 = {
390 .name = "cdev1",
391 .hw = &tegra_cdev1_hw.hw,
392 .ops = &tegra_cdev_clk_ops,
393 .flags = CLK_IS_ROOT,
394};
459 395
460/* dap_mclk2, belongs to the cdev2 pingroup. */ 396/* dap_mclk2, belongs to the cdev2 pingroup. */
461static struct clk tegra_clk_cdev2 = { 397static struct clk tegra_cdev2;
462 .name = "cdev2", 398static struct clk_tegra tegra_cdev2_hw = {
463 .ops = &tegra_cdev_clk_ops, 399 .hw = {
464 .rate = 26000000, 400 .clk = &tegra_cdev2,
465 .max_rate = 26000000, 401 },
466 .u.periph = { 402 .fixed_rate = 26000000,
467 .clk_num = 93, 403 .u.periph = {
404 .clk_num = 93,
468 }, 405 },
469}; 406};
407static struct clk tegra_cdev2 = {
408 .name = "cdev2",
409 .hw = &tegra_cdev2_hw.hw,
410 .ops = &tegra_cdev_clk_ops,
411 .flags = CLK_IS_ROOT,
412};
470 413
471/* initialized before peripheral clocks */ 414/* initialized before peripheral clocks */
472static struct clk_mux_sel mux_audio_sync_clk[8+1]; 415static struct clk_mux_sel mux_audio_sync_clk[8+1];
@@ -487,30 +430,66 @@ static const struct audio_sources {
487 { NULL, 0 } 430 { NULL, 0 }
488}; 431};
489 432
490static struct clk tegra_clk_audio = { 433static const char *audio_parent_names[] = {
491 .name = "audio", 434 "spdif_in",
492 .inputs = mux_audio_sync_clk, 435 "i2s1",
493 .reg = 0x38, 436 "i2s2",
494 .max_rate = 73728000, 437 "dummy",
495 .ops = &tegra_audio_sync_clk_ops 438 "pll_a_out0",
439 "dummy",
440 "dummy",
441 "dummy",
442};
443
444static struct clk *audio_parents[] = {
445 NULL,
446 NULL,
447 NULL,
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453};
454
455static struct clk tegra_audio;
456static struct clk_tegra tegra_audio_hw = {
457 .hw = {
458 .clk = &tegra_audio,
459 },
460 .reg = 0x38,
461 .max_rate = 73728000,
462};
463DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
464 audio_parents, NULL);
465
466static const char *audio_2x_parent_names[] = {
467 "audio",
496}; 468};
497 469
498static struct clk tegra_clk_audio_2x = { 470static struct clk *audio_2x_parents[] = {
499 .name = "audio_2x", 471 &tegra_audio,
500 .flags = PERIPH_NO_RESET, 472};
501 .max_rate = 48000000, 473
502 .ops = &tegra_clk_double_ops, 474static struct clk tegra_audio_2x;
503 .reg = 0x34, 475static struct clk_tegra tegra_audio_2x_hw = {
476 .hw = {
477 .clk = &tegra_audio_2x,
478 },
479 .flags = PERIPH_NO_RESET,
480 .max_rate = 48000000,
481 .reg = 0x34,
504 .reg_shift = 8, 482 .reg_shift = 8,
505 .parent = &tegra_clk_audio,
506 .u.periph = { 483 .u.periph = {
507 .clk_num = 89, 484 .clk_num = 89,
508 }, 485 },
509}; 486};
487DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
488 audio_2x_parents, &tegra_audio);
510 489
511static struct clk_lookup tegra_audio_clk_lookups[] = { 490static struct clk_lookup tegra_audio_clk_lookups[] = {
512 { .con_id = "audio", .clk = &tegra_clk_audio }, 491 { .con_id = "audio", .clk = &tegra_audio },
513 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x } 492 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
514}; 493};
515 494
516/* This is called after peripheral clocks are initialized, as the 495/* This is called after peripheral clocks are initialized, as the
@@ -529,315 +508,501 @@ static void init_audio_sync_clock_mux(void)
529 if (!sel->input) 508 if (!sel->input)
530 pr_err("%s: could not find clk %s\n", __func__, 509 pr_err("%s: could not find clk %s\n", __func__,
531 src->name); 510 src->name);
511 audio_parents[src->value] = sel->input;
532 sel->value = src->value; 512 sel->value = src->value;
533 } 513 }
534 514
535 lookup = tegra_audio_clk_lookups; 515 lookup = tegra_audio_clk_lookups;
536 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) { 516 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
537 clk_init(lookup->clk); 517 struct clk *c = lookup->clk;
538 clkdev_add(lookup); 518 struct clk_tegra *clk = to_clk_tegra(c->hw);
519 __clk_init(NULL, c);
520 INIT_LIST_HEAD(&clk->shared_bus_list);
521 clk->lookup.con_id = lookup->con_id;
522 clk->lookup.clk = c;
523 clkdev_add(&clk->lookup);
524 tegra_clk_add(c);
539 } 525 }
540} 526}
541 527
542static struct clk_mux_sel mux_cclk[] = { 528static const char *mux_cclk[] = {
543 { .input = &tegra_clk_m, .value = 0}, 529 "clk_m",
544 { .input = &tegra_pll_c, .value = 1}, 530 "pll_c",
545 { .input = &tegra_clk_32k, .value = 2}, 531 "clk_32k",
546 { .input = &tegra_pll_m, .value = 3}, 532 "pll_m",
547 { .input = &tegra_pll_p, .value = 4}, 533 "pll_p",
548 { .input = &tegra_pll_p_out4, .value = 5}, 534 "pll_p_out4",
549 { .input = &tegra_pll_p_out3, .value = 6}, 535 "pll_p_out3",
550 { .input = &tegra_clk_d, .value = 7}, 536 "clk_d",
551 { .input = &tegra_pll_x, .value = 8}, 537 "pll_x",
552 { NULL, 0}, 538};
553}; 539
554 540
555static struct clk_mux_sel mux_sclk[] = { 541static struct clk *mux_cclk_p[] = {
556 { .input = &tegra_clk_m, .value = 0}, 542 &tegra_clk_m,
557 { .input = &tegra_pll_c_out1, .value = 1}, 543 &tegra_pll_c,
558 { .input = &tegra_pll_p_out4, .value = 2}, 544 &tegra_clk_32k,
559 { .input = &tegra_pll_p_out3, .value = 3}, 545 &tegra_pll_m,
560 { .input = &tegra_pll_p_out2, .value = 4}, 546 &tegra_pll_p,
561 { .input = &tegra_clk_d, .value = 5}, 547 &tegra_pll_p_out4,
562 { .input = &tegra_clk_32k, .value = 6}, 548 &tegra_pll_p_out3,
563 { .input = &tegra_pll_m_out1, .value = 7}, 549 &tegra_clk_d,
564 { NULL, 0}, 550 &tegra_pll_x,
565}; 551};
566 552
567static struct clk tegra_clk_cclk = { 553static const char *mux_sclk[] = {
568 .name = "cclk", 554 "clk_m",
569 .inputs = mux_cclk, 555 "pll_c_out1",
570 .reg = 0x20, 556 "pll_p_out4",
571 .ops = &tegra_super_ops, 557 "pllp_p_out3",
558 "pll_p_out2",
559 "clk_d",
560 "clk_32k",
561 "pll_m_out1",
562};
563
564static struct clk *mux_sclk_p[] = {
565 &tegra_clk_m,
566 &tegra_pll_c_out1,
567 &tegra_pll_p_out4,
568 &tegra_pll_p_out3,
569 &tegra_pll_p_out2,
570 &tegra_clk_d,
571 &tegra_clk_32k,
572 &tegra_pll_m_out1,
573};
574
575static struct clk tegra_cclk;
576static struct clk_tegra tegra_cclk_hw = {
577 .hw = {
578 .clk = &tegra_cclk,
579 },
580 .reg = 0x20,
572 .max_rate = 1000000000, 581 .max_rate = 1000000000,
573}; 582};
583DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
584 mux_cclk_p, NULL);
574 585
575static struct clk tegra_clk_sclk = { 586static struct clk tegra_sclk;
576 .name = "sclk", 587static struct clk_tegra tegra_sclk_hw = {
577 .inputs = mux_sclk, 588 .hw = {
578 .reg = 0x28, 589 .clk = &tegra_sclk,
579 .ops = &tegra_super_ops, 590 },
591 .reg = 0x28,
580 .max_rate = 240000000, 592 .max_rate = 240000000,
581 .min_rate = 120000000, 593 .min_rate = 120000000,
582}; 594};
595DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
596 mux_sclk_p, NULL);
583 597
584static struct clk tegra_clk_virtual_cpu = { 598static const char *tegra_cop_parent_names[] = {
585 .name = "cpu", 599 "tegra_sclk",
586 .parent = &tegra_clk_cclk, 600};
587 .ops = &tegra_cpu_ops, 601
588 .max_rate = 1000000000, 602static struct clk *tegra_cop_parents[] = {
589 .u.cpu = { 603 &tegra_sclk,
590 .main = &tegra_pll_x,
591 .backup = &tegra_pll_p,
592 },
593}; 604};
594 605
595static struct clk tegra_clk_cop = { 606static struct clk tegra_cop;
596 .name = "cop", 607static struct clk_tegra tegra_cop_hw = {
597 .parent = &tegra_clk_sclk, 608 .hw = {
598 .ops = &tegra_cop_ops, 609 .clk = &tegra_cop,
610 },
599 .max_rate = 240000000, 611 .max_rate = 240000000,
612 .reset = &tegra2_cop_clk_reset,
613};
614DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
615 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
616
617static const char *tegra_hclk_parent_names[] = {
618 "tegra_sclk",
619};
620
621static struct clk *tegra_hclk_parents[] = {
622 &tegra_sclk,
600}; 623};
601 624
602static struct clk tegra_clk_hclk = { 625static struct clk tegra_hclk;
603 .name = "hclk", 626static struct clk_tegra tegra_hclk_hw = {
604 .flags = DIV_BUS, 627 .hw = {
605 .parent = &tegra_clk_sclk, 628 .clk = &tegra_hclk,
606 .reg = 0x30, 629 },
607 .reg_shift = 4, 630 .flags = DIV_BUS,
608 .ops = &tegra_bus_ops, 631 .reg = 0x30,
609 .max_rate = 240000000, 632 .reg_shift = 4,
633 .max_rate = 240000000,
634};
635DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
636 tegra_hclk_parents, &tegra_sclk);
637
638static const char *tegra_pclk_parent_names[] = {
639 "tegra_hclk",
610}; 640};
611 641
612static struct clk tegra_clk_pclk = { 642static struct clk *tegra_pclk_parents[] = {
613 .name = "pclk", 643 &tegra_hclk,
614 .flags = DIV_BUS,
615 .parent = &tegra_clk_hclk,
616 .reg = 0x30,
617 .reg_shift = 0,
618 .ops = &tegra_bus_ops,
619 .max_rate = 120000000,
620}; 644};
621 645
622static struct clk tegra_clk_blink = { 646static struct clk tegra_pclk;
623 .name = "blink", 647static struct clk_tegra tegra_pclk_hw = {
624 .parent = &tegra_clk_32k, 648 .hw = {
625 .reg = 0x40, 649 .clk = &tegra_pclk,
626 .ops = &tegra_blink_clk_ops, 650 },
627 .max_rate = 32768, 651 .flags = DIV_BUS,
652 .reg = 0x30,
653 .reg_shift = 0,
654 .max_rate = 120000000,
628}; 655};
656DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
657 tegra_pclk_parents, &tegra_hclk);
629 658
630static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { 659static const char *tegra_blink_parent_names[] = {
631 { .input = &tegra_pll_m, .value = 0}, 660 "clk_32k",
632 { .input = &tegra_pll_c, .value = 1},
633 { .input = &tegra_pll_p, .value = 2},
634 { .input = &tegra_pll_a_out0, .value = 3},
635 { NULL, 0},
636}; 661};
637 662
638static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { 663static struct clk *tegra_blink_parents[] = {
639 { .input = &tegra_pll_m, .value = 0}, 664 &tegra_clk_32k,
640 { .input = &tegra_pll_c, .value = 1},
641 { .input = &tegra_pll_p, .value = 2},
642 { .input = &tegra_clk_m, .value = 3},
643 { NULL, 0},
644}; 665};
645 666
646static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { 667static struct clk tegra_blink;
647 { .input = &tegra_pll_p, .value = 0}, 668static struct clk_tegra tegra_blink_hw = {
648 { .input = &tegra_pll_c, .value = 1}, 669 .hw = {
649 { .input = &tegra_pll_m, .value = 2}, 670 .clk = &tegra_blink,
650 { .input = &tegra_clk_m, .value = 3}, 671 },
651 { NULL, 0}, 672 .reg = 0x40,
673 .max_rate = 32768,
674};
675DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
676 tegra_blink_parents, &tegra_clk_32k);
677
678static const char *mux_pllm_pllc_pllp_plla[] = {
679 "pll_m",
680 "pll_c",
681 "pll_p",
682 "pll_a_out0",
652}; 683};
653 684
654static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = { 685static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
655 {.input = &tegra_pll_a_out0, .value = 0}, 686 &tegra_pll_m,
656 {.input = &tegra_clk_audio_2x, .value = 1}, 687 &tegra_pll_c,
657 {.input = &tegra_pll_p, .value = 2}, 688 &tegra_pll_p,
658 {.input = &tegra_clk_m, .value = 3}, 689 &tegra_pll_a_out0,
659 { NULL, 0},
660}; 690};
661 691
662static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { 692static const char *mux_pllm_pllc_pllp_clkm[] = {
663 {.input = &tegra_pll_p, .value = 0}, 693 "pll_m",
664 {.input = &tegra_pll_d_out0, .value = 1}, 694 "pll_c",
665 {.input = &tegra_pll_c, .value = 2}, 695 "pll_p",
666 {.input = &tegra_clk_m, .value = 3}, 696 "clk_m",
667 { NULL, 0},
668}; 697};
669 698
670static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { 699static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
671 {.input = &tegra_pll_p, .value = 0}, 700 &tegra_pll_m,
672 {.input = &tegra_pll_c, .value = 1}, 701 &tegra_pll_c,
673 {.input = &tegra_clk_audio, .value = 2}, 702 &tegra_pll_p,
674 {.input = &tegra_clk_m, .value = 3}, 703 &tegra_clk_m,
675 {.input = &tegra_clk_32k, .value = 4},
676 { NULL, 0},
677}; 704};
678 705
679static struct clk_mux_sel mux_pllp_pllc_pllm[] = { 706static const char *mux_pllp_pllc_pllm_clkm[] = {
680 {.input = &tegra_pll_p, .value = 0}, 707 "pll_p",
681 {.input = &tegra_pll_c, .value = 1}, 708 "pll_c",
682 {.input = &tegra_pll_m, .value = 2}, 709 "pll_m",
683 { NULL, 0}, 710 "clk_m",
684}; 711};
685 712
686static struct clk_mux_sel mux_clk_m[] = { 713static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
687 { .input = &tegra_clk_m, .value = 0}, 714 &tegra_pll_p,
688 { NULL, 0}, 715 &tegra_pll_c,
716 &tegra_pll_m,
717 &tegra_clk_m,
689}; 718};
690 719
691static struct clk_mux_sel mux_pllp_out3[] = { 720static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
692 { .input = &tegra_pll_p_out3, .value = 0}, 721 "pll_a_out0",
693 { NULL, 0}, 722 "audio_2x",
723 "pll_p",
724 "clk_m",
694}; 725};
695 726
696static struct clk_mux_sel mux_plld[] = { 727static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
697 { .input = &tegra_pll_d, .value = 0}, 728 &tegra_pll_a_out0,
698 { NULL, 0}, 729 &tegra_audio_2x,
730 &tegra_pll_p,
731 &tegra_clk_m,
699}; 732};
700 733
701static struct clk_mux_sel mux_clk_32k[] = { 734static const char *mux_pllp_plld_pllc_clkm[] = {
702 { .input = &tegra_clk_32k, .value = 0}, 735 "pllp",
703 { NULL, 0}, 736 "pll_d_out0",
737 "pll_c",
738 "clk_m",
704}; 739};
705 740
706static struct clk_mux_sel mux_pclk[] = { 741static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
707 { .input = &tegra_clk_pclk, .value = 0}, 742 &tegra_pll_p,
708 { NULL, 0}, 743 &tegra_pll_d_out0,
744 &tegra_pll_c,
745 &tegra_clk_m,
709}; 746};
710 747
711static struct clk tegra_clk_emc = { 748static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
712 .name = "emc", 749 "pll_p",
713 .ops = &tegra_emc_clk_ops, 750 "pll_c",
751 "audio",
752 "clk_m",
753 "clk_32k",
754};
755
756static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
757 &tegra_pll_p,
758 &tegra_pll_c,
759 &tegra_audio,
760 &tegra_clk_m,
761 &tegra_clk_32k,
762};
763
764static const char *mux_pllp_pllc_pllm[] = {
765 "pll_p",
766 "pll_c",
767 "pll_m"
768};
769
770static struct clk *mux_pllp_pllc_pllm_p[] = {
771 &tegra_pll_p,
772 &tegra_pll_c,
773 &tegra_pll_m,
774};
775
776static const char *mux_clk_m[] = {
777 "clk_m",
778};
779
780static struct clk *mux_clk_m_p[] = {
781 &tegra_clk_m,
782};
783
784static const char *mux_pllp_out3[] = {
785 "pll_p_out3",
786};
787
788static struct clk *mux_pllp_out3_p[] = {
789 &tegra_pll_p_out3,
790};
791
792static const char *mux_plld[] = {
793 "pll_d",
794};
795
796static struct clk *mux_plld_p[] = {
797 &tegra_pll_d,
798};
799
800static const char *mux_clk_32k[] = {
801 "clk_32k",
802};
803
804static struct clk *mux_clk_32k_p[] = {
805 &tegra_clk_32k,
806};
807
808static const char *mux_pclk[] = {
809 "pclk",
810};
811
812static struct clk *mux_pclk_p[] = {
813 &tegra_pclk,
814};
815
816static struct clk tegra_emc;
817static struct clk_tegra tegra_emc_hw = {
818 .hw = {
819 .clk = &tegra_emc,
820 },
714 .reg = 0x19c, 821 .reg = 0x19c,
715 .max_rate = 800000000, 822 .max_rate = 800000000,
716 .inputs = mux_pllm_pllc_pllp_clkm,
717 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, 823 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
824 .reset = &tegra2_periph_clk_reset,
718 .u.periph = { 825 .u.periph = {
719 .clk_num = 57, 826 .clk_num = 57,
720 }, 827 },
721}; 828};
722 829DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
723#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ 830 mux_pllm_pllc_pllp_clkm_p, NULL);
724 { \ 831
725 .name = _name, \ 832#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
726 .lookup = { \ 833 _max, _inputs, _flags) \
727 .dev_id = _dev, \ 834 static struct clk tegra_##_name; \
728 .con_id = _con, \ 835 static struct clk_tegra tegra_##_name##_hw = { \
836 .hw = { \
837 .clk = &tegra_##_name, \
729 }, \ 838 }, \
730 .ops = &tegra_periph_clk_ops, \ 839 .lookup = { \
731 .reg = _reg, \ 840 .dev_id = _dev, \
732 .inputs = _inputs, \ 841 .con_id = _con, \
733 .flags = _flags, \
734 .max_rate = _max, \
735 .u.periph = { \
736 .clk_num = _clk_num, \
737 }, \ 842 }, \
738 } 843 .reg = _reg, \
739 844 .flags = _flags, \
740#define SHARED_CLK(_name, _dev, _con, _parent) \ 845 .max_rate = _max, \
741 { \ 846 .u.periph = { \
742 .name = _name, \ 847 .clk_num = _clk_num, \
743 .lookup = { \
744 .dev_id = _dev, \
745 .con_id = _con, \
746 }, \ 848 }, \
747 .ops = &tegra_clk_shared_bus_ops, \ 849 .reset = tegra2_periph_clk_reset, \
748 .parent = _parent, \ 850 }; \
749 } 851 static struct clk tegra_##_name = { \
852 .name = #_name, \
853 .ops = &tegra_periph_clk_ops, \
854 .hw = &tegra_##_name##_hw.hw, \
855 .parent_names = _inputs, \
856 .parents = _inputs##_p, \
857 .num_parents = ARRAY_SIZE(_inputs), \
858 };
859
860PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
861PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
862PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
863PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
864PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
865PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
866PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
867PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
868PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
869PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
870PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
871PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
872PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
873PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
874PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
875PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
876PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
877PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
878PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
879PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
880PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
881PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
882PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
883PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
884PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
885PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
886PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
887/* FIXME: what is la? */
888PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
889PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
890PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
891PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
892PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
893PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
894PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
895PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
896PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
897PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
898PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
899PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
900PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
901PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
902PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
903PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
904PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
905PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
906PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
907PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
908PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
909PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
910PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
911PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
912PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
913PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
914PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
915PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
916PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
917PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
918PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
919PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
920PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
921PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
922PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
923PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
924PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
925PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
926PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
927PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
928
929static struct clk *tegra_list_clks[] = {
930 &tegra_apbdma,
931 &tegra_rtc,
932 &tegra_timer,
933 &tegra_i2s1,
934 &tegra_i2s2,
935 &tegra_spdif_out,
936 &tegra_spdif_in,
937 &tegra_pwm,
938 &tegra_spi,
939 &tegra_xio,
940 &tegra_twc,
941 &tegra_sbc1,
942 &tegra_sbc2,
943 &tegra_sbc3,
944 &tegra_sbc4,
945 &tegra_ide,
946 &tegra_ndflash,
947 &tegra_vfir,
948 &tegra_sdmmc1,
949 &tegra_sdmmc2,
950 &tegra_sdmmc3,
951 &tegra_sdmmc4,
952 &tegra_vcp,
953 &tegra_bsea,
954 &tegra_bsev,
955 &tegra_vde,
956 &tegra_csite,
957 &tegra_la,
958 &tegra_owr,
959 &tegra_nor,
960 &tegra_mipi,
961 &tegra_i2c1,
962 &tegra_i2c2,
963 &tegra_i2c3,
964 &tegra_dvc,
965 &tegra_i2c1_i2c,
966 &tegra_i2c2_i2c,
967 &tegra_i2c3_i2c,
968 &tegra_dvc_i2c,
969 &tegra_uarta,
970 &tegra_uartb,
971 &tegra_uartc,
972 &tegra_uartd,
973 &tegra_uarte,
974 &tegra_3d,
975 &tegra_2d,
976 &tegra_vi,
977 &tegra_vi_sensor,
978 &tegra_epp,
979 &tegra_mpe,
980 &tegra_host1x,
981 &tegra_cve,
982 &tegra_tvo,
983 &tegra_hdmi,
984 &tegra_tvdac,
985 &tegra_disp1,
986 &tegra_disp2,
987 &tegra_usbd,
988 &tegra_usb2,
989 &tegra_usb3,
990 &tegra_dsi,
991 &tegra_csi,
992 &tegra_isp,
993 &tegra_csus,
994 &tegra_pex,
995 &tegra_afi,
996 &tegra_pcie_xclk,
997};
750 998
751static struct clk tegra_list_clks[] = { 999#define CLK_DUPLICATE(_name, _dev, _con) \
752 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0), 1000 { \
753 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), 1001 .name = _name, \
754 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), 1002 .lookup = { \
755 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 1003 .dev_id = _dev, \
756 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 1004 .con_id = _con, \
757 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 1005 }, \
758 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
759 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
760 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
761 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
762 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
763 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
764 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
765 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
766 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
767 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
768 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
769 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
770 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
771 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
772 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
773 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
774 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
775 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
776 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
777 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
778 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
779 /* FIXME: what is la? */
780 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
781 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
782 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
783 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
784 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
785 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
786 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
787 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
788 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
789 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
790 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
791 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
792 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
793 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
794 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
795 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
796 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
797 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
798 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
799 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
800 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
801 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
802 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
803 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
804 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
805 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
806 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
807 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
808 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
809 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
810 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
811 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
812 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
813 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
814 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
815 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
816 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
817 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
818 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
819 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
820
821 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
822 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
823 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
824 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
825 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
826 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
827 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
828 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
829 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
830 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
831 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
832};
833
834#define CLK_DUPLICATE(_name, _dev, _con) \
835 { \
836 .name = _name, \
837 .lookup = { \
838 .dev_id = _dev, \
839 .con_id = _con, \
840 }, \
841 } 1006 }
842 1007
843/* Some clocks may be used by different drivers depending on the board 1008/* Some clocks may be used by different drivers depending on the board
@@ -850,25 +1015,26 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
850 CLK_DUPLICATE("uartc", "serial8250.2", NULL), 1015 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
851 CLK_DUPLICATE("uartd", "serial8250.3", NULL), 1016 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
852 CLK_DUPLICATE("uarte", "serial8250.4", NULL), 1017 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
853 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 1018 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
854 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 1019 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
855 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 1020 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
856 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), 1021 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
857 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), 1022 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
858 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), 1023 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
859 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), 1024 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
860 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), 1025 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
861 CLK_DUPLICATE("epp", "tegra_grhost", "epp"), 1026 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
862 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"), 1027 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
863 CLK_DUPLICATE("cop", "tegra-avp", "cop"), 1028 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
864 CLK_DUPLICATE("vde", "tegra-aes", "vde"), 1029 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1030 CLK_DUPLICATE("cclk", NULL, "cpu"),
865}; 1031};
866 1032
867#define CLK(dev, con, ck) \ 1033#define CLK(dev, con, ck) \
868 { \ 1034 { \
869 .dev_id = dev, \ 1035 .dev_id = dev, \
870 .con_id = con, \ 1036 .con_id = con, \
871 .clk = ck, \ 1037 .clk = ck, \
872 } 1038 }
873 1039
874static struct clk *tegra_ptr_clks[] = { 1040static struct clk *tegra_ptr_clks[] = {
@@ -891,27 +1057,33 @@ static struct clk *tegra_ptr_clks[] = {
891 &tegra_pll_u, 1057 &tegra_pll_u,
892 &tegra_pll_x, 1058 &tegra_pll_x,
893 &tegra_pll_e, 1059 &tegra_pll_e,
894 &tegra_clk_cclk, 1060 &tegra_cclk,
895 &tegra_clk_sclk, 1061 &tegra_sclk,
896 &tegra_clk_hclk, 1062 &tegra_hclk,
897 &tegra_clk_pclk, 1063 &tegra_pclk,
898 &tegra_clk_d, 1064 &tegra_clk_d,
899 &tegra_clk_cdev1, 1065 &tegra_cdev1,
900 &tegra_clk_cdev2, 1066 &tegra_cdev2,
901 &tegra_clk_virtual_cpu, 1067 &tegra_blink,
902 &tegra_clk_blink, 1068 &tegra_cop,
903 &tegra_clk_cop, 1069 &tegra_emc,
904 &tegra_clk_emc,
905}; 1070};
906 1071
907static void tegra2_init_one_clock(struct clk *c) 1072static void tegra2_init_one_clock(struct clk *c)
908{ 1073{
909 clk_init(c); 1074 struct clk_tegra *clk = to_clk_tegra(c->hw);
910 INIT_LIST_HEAD(&c->shared_bus_list); 1075 int ret;
911 if (!c->lookup.dev_id && !c->lookup.con_id) 1076
912 c->lookup.con_id = c->name; 1077 ret = __clk_init(NULL, c);
913 c->lookup.clk = c; 1078 if (ret)
914 clkdev_add(&c->lookup); 1079 pr_err("clk init failed %s\n", __clk_get_name(c));
1080
1081 INIT_LIST_HEAD(&clk->shared_bus_list);
1082 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1083 clk->lookup.con_id = c->name;
1084 clk->lookup.clk = c;
1085 clkdev_add(&clk->lookup);
1086 tegra_clk_add(c);
915} 1087}
916 1088
917void __init tegra2_init_clocks(void) 1089void __init tegra2_init_clocks(void)
@@ -923,7 +1095,7 @@ void __init tegra2_init_clocks(void)
923 tegra2_init_one_clock(tegra_ptr_clks[i]); 1095 tegra2_init_one_clock(tegra_ptr_clks[i]);
924 1096
925 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) 1097 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
926 tegra2_init_one_clock(&tegra_list_clks[i]); 1098 tegra2_init_one_clock(tegra_list_clks[i]);
927 1099
928 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { 1100 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
929 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); 1101 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 645ef6900a0e..a9fa8ea0b6e0 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -381,14 +381,16 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
381 udelay(2); \ 381 udelay(2); \
382 } while (0) 382 } while (0)
383 383
384 384static inline int clk_set_div(struct clk_tegra *c, u32 n)
385static inline int clk_set_div(struct clk *c, u32 n)
386{ 385{
387 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); 386 struct clk *clk = c->hw.clk;
387
388 return clk_set_rate(clk,
389 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
388} 390}
389 391
390static inline u32 periph_clk_to_reg( 392static inline u32 periph_clk_to_reg(
391 struct clk *c, u32 reg_L, u32 reg_V, int offs) 393 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
392{ 394{
393 u32 reg = c->u.periph.clk_num / 32; 395 u32 reg = c->u.periph.clk_num / 32;
394 BUG_ON(reg >= RST_DEVICES_NUM); 396 BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +472,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
470 return divider_u16 - 1; 472 return divider_u16 - 1;
471} 473}
472 474
475static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
476 unsigned long parent_rate)
477{
478 return to_clk_tegra(hw)->fixed_rate;
479}
480
481struct clk_ops tegra_clk_32k_ops = {
482 .recalc_rate = tegra30_clk_fixed_recalc_rate,
483};
484
473/* clk_m functions */ 485/* clk_m functions */
474static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c) 486static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
487 unsigned long parent_rate)
488{
489 if (!to_clk_tegra(hw)->fixed_rate)
490 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
491 return to_clk_tegra(hw)->fixed_rate;
492}
493
494static void tegra30_clk_m_init(struct clk_hw *hw)
475{ 495{
476 u32 osc_ctrl = clk_readl(OSC_CTRL); 496 u32 osc_ctrl = clk_readl(OSC_CTRL);
477 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; 497 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
478 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 498 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
479 499
480 c->rate = clk_measure_input_freq(); 500 switch (to_clk_tegra(hw)->fixed_rate) {
481 switch (c->rate) {
482 case 12000000: 501 case 12000000:
483 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; 502 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
484 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 503 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +527,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
508 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 527 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
509 break; 528 break;
510 default: 529 default:
511 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); 530 pr_err("%s: Unexpected clock rate %ld", __func__,
531 to_clk_tegra(hw)->fixed_rate);
512 BUG(); 532 BUG();
513 } 533 }
514 clk_writel(auto_clock_control, OSC_CTRL); 534 clk_writel(auto_clock_control, OSC_CTRL);
515 return c->rate;
516} 535}
517 536
518static void tegra30_clk_m_init(struct clk *c) 537struct clk_ops tegra30_clk_m_ops = {
519{ 538 .init = tegra30_clk_m_init,
520 pr_debug("%s on clock %s\n", __func__, c->name); 539 .recalc_rate = tegra30_clk_m_recalc_rate,
521 tegra30_clk_m_autodetect_rate(c); 540};
522}
523 541
524static int tegra30_clk_m_enable(struct clk *c) 542static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
543 unsigned long parent_rate)
525{ 544{
526 pr_debug("%s on clock %s\n", __func__, c->name); 545 struct clk_tegra *c = to_clk_tegra(hw);
527 return 0; 546 u64 rate = parent_rate;
528}
529 547
530static void tegra30_clk_m_disable(struct clk *c) 548 if (c->mul != 0 && c->div != 0) {
531{ 549 rate *= c->mul;
532 pr_debug("%s on clock %s\n", __func__, c->name); 550 rate += c->div - 1; /* round up */
533 WARN(1, "Attempting to disable main SoC clock\n"); 551 do_div(rate, c->div);
534} 552 }
535 553
536struct clk_ops tegra30_clk_m_ops = { 554 return rate;
537 .init = tegra30_clk_m_init, 555}
538 .enable = tegra30_clk_m_enable,
539 .disable = tegra30_clk_m_disable,
540};
541 556
542struct clk_ops tegra_clk_m_div_ops = { 557struct clk_ops tegra_clk_m_div_ops = {
543 .enable = tegra30_clk_m_enable, 558 .recalc_rate = tegra30_clk_m_div_recalc_rate,
544}; 559};
545 560
546/* PLL reference divider functions */ 561/* PLL reference divider functions */
547static void tegra30_pll_ref_init(struct clk *c) 562static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
563 unsigned long parent_rate)
548{ 564{
565 struct clk_tegra *c = to_clk_tegra(hw);
566 unsigned long rate = parent_rate;
549 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; 567 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
550 pr_debug("%s on clock %s\n", __func__, c->name);
551 568
552 switch (pll_ref_div) { 569 switch (pll_ref_div) {
553 case OSC_CTRL_PLL_REF_DIV_1: 570 case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +581,18 @@ static void tegra30_pll_ref_init(struct clk *c)
564 BUG(); 581 BUG();
565 } 582 }
566 c->mul = 1; 583 c->mul = 1;
567 c->state = ON; 584
585 if (c->mul != 0 && c->div != 0) {
586 rate *= c->mul;
587 rate += c->div - 1; /* round up */
588 do_div(rate, c->div);
589 }
590
591 return rate;
568} 592}
569 593
570struct clk_ops tegra_pll_ref_ops = { 594struct clk_ops tegra_pll_ref_ops = {
571 .init = tegra30_pll_ref_init, 595 .recalc_rate = tegra30_pll_ref_recalc_rate,
572 .enable = tegra30_clk_m_enable,
573 .disable = tegra30_clk_m_disable,
574}; 596};
575 597
576/* super clock functions */ 598/* super clock functions */
@@ -581,56 +603,50 @@ struct clk_ops tegra_pll_ref_ops = {
581 * only when its parent is a fixed rate PLL, since we can't change PLL rate 603 * only when its parent is a fixed rate PLL, since we can't change PLL rate
582 * in this case. 604 * in this case.
583 */ 605 */
584static void tegra30_super_clk_init(struct clk *c) 606static void tegra30_super_clk_init(struct clk_hw *hw)
585{ 607{
586 u32 val; 608 struct clk_tegra *c = to_clk_tegra(hw);
587 int source; 609 struct clk_tegra *p =
588 int shift; 610 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
589 const struct clk_mux_sel *sel;
590 val = clk_readl(c->reg + SUPER_CLK_MUX);
591 c->state = ON;
592 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
593 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
594 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
595 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
596 source = (val >> shift) & SUPER_SOURCE_MASK;
597 if (c->flags & DIV_2)
598 source |= val & SUPER_LP_DIV2_BYPASS;
599 for (sel = c->inputs; sel->input != NULL; sel++) {
600 if (sel->value == source)
601 break;
602 }
603 BUG_ON(sel->input == NULL);
604 c->parent = sel->input;
605 611
612 c->state = ON;
606 if (c->flags & DIV_U71) { 613 if (c->flags & DIV_U71) {
607 /* Init safe 7.1 divider value (does not affect PLLX path) */ 614 /* Init safe 7.1 divider value (does not affect PLLX path) */
608 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, 615 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
609 c->reg + SUPER_CLK_DIVIDER); 616 c->reg + SUPER_CLK_DIVIDER);
610 c->mul = 2; 617 c->mul = 2;
611 c->div = 2; 618 c->div = 2;
612 if (!(c->parent->flags & PLLX)) 619 if (!(p->flags & PLLX))
613 c->div += SUPER_CLOCK_DIV_U71_MIN; 620 c->div += SUPER_CLOCK_DIV_U71_MIN;
614 } else 621 } else
615 clk_writel(0, c->reg + SUPER_CLK_DIVIDER); 622 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
616} 623}
617 624
618static int tegra30_super_clk_enable(struct clk *c) 625static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
619{ 626{
620 return 0; 627 struct clk_tegra *c = to_clk_tegra(hw);
621} 628 u32 val;
629 int source;
630 int shift;
622 631
623static void tegra30_super_clk_disable(struct clk *c) 632 val = clk_readl(c->reg + SUPER_CLK_MUX);
624{ 633 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
625 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and 634 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
626 geared up g-mode super clock - mode switch may request to disable 635 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
627 either of them; accept request with no affect on h/w */ 636 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
637 source = (val >> shift) & SUPER_SOURCE_MASK;
638 if (c->flags & DIV_2)
639 source |= val & SUPER_LP_DIV2_BYPASS;
640
641 return source;
628} 642}
629 643
630static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p) 644static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
631{ 645{
646 struct clk_tegra *c = to_clk_tegra(hw);
647 struct clk_tegra *p =
648 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
632 u32 val; 649 u32 val;
633 const struct clk_mux_sel *sel;
634 int shift; 650 int shift;
635 651
636 val = clk_readl(c->reg + SUPER_CLK_MUX); 652 val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +654,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
638 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 654 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
639 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 655 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
640 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; 656 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
641 for (sel = c->inputs; sel->input != NULL; sel++) {
642 if (sel->input == p) {
643 /* For LP mode super-clock switch between PLLX direct
644 and divided-by-2 outputs is allowed only when other
645 than PLLX clock source is current parent */
646 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
647 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
648 if (c->parent->flags & PLLX)
649 return -EINVAL;
650 val ^= SUPER_LP_DIV2_BYPASS;
651 clk_writel_delay(val, c->reg);
652 }
653 val &= ~(SUPER_SOURCE_MASK << shift);
654 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
655
656 /* 7.1 divider for CPU super-clock does not affect
657 PLLX path */
658 if (c->flags & DIV_U71) {
659 u32 div = 0;
660 if (!(p->flags & PLLX)) {
661 div = clk_readl(c->reg +
662 SUPER_CLK_DIVIDER);
663 div &= SUPER_CLOCK_DIV_U71_MASK;
664 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
665 }
666 c->div = div + 2;
667 c->mul = 2;
668 }
669 657
670 if (c->refcnt) 658 /* For LP mode super-clock switch between PLLX direct
671 clk_enable(p); 659 and divided-by-2 outputs is allowed only when other
672 660 than PLLX clock source is current parent */
673 clk_writel_delay(val, c->reg); 661 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
674 662 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
675 if (c->refcnt && c->parent) 663 if (p->flags & PLLX)
676 clk_disable(c->parent); 664 return -EINVAL;
665 val ^= SUPER_LP_DIV2_BYPASS;
666 clk_writel_delay(val, c->reg);
667 }
668 val &= ~(SUPER_SOURCE_MASK << shift);
669 val |= (index & SUPER_SOURCE_MASK) << shift;
677 670
678 clk_reparent(c, p); 671 /* 7.1 divider for CPU super-clock does not affect
679 return 0; 672 PLLX path */
673 if (c->flags & DIV_U71) {
674 u32 div = 0;
675 if (!(p->flags & PLLX)) {
676 div = clk_readl(c->reg +
677 SUPER_CLK_DIVIDER);
678 div &= SUPER_CLOCK_DIV_U71_MASK;
679 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
680 } 680 }
681 c->div = div + 2;
682 c->mul = 2;
681 } 683 }
682 return -EINVAL; 684 clk_writel_delay(val, c->reg);
685
686 return 0;
683} 687}
684 688
685/* 689/*
@@ -691,10 +695,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
691 * rate of this PLL can't be changed, and it has many other children. In 695 * rate of this PLL can't be changed, and it has many other children. In
692 * this case use 7.1 fractional divider to adjust the super clock rate. 696 * this case use 7.1 fractional divider to adjust the super clock rate.
693 */ 697 */
694static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate) 698static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
699 unsigned long parent_rate)
695{ 700{
696 if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) { 701 struct clk_tegra *c = to_clk_tegra(hw);
697 int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate, 702 struct clk *parent = __clk_get_parent(hw->clk);
703 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
704
705 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
706 int div = clk_div71_get_divider(parent_rate,
698 rate, c->flags, ROUND_DIVIDER_DOWN); 707 rate, c->flags, ROUND_DIVIDER_DOWN);
699 div = max(div, SUPER_CLOCK_DIV_U71_MIN); 708 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
700 709
@@ -704,55 +713,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
704 c->mul = 2; 713 c->mul = 2;
705 return 0; 714 return 0;
706 } 715 }
707 return clk_set_rate(c->parent, rate); 716 return 0;
717}
718
719static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
720 unsigned long parent_rate)
721{
722 struct clk_tegra *c = to_clk_tegra(hw);
723 u64 rate = parent_rate;
724
725 if (c->mul != 0 && c->div != 0) {
726 rate *= c->mul;
727 rate += c->div - 1; /* round up */
728 do_div(rate, c->div);
729 }
730
731 return rate;
732}
733
734static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
735 unsigned long *prate)
736{
737 struct clk_tegra *c = to_clk_tegra(hw);
738 struct clk *parent = __clk_get_parent(hw->clk);
739 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
740 int mul = 2;
741 int div;
742
743 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
744 div = clk_div71_get_divider(*prate,
745 rate, c->flags, ROUND_DIVIDER_DOWN);
746 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
747 rate = *prate * mul;
748 rate += div - 1; /* round up */
749 do_div(rate, c->div);
750
751 return rate;
752 }
753 return *prate;
708} 754}
709 755
710struct clk_ops tegra30_super_ops = { 756struct clk_ops tegra30_super_ops = {
711 .init = tegra30_super_clk_init, 757 .init = tegra30_super_clk_init,
712 .enable = tegra30_super_clk_enable, 758 .set_parent = tegra30_super_clk_set_parent,
713 .disable = tegra30_super_clk_disable, 759 .get_parent = tegra30_super_clk_get_parent,
714 .set_parent = tegra30_super_clk_set_parent, 760 .recalc_rate = tegra30_super_clk_recalc_rate,
715 .set_rate = tegra30_super_clk_set_rate, 761 .round_rate = tegra30_super_clk_round_rate,
762 .set_rate = tegra30_super_clk_set_rate,
716}; 763};
717 764
718static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate) 765static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
766 unsigned long parent_rate)
719{ 767{
720 /* The input value 'rate' is the clock rate of the CPU complex. */ 768 struct clk_tegra *c = to_clk_tegra(hw);
721 c->rate = (rate * c->mul) / c->div; 769 u64 rate = parent_rate;
722 return 0; 770
771 if (c->mul != 0 && c->div != 0) {
772 rate *= c->mul;
773 rate += c->div - 1; /* round up */
774 do_div(rate, c->div);
775 }
776
777 return rate;
723} 778}
724 779
725struct clk_ops tegra30_twd_ops = { 780struct clk_ops tegra30_twd_ops = {
726 .set_rate = tegra30_twd_clk_set_rate, 781 .recalc_rate = tegra30_twd_clk_recalc_rate,
727}; 782};
728 783
729/* Blink output functions */ 784/* Blink output functions */
730 785static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
731static void tegra30_blink_clk_init(struct clk *c)
732{ 786{
787 struct clk_tegra *c = to_clk_tegra(hw);
733 u32 val; 788 u32 val;
734 789
735 val = pmc_readl(PMC_CTRL); 790 val = pmc_readl(PMC_CTRL);
736 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; 791 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
737 c->mul = 1; 792 return c->state;
738 val = pmc_readl(c->reg);
739
740 if (val & PMC_BLINK_TIMER_ENB) {
741 unsigned int on_off;
742
743 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
744 PMC_BLINK_TIMER_DATA_ON_MASK;
745 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
746 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
747 on_off += val;
748 /* each tick in the blink timer is 4 32KHz clocks */
749 c->div = on_off * 4;
750 } else {
751 c->div = 1;
752 }
753} 793}
754 794
755static int tegra30_blink_clk_enable(struct clk *c) 795static int tegra30_blink_clk_enable(struct clk_hw *hw)
756{ 796{
757 u32 val; 797 u32 val;
758 798
@@ -765,7 +805,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
765 return 0; 805 return 0;
766} 806}
767 807
768static void tegra30_blink_clk_disable(struct clk *c) 808static void tegra30_blink_clk_disable(struct clk_hw *hw)
769{ 809{
770 u32 val; 810 u32 val;
771 811
@@ -776,9 +816,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
776 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); 816 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
777} 817}
778 818
779static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate) 819static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
820 unsigned long parent_rate)
780{ 821{
781 unsigned long parent_rate = clk_get_rate(c->parent); 822 struct clk_tegra *c = to_clk_tegra(hw);
823
782 if (rate >= parent_rate) { 824 if (rate >= parent_rate) {
783 c->div = 1; 825 c->div = 1;
784 pmc_writel(0, c->reg); 826 pmc_writel(0, c->reg);
@@ -801,40 +843,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
801 return 0; 843 return 0;
802} 844}
803 845
804struct clk_ops tegra30_blink_clk_ops = { 846static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
805 .init = &tegra30_blink_clk_init, 847 unsigned long parent_rate)
806 .enable = &tegra30_blink_clk_enable, 848{
807 .disable = &tegra30_blink_clk_disable, 849 struct clk_tegra *c = to_clk_tegra(hw);
808 .set_rate = &tegra30_blink_clk_set_rate, 850 u64 rate = parent_rate;
809}; 851 u32 val;
852 u32 mul;
853 u32 div;
854 u32 on_off;
810 855
811/* PLL Functions */ 856 mul = 1;
812static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, 857 val = pmc_readl(c->reg);
813 u32 lock_bit) 858
859 if (val & PMC_BLINK_TIMER_ENB) {
860 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
861 PMC_BLINK_TIMER_DATA_ON_MASK;
862 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
863 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
864 on_off += val;
865 /* each tick in the blink timer is 4 32KHz clocks */
866 div = on_off * 4;
867 } else {
868 div = 1;
869 }
870
871 if (mul != 0 && div != 0) {
872 rate *= mul;
873 rate += div - 1; /* round up */
874 do_div(rate, div);
875 }
876 return rate;
877}
878
879static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
880 unsigned long *prate)
814{ 881{
815#if USE_PLL_LOCK_BITS 882 int div;
816 int i; 883 int mul;
817 for (i = 0; i < c->u.pll.lock_delay; i++) { 884 long round_rate = *prate;
818 if (clk_readl(lock_reg) & lock_bit) { 885
819 udelay(PLL_POST_LOCK_DELAY); 886 mul = 1;
820 return 0; 887
821 } 888 if (rate >= *prate) {
822 udelay(2); /* timeout = 2 * lock time */ 889 div = 1;
890 } else {
891 div = DIV_ROUND_UP(*prate / 8, rate);
892 div *= 8;
823 } 893 }
824 pr_err("Timed out waiting for lock bit on pll %s", c->name);
825 return -1;
826#endif
827 udelay(c->u.pll.lock_delay);
828 894
829 return 0; 895 round_rate *= mul;
896 round_rate += div - 1;
897 do_div(round_rate, div);
898
899 return round_rate;
830} 900}
831 901
832static void tegra30_utmi_param_configure(struct clk *c) 902struct clk_ops tegra30_blink_clk_ops = {
903 .is_enabled = tegra30_blink_clk_is_enabled,
904 .enable = tegra30_blink_clk_enable,
905 .disable = tegra30_blink_clk_disable,
906 .recalc_rate = tegra30_blink_clk_recalc_rate,
907 .round_rate = tegra30_blink_clk_round_rate,
908 .set_rate = tegra30_blink_clk_set_rate,
909};
910
911static void tegra30_utmi_param_configure(struct clk_hw *hw)
833{ 912{
913 unsigned long main_rate =
914 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
834 u32 reg; 915 u32 reg;
835 int i; 916 int i;
836 unsigned long main_rate =
837 clk_get_rate(c->parent->parent);
838 917
839 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 918 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
840 if (main_rate == utmi_parameters[i].osc_frequency) 919 if (main_rate == utmi_parameters[i].osc_frequency)
@@ -885,50 +964,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
885 clk_writel(reg, UTMIP_PLL_CFG1); 964 clk_writel(reg, UTMIP_PLL_CFG1);
886} 965}
887 966
888static void tegra30_pll_clk_init(struct clk *c) 967/* PLL Functions */
968static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
969 u32 lock_bit)
970{
971 int ret = 0;
972
973#if USE_PLL_LOCK_BITS
974 int i;
975 for (i = 0; i < c->u.pll.lock_delay; i++) {
976 if (clk_readl(lock_reg) & lock_bit) {
977 udelay(PLL_POST_LOCK_DELAY);
978 return 0;
979 }
980 udelay(2); /* timeout = 2 * lock time */
981 }
982 pr_err("Timed out waiting for lock bit on pll %s",
983 __clk_get_name(hw->clk));
984 ret = -1;
985#else
986 udelay(c->u.pll.lock_delay);
987#endif
988 return ret;
989}
990
991static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
889{ 992{
993 struct clk_tegra *c = to_clk_tegra(hw);
890 u32 val = clk_readl(c->reg + PLL_BASE); 994 u32 val = clk_readl(c->reg + PLL_BASE);
891 995
892 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; 996 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
997 return c->state;
998}
893 999
894 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { 1000static void tegra30_pll_clk_init(struct clk_hw *hw)
895 const struct clk_pll_freq_table *sel; 1001{
896 unsigned long input_rate = clk_get_rate(c->parent); 1002 struct clk_tegra *c = to_clk_tegra(hw);
897 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
898 if (sel->input_rate == input_rate &&
899 sel->output_rate == c->u.pll.fixed_rate) {
900 c->mul = sel->n;
901 c->div = sel->m * sel->p;
902 return;
903 }
904 }
905 pr_err("Clock %s has unknown fixed frequency\n", c->name);
906 BUG();
907 } else if (val & PLL_BASE_BYPASS) {
908 c->mul = 1;
909 c->div = 1;
910 } else {
911 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
912 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
913 if (c->flags & PLLU)
914 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
915 else
916 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
917 PLL_BASE_DIVP_SHIFT));
918 if (c->flags & PLL_FIXED) {
919 unsigned long rate = clk_get_rate_locked(c);
920 BUG_ON(rate != c->u.pll.fixed_rate);
921 }
922 }
923 1003
924 if (c->flags & PLLU) 1004 if (c->flags & PLLU)
925 tegra30_utmi_param_configure(c); 1005 tegra30_utmi_param_configure(hw);
926} 1006}
927 1007
928static int tegra30_pll_clk_enable(struct clk *c) 1008static int tegra30_pll_clk_enable(struct clk_hw *hw)
929{ 1009{
1010 struct clk_tegra *c = to_clk_tegra(hw);
930 u32 val; 1011 u32 val;
931 pr_debug("%s on clock %s\n", __func__, c->name); 1012 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
932 1013
933#if USE_PLL_LOCK_BITS 1014#if USE_PLL_LOCK_BITS
934 val = clk_readl(c->reg + PLL_MISC(c)); 1015 val = clk_readl(c->reg + PLL_MISC(c));
@@ -951,10 +1032,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
951 return 0; 1032 return 0;
952} 1033}
953 1034
954static void tegra30_pll_clk_disable(struct clk *c) 1035static void tegra30_pll_clk_disable(struct clk_hw *hw)
955{ 1036{
1037 struct clk_tegra *c = to_clk_tegra(hw);
956 u32 val; 1038 u32 val;
957 pr_debug("%s on clock %s\n", __func__, c->name); 1039 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
958 1040
959 val = clk_readl(c->reg); 1041 val = clk_readl(c->reg);
960 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1042 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -967,36 +1049,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
967 } 1049 }
968} 1050}
969 1051
970static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate) 1052static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1053 unsigned long parent_rate)
971{ 1054{
1055 struct clk_tegra *c = to_clk_tegra(hw);
972 u32 val, p_div, old_base; 1056 u32 val, p_div, old_base;
973 unsigned long input_rate; 1057 unsigned long input_rate;
974 const struct clk_pll_freq_table *sel; 1058 const struct clk_pll_freq_table *sel;
975 struct clk_pll_freq_table cfg; 1059 struct clk_pll_freq_table cfg;
976 1060
977 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
978
979 if (c->flags & PLL_FIXED) { 1061 if (c->flags & PLL_FIXED) {
980 int ret = 0; 1062 int ret = 0;
981 if (rate != c->u.pll.fixed_rate) { 1063 if (rate != c->u.pll.fixed_rate) {
982 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 1064 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
983 __func__, c->name, c->u.pll.fixed_rate, rate); 1065 __func__, __clk_get_name(hw->clk),
1066 c->u.pll.fixed_rate, rate);
984 ret = -EINVAL; 1067 ret = -EINVAL;
985 } 1068 }
986 return ret; 1069 return ret;
987 } 1070 }
988 1071
989 if (c->flags & PLLM) { 1072 if (c->flags & PLLM) {
990 if (rate != clk_get_rate_locked(c)) { 1073 if (rate != __clk_get_rate(hw->clk)) {
991 pr_err("%s: Can not change memory %s rate in flight\n", 1074 pr_err("%s: Can not change memory %s rate in flight\n",
992 __func__, c->name); 1075 __func__, __clk_get_name(hw->clk));
993 return -EINVAL; 1076 return -EINVAL;
994 } 1077 }
995 return 0;
996 } 1078 }
997 1079
998 p_div = 0; 1080 p_div = 0;
999 input_rate = clk_get_rate(c->parent); 1081 input_rate = parent_rate;
1000 1082
1001 /* Check if the target rate is tabulated */ 1083 /* Check if the target rate is tabulated */
1002 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1084 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1054,7 +1136,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1054 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || 1136 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1055 (cfg.output_rate > c->u.pll.vco_max)) { 1137 (cfg.output_rate > c->u.pll.vco_max)) {
1056 pr_err("%s: Failed to set %s out-of-table rate %lu\n", 1138 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1057 __func__, c->name, rate); 1139 __func__, __clk_get_name(hw->clk), rate);
1058 return -EINVAL; 1140 return -EINVAL;
1059 } 1141 }
1060 p_div <<= PLL_BASE_DIVP_SHIFT; 1142 p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1072,7 +1154,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1072 return 0; 1154 return 0;
1073 1155
1074 if (c->state == ON) { 1156 if (c->state == ON) {
1075 tegra30_pll_clk_disable(c); 1157 tegra30_pll_clk_disable(hw);
1076 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1158 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1077 } 1159 }
1078 clk_writel(val, c->reg + PLL_BASE); 1160 clk_writel(val, c->reg + PLL_BASE);
@@ -1094,21 +1176,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1094 } 1176 }
1095 1177
1096 if (c->state == ON) 1178 if (c->state == ON)
1097 tegra30_pll_clk_enable(c); 1179 tegra30_pll_clk_enable(hw);
1180
1181 c->u.pll.fixed_rate = rate;
1098 1182
1099 return 0; 1183 return 0;
1100} 1184}
1101 1185
1186static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1187 unsigned long *prate)
1188{
1189 struct clk_tegra *c = to_clk_tegra(hw);
1190 unsigned long input_rate = *prate;
1191 unsigned long output_rate = *prate;
1192 const struct clk_pll_freq_table *sel;
1193 struct clk_pll_freq_table cfg;
1194 int mul;
1195 int div;
1196 u32 p_div;
1197 u32 val;
1198
1199 if (c->flags & PLL_FIXED)
1200 return c->u.pll.fixed_rate;
1201
1202 if (c->flags & PLLM)
1203 return __clk_get_rate(hw->clk);
1204
1205 p_div = 0;
1206 /* Check if the target rate is tabulated */
1207 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1208 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1209 if (c->flags & PLLU) {
1210 BUG_ON(sel->p < 1 || sel->p > 2);
1211 if (sel->p == 1)
1212 p_div = PLLU_BASE_POST_DIV;
1213 } else {
1214 BUG_ON(sel->p < 1);
1215 for (val = sel->p; val > 1; val >>= 1)
1216 p_div++;
1217 p_div <<= PLL_BASE_DIVP_SHIFT;
1218 }
1219 break;
1220 }
1221 }
1222
1223 if (sel->input_rate == 0) {
1224 unsigned long cfreq;
1225 BUG_ON(c->flags & PLLU);
1226 sel = &cfg;
1227
1228 switch (input_rate) {
1229 case 12000000:
1230 case 26000000:
1231 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1232 break;
1233 case 13000000:
1234 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1235 break;
1236 case 16800000:
1237 case 19200000:
1238 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1239 break;
1240 default:
1241 pr_err("%s: Unexpected reference rate %lu\n",
1242 __func__, input_rate);
1243 BUG();
1244 }
1245
1246 /* Raise VCO to guarantee 0.5% accuracy */
1247 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1248 cfg.output_rate <<= 1)
1249 p_div++;
1250
1251 cfg.p = 0x1 << p_div;
1252 cfg.m = input_rate / cfreq;
1253 cfg.n = cfg.output_rate / cfreq;
1254 }
1255
1256 mul = sel->n;
1257 div = sel->m * sel->p;
1258
1259 output_rate *= mul;
1260 output_rate += div - 1; /* round up */
1261 do_div(output_rate, div);
1262
1263 return output_rate;
1264}
1265
1266static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1267 unsigned long parent_rate)
1268{
1269 struct clk_tegra *c = to_clk_tegra(hw);
1270 u64 rate = parent_rate;
1271 u32 val = clk_readl(c->reg + PLL_BASE);
1272
1273 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1274 const struct clk_pll_freq_table *sel;
1275 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1276 if (sel->input_rate == parent_rate &&
1277 sel->output_rate == c->u.pll.fixed_rate) {
1278 c->mul = sel->n;
1279 c->div = sel->m * sel->p;
1280 break;
1281 }
1282 }
1283 pr_err("Clock %s has unknown fixed frequency\n",
1284 __clk_get_name(hw->clk));
1285 BUG();
1286 } else if (val & PLL_BASE_BYPASS) {
1287 c->mul = 1;
1288 c->div = 1;
1289 } else {
1290 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1291 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1292 if (c->flags & PLLU)
1293 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1294 else
1295 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1296 PLL_BASE_DIVP_SHIFT));
1297 }
1298
1299 if (c->mul != 0 && c->div != 0) {
1300 rate *= c->mul;
1301 rate += c->div - 1; /* round up */
1302 do_div(rate, c->div);
1303 }
1304
1305 return rate;
1306}
1307
1102struct clk_ops tegra30_pll_ops = { 1308struct clk_ops tegra30_pll_ops = {
1103 .init = tegra30_pll_clk_init, 1309 .is_enabled = tegra30_pll_clk_is_enabled,
1104 .enable = tegra30_pll_clk_enable, 1310 .init = tegra30_pll_clk_init,
1105 .disable = tegra30_pll_clk_disable, 1311 .enable = tegra30_pll_clk_enable,
1106 .set_rate = tegra30_pll_clk_set_rate, 1312 .disable = tegra30_pll_clk_disable,
1313 .recalc_rate = tegra30_pll_recalc_rate,
1314 .round_rate = tegra30_pll_round_rate,
1315 .set_rate = tegra30_pll_clk_set_rate,
1107}; 1316};
1108 1317
1109static int 1318int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1110tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1319 enum tegra_clk_ex_param p, u32 setting)
1111{ 1320{
1321 struct clk_tegra *c = to_clk_tegra(hw);
1112 u32 val, mask, reg; 1322 u32 val, mask, reg;
1113 1323
1114 switch (p) { 1324 switch (p) {
@@ -1140,41 +1350,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1140 return 0; 1350 return 0;
1141} 1351}
1142 1352
1143struct clk_ops tegra_plld_ops = { 1353static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1144 .init = tegra30_pll_clk_init,
1145 .enable = tegra30_pll_clk_enable,
1146 .disable = tegra30_pll_clk_disable,
1147 .set_rate = tegra30_pll_clk_set_rate,
1148 .clk_cfg_ex = tegra30_plld_clk_cfg_ex,
1149};
1150
1151static void tegra30_plle_clk_init(struct clk *c)
1152{ 1354{
1355 struct clk_tegra *c = to_clk_tegra(hw);
1153 u32 val; 1356 u32 val;
1154 1357
1155 val = clk_readl(PLLE_AUX);
1156 c->parent = (val & PLLE_AUX_PLLP_SEL) ?
1157 tegra_get_clock_by_name("pll_p") :
1158 tegra_get_clock_by_name("pll_ref");
1159
1160 val = clk_readl(c->reg + PLL_BASE); 1358 val = clk_readl(c->reg + PLL_BASE);
1161 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; 1359 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1162 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; 1360 return c->state;
1163 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1164 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1165} 1361}
1166 1362
1167static void tegra30_plle_clk_disable(struct clk *c) 1363static void tegra30_plle_clk_disable(struct clk_hw *hw)
1168{ 1364{
1365 struct clk_tegra *c = to_clk_tegra(hw);
1169 u32 val; 1366 u32 val;
1170 pr_debug("%s on clock %s\n", __func__, c->name);
1171 1367
1172 val = clk_readl(c->reg + PLL_BASE); 1368 val = clk_readl(c->reg + PLL_BASE);
1173 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); 1369 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1174 clk_writel(val, c->reg + PLL_BASE); 1370 clk_writel(val, c->reg + PLL_BASE);
1175} 1371}
1176 1372
1177static void tegra30_plle_training(struct clk *c) 1373static void tegra30_plle_training(struct clk_tegra *c)
1178{ 1374{
1179 u32 val; 1375 u32 val;
1180 1376
@@ -1197,12 +1393,15 @@ static void tegra30_plle_training(struct clk *c)
1197 } while (!(val & PLLE_MISC_READY)); 1393 } while (!(val & PLLE_MISC_READY));
1198} 1394}
1199 1395
1200static int tegra30_plle_configure(struct clk *c, bool force_training) 1396static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1201{ 1397{
1202 u32 val; 1398 struct clk_tegra *c = to_clk_tegra(hw);
1399 struct clk *parent = __clk_get_parent(hw->clk);
1203 const struct clk_pll_freq_table *sel; 1400 const struct clk_pll_freq_table *sel;
1401 u32 val;
1402
1204 unsigned long rate = c->u.pll.fixed_rate; 1403 unsigned long rate = c->u.pll.fixed_rate;
1205 unsigned long input_rate = clk_get_rate(c->parent); 1404 unsigned long input_rate = __clk_get_rate(parent);
1206 1405
1207 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1406 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1208 if (sel->input_rate == input_rate && sel->output_rate == rate) 1407 if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1213,7 +1412,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1213 return -ENOSYS; 1412 return -ENOSYS;
1214 1413
1215 /* disable PLLE, clear setup fiels */ 1414 /* disable PLLE, clear setup fiels */
1216 tegra30_plle_clk_disable(c); 1415 tegra30_plle_clk_disable(hw);
1217 1416
1218 val = clk_readl(c->reg + PLL_MISC(c)); 1417 val = clk_readl(c->reg + PLL_MISC(c));
1219 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 1418 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1251,52 +1450,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1251 return 0; 1450 return 0;
1252} 1451}
1253 1452
1254static int tegra30_plle_clk_enable(struct clk *c) 1453static int tegra30_plle_clk_enable(struct clk_hw *hw)
1255{ 1454{
1256 pr_debug("%s on clock %s\n", __func__, c->name); 1455 struct clk_tegra *c = to_clk_tegra(hw);
1257 return tegra30_plle_configure(c, !c->set); 1456
1457 return tegra30_plle_configure(hw, !c->set);
1458}
1459
1460static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1461 unsigned long parent_rate)
1462{
1463 struct clk_tegra *c = to_clk_tegra(hw);
1464 unsigned long rate = parent_rate;
1465 u32 val;
1466
1467 val = clk_readl(c->reg + PLL_BASE);
1468 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1469 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1470 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1471
1472 if (c->mul != 0 && c->div != 0) {
1473 rate *= c->mul;
1474 rate += c->div - 1; /* round up */
1475 do_div(rate, c->div);
1476 }
1477 return rate;
1258} 1478}
1259 1479
1260struct clk_ops tegra30_plle_ops = { 1480struct clk_ops tegra30_plle_ops = {
1261 .init = tegra30_plle_clk_init, 1481 .is_enabled = tegra30_plle_clk_is_enabled,
1262 .enable = tegra30_plle_clk_enable, 1482 .enable = tegra30_plle_clk_enable,
1263 .disable = tegra30_plle_clk_disable, 1483 .disable = tegra30_plle_clk_disable,
1484 .recalc_rate = tegra30_plle_clk_recalc_rate,
1264}; 1485};
1265 1486
1266/* Clock divider ops */ 1487/* Clock divider ops */
1267static void tegra30_pll_div_clk_init(struct clk *c) 1488static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1268{ 1489{
1490 struct clk_tegra *c = to_clk_tegra(hw);
1491
1269 if (c->flags & DIV_U71) { 1492 if (c->flags & DIV_U71) {
1270 u32 divu71;
1271 u32 val = clk_readl(c->reg); 1493 u32 val = clk_readl(c->reg);
1272 val >>= c->reg_shift; 1494 val >>= c->reg_shift;
1273 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; 1495 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1274 if (!(val & PLL_OUT_RESET_DISABLE)) 1496 if (!(val & PLL_OUT_RESET_DISABLE))
1275 c->state = OFF; 1497 c->state = OFF;
1276
1277 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1278 c->div = (divu71 + 2);
1279 c->mul = 2;
1280 } else if (c->flags & DIV_2) {
1281 c->state = ON;
1282 if (c->flags & (PLLD | PLLX)) {
1283 c->div = 2;
1284 c->mul = 1;
1285 } else
1286 BUG();
1287 } else { 1498 } else {
1288 c->state = ON; 1499 c->state = ON;
1289 c->div = 1;
1290 c->mul = 1;
1291 } 1500 }
1501 return c->state;
1292} 1502}
1293 1503
1294static int tegra30_pll_div_clk_enable(struct clk *c) 1504static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1295{ 1505{
1506 struct clk_tegra *c = to_clk_tegra(hw);
1296 u32 val; 1507 u32 val;
1297 u32 new_val; 1508 u32 new_val;
1298 1509
1299 pr_debug("%s: %s\n", __func__, c->name); 1510 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1300 if (c->flags & DIV_U71) { 1511 if (c->flags & DIV_U71) {
1301 val = clk_readl(c->reg); 1512 val = clk_readl(c->reg);
1302 new_val = val >> c->reg_shift; 1513 new_val = val >> c->reg_shift;
@@ -1314,12 +1525,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
1314 return -EINVAL; 1525 return -EINVAL;
1315} 1526}
1316 1527
1317static void tegra30_pll_div_clk_disable(struct clk *c) 1528static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1318{ 1529{
1530 struct clk_tegra *c = to_clk_tegra(hw);
1319 u32 val; 1531 u32 val;
1320 u32 new_val; 1532 u32 new_val;
1321 1533
1322 pr_debug("%s: %s\n", __func__, c->name); 1534 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1323 if (c->flags & DIV_U71) { 1535 if (c->flags & DIV_U71) {
1324 val = clk_readl(c->reg); 1536 val = clk_readl(c->reg);
1325 new_val = val >> c->reg_shift; 1537 new_val = val >> c->reg_shift;
@@ -1333,14 +1545,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
1333 } 1545 }
1334} 1546}
1335 1547
1336static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate) 1548static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1549 unsigned long parent_rate)
1337{ 1550{
1551 struct clk_tegra *c = to_clk_tegra(hw);
1338 u32 val; 1552 u32 val;
1339 u32 new_val; 1553 u32 new_val;
1340 int divider_u71; 1554 int divider_u71;
1341 unsigned long parent_rate = clk_get_rate(c->parent);
1342 1555
1343 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1344 if (c->flags & DIV_U71) { 1556 if (c->flags & DIV_U71) {
1345 divider_u71 = clk_div71_get_divider( 1557 divider_u71 = clk_div71_get_divider(
1346 parent_rate, rate, c->flags, ROUND_DIVIDER_UP); 1558 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1358,19 +1570,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
1358 clk_writel_delay(val, c->reg); 1570 clk_writel_delay(val, c->reg);
1359 c->div = divider_u71 + 2; 1571 c->div = divider_u71 + 2;
1360 c->mul = 2; 1572 c->mul = 2;
1573 c->fixed_rate = rate;
1361 return 0; 1574 return 0;
1362 } 1575 }
1363 } else if (c->flags & DIV_2) 1576 } else if (c->flags & DIV_2) {
1364 return clk_set_rate(c->parent, rate * 2); 1577 c->fixed_rate = rate;
1578 return 0;
1579 }
1365 1580
1366 return -EINVAL; 1581 return -EINVAL;
1367} 1582}
1368 1583
1369static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate) 1584static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1585 unsigned long parent_rate)
1586{
1587 struct clk_tegra *c = to_clk_tegra(hw);
1588 u64 rate = parent_rate;
1589
1590 if (c->flags & DIV_U71) {
1591 u32 divu71;
1592 u32 val = clk_readl(c->reg);
1593 val >>= c->reg_shift;
1594
1595 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1596 c->div = (divu71 + 2);
1597 c->mul = 2;
1598 } else if (c->flags & DIV_2) {
1599 if (c->flags & (PLLD | PLLX)) {
1600 c->div = 2;
1601 c->mul = 1;
1602 } else
1603 BUG();
1604 } else {
1605 c->div = 1;
1606 c->mul = 1;
1607 }
1608 if (c->mul != 0 && c->div != 0) {
1609 rate *= c->mul;
1610 rate += c->div - 1; /* round up */
1611 do_div(rate, c->div);
1612 }
1613
1614 return rate;
1615}
1616
1617static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1618 unsigned long rate, unsigned long *prate)
1370{ 1619{
1620 struct clk_tegra *c = to_clk_tegra(hw);
1621 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1371 int divider; 1622 int divider;
1372 unsigned long parent_rate = clk_get_rate(c->parent); 1623
1373 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1624 if (prate)
1625 parent_rate = *prate;
1374 1626
1375 if (c->flags & DIV_U71) { 1627 if (c->flags & DIV_U71) {
1376 divider = clk_div71_get_divider( 1628 divider = clk_div71_get_divider(
@@ -1378,23 +1630,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1378 if (divider < 0) 1630 if (divider < 0)
1379 return divider; 1631 return divider;
1380 return DIV_ROUND_UP(parent_rate * 2, divider + 2); 1632 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1381 } else if (c->flags & DIV_2) 1633 } else if (c->flags & DIV_2) {
1382 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ 1634 *prate = rate * 2;
1383 return rate; 1635 return rate;
1636 }
1384 1637
1385 return -EINVAL; 1638 return -EINVAL;
1386} 1639}
1387 1640
1388struct clk_ops tegra30_pll_div_ops = { 1641struct clk_ops tegra30_pll_div_ops = {
1389 .init = tegra30_pll_div_clk_init, 1642 .is_enabled = tegra30_pll_div_clk_is_enabled,
1390 .enable = tegra30_pll_div_clk_enable, 1643 .enable = tegra30_pll_div_clk_enable,
1391 .disable = tegra30_pll_div_clk_disable, 1644 .disable = tegra30_pll_div_clk_disable,
1392 .set_rate = tegra30_pll_div_clk_set_rate, 1645 .set_rate = tegra30_pll_div_clk_set_rate,
1393 .round_rate = tegra30_pll_div_clk_round_rate, 1646 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1647 .round_rate = tegra30_pll_div_clk_round_rate,
1394}; 1648};
1395 1649
1396/* Periph clk ops */ 1650/* Periph clk ops */
1397static inline u32 periph_clk_source_mask(struct clk *c) 1651static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1398{ 1652{
1399 if (c->flags & MUX8) 1653 if (c->flags & MUX8)
1400 return 7 << 29; 1654 return 7 << 29;
@@ -1408,7 +1662,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
1408 return 3 << 30; 1662 return 3 << 30;
1409} 1663}
1410 1664
1411static inline u32 periph_clk_source_shift(struct clk *c) 1665static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1412{ 1666{
1413 if (c->flags & MUX8) 1667 if (c->flags & MUX8)
1414 return 29; 1668 return 29;
@@ -1422,47 +1676,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
1422 return 30; 1676 return 30;
1423} 1677}
1424 1678
1425static void tegra30_periph_clk_init(struct clk *c) 1679static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1426{ 1680{
1427 u32 val = clk_readl(c->reg); 1681 struct clk_tegra *c = to_clk_tegra(hw);
1428 const struct clk_mux_sel *mux = 0;
1429 const struct clk_mux_sel *sel;
1430 if (c->flags & MUX) {
1431 for (sel = c->inputs; sel->input != NULL; sel++) {
1432 if (((val & periph_clk_source_mask(c)) >>
1433 periph_clk_source_shift(c)) == sel->value)
1434 mux = sel;
1435 }
1436 BUG_ON(!mux);
1437
1438 c->parent = mux->input;
1439 } else {
1440 c->parent = c->inputs[0].input;
1441 }
1442
1443 if (c->flags & DIV_U71) {
1444 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1445 if ((c->flags & DIV_U71_UART) &&
1446 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1447 divu71 = 0;
1448 }
1449 if (c->flags & DIV_U71_IDLE) {
1450 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1451 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1452 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1453 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1454 clk_writel(val, c->reg);
1455 }
1456 c->div = divu71 + 2;
1457 c->mul = 2;
1458 } else if (c->flags & DIV_U16) {
1459 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1460 c->div = divu16 + 1;
1461 c->mul = 1;
1462 } else {
1463 c->div = 1;
1464 c->mul = 1;
1465 }
1466 1682
1467 c->state = ON; 1683 c->state = ON;
1468 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 1684 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1470,11 +1686,12 @@ static void tegra30_periph_clk_init(struct clk *c)
1470 if (!(c->flags & PERIPH_NO_RESET)) 1686 if (!(c->flags & PERIPH_NO_RESET))
1471 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) 1687 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1472 c->state = OFF; 1688 c->state = OFF;
1689 return c->state;
1473} 1690}
1474 1691
1475static int tegra30_periph_clk_enable(struct clk *c) 1692static int tegra30_periph_clk_enable(struct clk_hw *hw)
1476{ 1693{
1477 pr_debug("%s on clock %s\n", __func__, c->name); 1694 struct clk_tegra *c = to_clk_tegra(hw);
1478 1695
1479 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; 1696 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1480 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) 1697 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1493,31 +1710,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
1493 return 0; 1710 return 0;
1494} 1711}
1495 1712
1496static void tegra30_periph_clk_disable(struct clk *c) 1713static void tegra30_periph_clk_disable(struct clk_hw *hw)
1497{ 1714{
1715 struct clk_tegra *c = to_clk_tegra(hw);
1498 unsigned long val; 1716 unsigned long val;
1499 pr_debug("%s on clock %s\n", __func__, c->name);
1500 1717
1501 if (c->refcnt) 1718 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1502 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1503 1719
1504 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { 1720 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1505 /* If peripheral is in the APB bus then read the APB bus to 1721 return;
1506 * flush the write operation in apb bus. This will avoid the
1507 * peripheral access after disabling clock*/
1508 if (c->flags & PERIPH_ON_APB)
1509 val = chipid_readl();
1510 1722
1511 clk_writel_delay( 1723 /* If peripheral is in the APB bus then read the APB bus to
1512 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); 1724 * flush the write operation in apb bus. This will avoid the
1513 } 1725 * peripheral access after disabling clock*/
1726 if (c->flags & PERIPH_ON_APB)
1727 val = chipid_readl();
1728
1729 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1514} 1730}
1515 1731
1516static void tegra30_periph_clk_reset(struct clk *c, bool assert) 1732void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1517{ 1733{
1734 struct clk_tegra *c = to_clk_tegra(hw);
1518 unsigned long val; 1735 unsigned long val;
1519 pr_debug("%s %s on clock %s\n", __func__,
1520 assert ? "assert" : "deassert", c->name);
1521 1736
1522 if (!(c->flags & PERIPH_NO_RESET)) { 1737 if (!(c->flags & PERIPH_NO_RESET)) {
1523 if (assert) { 1738 if (assert) {
@@ -1536,42 +1751,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
1536 } 1751 }
1537} 1752}
1538 1753
1539static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p) 1754static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1540{ 1755{
1756 struct clk_tegra *c = to_clk_tegra(hw);
1541 u32 val; 1757 u32 val;
1542 const struct clk_mux_sel *sel;
1543 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1544 1758
1545 if (!(c->flags & MUX)) 1759 if (!(c->flags & MUX))
1546 return (p == c->parent) ? 0 : (-EINVAL); 1760 return (index == 0) ? 0 : (-EINVAL);
1547 1761
1548 for (sel = c->inputs; sel->input != NULL; sel++) { 1762 val = clk_readl(c->reg);
1549 if (sel->input == p) { 1763 val &= ~periph_clk_source_mask(c);
1550 val = clk_readl(c->reg); 1764 val |= (index << periph_clk_source_shift(c));
1551 val &= ~periph_clk_source_mask(c); 1765 clk_writel_delay(val, c->reg);
1552 val |= (sel->value << periph_clk_source_shift(c)); 1766 return 0;
1553 1767}
1554 if (c->refcnt)
1555 clk_enable(p);
1556
1557 clk_writel_delay(val, c->reg);
1558 1768
1559 if (c->refcnt && c->parent) 1769static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1560 clk_disable(c->parent); 1770{
1771 struct clk_tegra *c = to_clk_tegra(hw);
1772 u32 val = clk_readl(c->reg);
1773 int source = (val & periph_clk_source_mask(c)) >>
1774 periph_clk_source_shift(c);
1561 1775
1562 clk_reparent(c, p); 1776 if (!(c->flags & MUX))
1563 return 0; 1777 return 0;
1564 }
1565 }
1566 1778
1567 return -EINVAL; 1779 return source;
1568} 1780}
1569 1781
1570static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate) 1782static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1783 unsigned long parent_rate)
1571{ 1784{
1785 struct clk_tegra *c = to_clk_tegra(hw);
1572 u32 val; 1786 u32 val;
1573 int divider; 1787 int divider;
1574 unsigned long parent_rate = clk_get_rate(c->parent);
1575 1788
1576 if (c->flags & DIV_U71) { 1789 if (c->flags & DIV_U71) {
1577 divider = clk_div71_get_divider( 1790 divider = clk_div71_get_divider(
@@ -1610,12 +1823,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
1610 return -EINVAL; 1823 return -EINVAL;
1611} 1824}
1612 1825
1613static long tegra30_periph_clk_round_rate(struct clk *c, 1826static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1614 unsigned long rate) 1827 unsigned long *prate)
1615{ 1828{
1829 struct clk_tegra *c = to_clk_tegra(hw);
1830 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1616 int divider; 1831 int divider;
1617 unsigned long parent_rate = clk_get_rate(c->parent); 1832
1618 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1833 if (prate)
1834 parent_rate = *prate;
1619 1835
1620 if (c->flags & DIV_U71) { 1836 if (c->flags & DIV_U71) {
1621 divider = clk_div71_get_divider( 1837 divider = clk_div71_get_divider(
@@ -1633,20 +1849,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
1633 return -EINVAL; 1849 return -EINVAL;
1634} 1850}
1635 1851
1852static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1853 unsigned long parent_rate)
1854{
1855 struct clk_tegra *c = to_clk_tegra(hw);
1856 u64 rate = parent_rate;
1857 u32 val = clk_readl(c->reg);
1858
1859 if (c->flags & DIV_U71) {
1860 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1861 if ((c->flags & DIV_U71_UART) &&
1862 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1863 divu71 = 0;
1864 }
1865 if (c->flags & DIV_U71_IDLE) {
1866 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1867 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1868 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1869 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1870 clk_writel(val, c->reg);
1871 }
1872 c->div = divu71 + 2;
1873 c->mul = 2;
1874 } else if (c->flags & DIV_U16) {
1875 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1876 c->div = divu16 + 1;
1877 c->mul = 1;
1878 } else {
1879 c->div = 1;
1880 c->mul = 1;
1881 }
1882
1883 if (c->mul != 0 && c->div != 0) {
1884 rate *= c->mul;
1885 rate += c->div - 1; /* round up */
1886 do_div(rate, c->div);
1887 }
1888 return rate;
1889}
1890
1636struct clk_ops tegra30_periph_clk_ops = { 1891struct clk_ops tegra30_periph_clk_ops = {
1637 .init = &tegra30_periph_clk_init, 1892 .is_enabled = tegra30_periph_clk_is_enabled,
1893 .enable = tegra30_periph_clk_enable,
1894 .disable = tegra30_periph_clk_disable,
1895 .set_parent = tegra30_periph_clk_set_parent,
1896 .get_parent = tegra30_periph_clk_get_parent,
1897 .set_rate = tegra30_periph_clk_set_rate,
1898 .round_rate = tegra30_periph_clk_round_rate,
1899 .recalc_rate = tegra30_periph_clk_recalc_rate,
1900};
1901
1902static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
1903{
1904 struct clk *d = clk_get_sys(NULL, "pll_d");
1905 /* The DSIB parent selection bit is in PLLD base
1906 register - can not do direct r-m-w, must be
1907 protected by PLLD lock */
1908 tegra_clk_cfg_ex(
1909 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
1910
1911 return 0;
1912}
1913
1914struct clk_ops tegra30_dsib_clk_ops = {
1915 .is_enabled = tegra30_periph_clk_is_enabled,
1638 .enable = &tegra30_periph_clk_enable, 1916 .enable = &tegra30_periph_clk_enable,
1639 .disable = &tegra30_periph_clk_disable, 1917 .disable = &tegra30_periph_clk_disable,
1640 .set_parent = &tegra30_periph_clk_set_parent, 1918 .set_parent = &tegra30_dsib_clk_set_parent,
1919 .get_parent = &tegra30_periph_clk_get_parent,
1641 .set_rate = &tegra30_periph_clk_set_rate, 1920 .set_rate = &tegra30_periph_clk_set_rate,
1642 .round_rate = &tegra30_periph_clk_round_rate, 1921 .round_rate = &tegra30_periph_clk_round_rate,
1643 .reset = &tegra30_periph_clk_reset, 1922 .recalc_rate = &tegra30_periph_clk_recalc_rate,
1644}; 1923};
1645 1924
1646/* Periph extended clock configuration ops */ 1925/* Periph extended clock configuration ops */
1647static int 1926int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
1648tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1927 enum tegra_clk_ex_param p, u32 setting)
1649{ 1928{
1929 struct clk_tegra *c = to_clk_tegra(hw);
1930
1650 if (p == TEGRA_CLK_VI_INP_SEL) { 1931 if (p == TEGRA_CLK_VI_INP_SEL) {
1651 u32 val = clk_readl(c->reg); 1932 u32 val = clk_readl(c->reg);
1652 val &= ~PERIPH_CLK_VI_SEL_EX_MASK; 1933 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1658,20 +1939,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1658 return -EINVAL; 1939 return -EINVAL;
1659} 1940}
1660 1941
1661struct clk_ops tegra_vi_clk_ops = { 1942int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
1662 .init = &tegra30_periph_clk_init, 1943 enum tegra_clk_ex_param p, u32 setting)
1663 .enable = &tegra30_periph_clk_enable,
1664 .disable = &tegra30_periph_clk_disable,
1665 .set_parent = &tegra30_periph_clk_set_parent,
1666 .set_rate = &tegra30_periph_clk_set_rate,
1667 .round_rate = &tegra30_periph_clk_round_rate,
1668 .clk_cfg_ex = &tegra30_vi_clk_cfg_ex,
1669 .reset = &tegra30_periph_clk_reset,
1670};
1671
1672static int
1673tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1674{ 1944{
1945 struct clk_tegra *c = to_clk_tegra(hw);
1946
1675 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { 1947 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
1676 u32 val = clk_readl(c->reg); 1948 u32 val = clk_readl(c->reg);
1677 if (setting) 1949 if (setting)
@@ -1684,20 +1956,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1684 return -EINVAL; 1956 return -EINVAL;
1685} 1957}
1686 1958
1687struct clk_ops tegra_nand_clk_ops = { 1959int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
1688 .init = &tegra30_periph_clk_init, 1960 enum tegra_clk_ex_param p, u32 setting)
1689 .enable = &tegra30_periph_clk_enable,
1690 .disable = &tegra30_periph_clk_disable,
1691 .set_parent = &tegra30_periph_clk_set_parent,
1692 .set_rate = &tegra30_periph_clk_set_rate,
1693 .round_rate = &tegra30_periph_clk_round_rate,
1694 .clk_cfg_ex = &tegra30_nand_clk_cfg_ex,
1695 .reset = &tegra30_periph_clk_reset,
1696};
1697
1698static int
1699tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1700{ 1961{
1962 struct clk_tegra *c = to_clk_tegra(hw);
1963
1701 if (p == TEGRA_CLK_DTV_INVERT) { 1964 if (p == TEGRA_CLK_DTV_INVERT) {
1702 u32 val = clk_readl(c->reg); 1965 u32 val = clk_readl(c->reg);
1703 if (setting) 1966 if (setting)
@@ -1710,91 +1973,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1710 return -EINVAL; 1973 return -EINVAL;
1711} 1974}
1712 1975
1713struct clk_ops tegra_dtv_clk_ops = {
1714 .init = &tegra30_periph_clk_init,
1715 .enable = &tegra30_periph_clk_enable,
1716 .disable = &tegra30_periph_clk_disable,
1717 .set_parent = &tegra30_periph_clk_set_parent,
1718 .set_rate = &tegra30_periph_clk_set_rate,
1719 .round_rate = &tegra30_periph_clk_round_rate,
1720 .clk_cfg_ex = &tegra30_dtv_clk_cfg_ex,
1721 .reset = &tegra30_periph_clk_reset,
1722};
1723
1724static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
1725{
1726 const struct clk_mux_sel *sel;
1727 struct clk *d = tegra_get_clock_by_name("pll_d");
1728
1729 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1730
1731 for (sel = c->inputs; sel->input != NULL; sel++) {
1732 if (sel->input == p) {
1733 if (c->refcnt)
1734 clk_enable(p);
1735
1736 /* The DSIB parent selection bit is in PLLD base
1737 register - can not do direct r-m-w, must be
1738 protected by PLLD lock */
1739 tegra_clk_cfg_ex(
1740 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
1741
1742 if (c->refcnt && c->parent)
1743 clk_disable(c->parent);
1744
1745 clk_reparent(c, p);
1746 return 0;
1747 }
1748 }
1749
1750 return -EINVAL;
1751}
1752
1753struct clk_ops tegra_dsib_clk_ops = {
1754 .init = &tegra30_periph_clk_init,
1755 .enable = &tegra30_periph_clk_enable,
1756 .disable = &tegra30_periph_clk_disable,
1757 .set_parent = &tegra30_dsib_clk_set_parent,
1758 .set_rate = &tegra30_periph_clk_set_rate,
1759 .round_rate = &tegra30_periph_clk_round_rate,
1760 .reset = &tegra30_periph_clk_reset,
1761};
1762
1763/* pciex clock support only reset function */
1764struct clk_ops tegra_pciex_clk_ops = {
1765 .reset = tegra30_periph_clk_reset,
1766};
1767
1768/* Output clock ops */ 1976/* Output clock ops */
1769 1977
1770static DEFINE_SPINLOCK(clk_out_lock); 1978static DEFINE_SPINLOCK(clk_out_lock);
1771 1979
1772static void tegra30_clk_out_init(struct clk *c) 1980static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
1773{ 1981{
1774 const struct clk_mux_sel *mux = 0; 1982 struct clk_tegra *c = to_clk_tegra(hw);
1775 const struct clk_mux_sel *sel;
1776 u32 val = pmc_readl(c->reg); 1983 u32 val = pmc_readl(c->reg);
1777 1984
1778 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; 1985 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
1779 c->mul = 1; 1986 c->mul = 1;
1780 c->div = 1; 1987 c->div = 1;
1781 1988 return c->state;
1782 for (sel = c->inputs; sel->input != NULL; sel++) {
1783 if (((val & periph_clk_source_mask(c)) >>
1784 periph_clk_source_shift(c)) == sel->value)
1785 mux = sel;
1786 }
1787 BUG_ON(!mux);
1788 c->parent = mux->input;
1789} 1989}
1790 1990
1791static int tegra30_clk_out_enable(struct clk *c) 1991static int tegra30_clk_out_enable(struct clk_hw *hw)
1792{ 1992{
1993 struct clk_tegra *c = to_clk_tegra(hw);
1793 u32 val; 1994 u32 val;
1794 unsigned long flags; 1995 unsigned long flags;
1795 1996
1796 pr_debug("%s on clock %s\n", __func__, c->name);
1797
1798 spin_lock_irqsave(&clk_out_lock, flags); 1997 spin_lock_irqsave(&clk_out_lock, flags);
1799 val = pmc_readl(c->reg); 1998 val = pmc_readl(c->reg);
1800 val |= (0x1 << c->u.periph.clk_num); 1999 val |= (0x1 << c->u.periph.clk_num);
@@ -1804,13 +2003,12 @@ static int tegra30_clk_out_enable(struct clk *c)
1804 return 0; 2003 return 0;
1805} 2004}
1806 2005
1807static void tegra30_clk_out_disable(struct clk *c) 2006static void tegra30_clk_out_disable(struct clk_hw *hw)
1808{ 2007{
2008 struct clk_tegra *c = to_clk_tegra(hw);
1809 u32 val; 2009 u32 val;
1810 unsigned long flags; 2010 unsigned long flags;
1811 2011
1812 pr_debug("%s on clock %s\n", __func__, c->name);
1813
1814 spin_lock_irqsave(&clk_out_lock, flags); 2012 spin_lock_irqsave(&clk_out_lock, flags);
1815 val = pmc_readl(c->reg); 2013 val = pmc_readl(c->reg);
1816 val &= ~(0x1 << c->u.periph.clk_num); 2014 val &= ~(0x1 << c->u.periph.clk_num);
@@ -1818,58 +2016,59 @@ static void tegra30_clk_out_disable(struct clk *c)
1818 spin_unlock_irqrestore(&clk_out_lock, flags); 2016 spin_unlock_irqrestore(&clk_out_lock, flags);
1819} 2017}
1820 2018
1821static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p) 2019static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
1822{ 2020{
2021 struct clk_tegra *c = to_clk_tegra(hw);
1823 u32 val; 2022 u32 val;
1824 unsigned long flags; 2023 unsigned long flags;
1825 const struct clk_mux_sel *sel;
1826 2024
1827 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 2025 spin_lock_irqsave(&clk_out_lock, flags);
1828 2026 val = pmc_readl(c->reg);
1829 for (sel = c->inputs; sel->input != NULL; sel++) { 2027 val &= ~periph_clk_source_mask(c);
1830 if (sel->input == p) { 2028 val |= (index << periph_clk_source_shift(c));
1831 if (c->refcnt) 2029 pmc_writel(val, c->reg);
1832 clk_enable(p); 2030 spin_unlock_irqrestore(&clk_out_lock, flags);
1833 2031
1834 spin_lock_irqsave(&clk_out_lock, flags); 2032 return 0;
1835 val = pmc_readl(c->reg); 2033}
1836 val &= ~periph_clk_source_mask(c);
1837 val |= (sel->value << periph_clk_source_shift(c));
1838 pmc_writel(val, c->reg);
1839 spin_unlock_irqrestore(&clk_out_lock, flags);
1840 2034
1841 if (c->refcnt && c->parent) 2035static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
1842 clk_disable(c->parent); 2036{
2037 struct clk_tegra *c = to_clk_tegra(hw);
2038 u32 val = pmc_readl(c->reg);
2039 int source;
1843 2040
1844 clk_reparent(c, p); 2041 source = (val & periph_clk_source_mask(c)) >>
1845 return 0; 2042 periph_clk_source_shift(c);
1846 } 2043 return source;
1847 }
1848 return -EINVAL;
1849} 2044}
1850 2045
1851struct clk_ops tegra_clk_out_ops = { 2046struct clk_ops tegra_clk_out_ops = {
1852 .init = &tegra30_clk_out_init, 2047 .is_enabled = tegra30_clk_out_is_enabled,
1853 .enable = &tegra30_clk_out_enable, 2048 .enable = tegra30_clk_out_enable,
1854 .disable = &tegra30_clk_out_disable, 2049 .disable = tegra30_clk_out_disable,
1855 .set_parent = &tegra30_clk_out_set_parent, 2050 .set_parent = tegra30_clk_out_set_parent,
2051 .get_parent = tegra30_clk_out_get_parent,
2052 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1856}; 2053};
1857 2054
1858/* Clock doubler ops */ 2055/* Clock doubler ops */
1859static void tegra30_clk_double_init(struct clk *c) 2056static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
1860{ 2057{
1861 u32 val = clk_readl(c->reg); 2058 struct clk_tegra *c = to_clk_tegra(hw);
1862 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; 2059
1863 c->div = 1;
1864 c->state = ON; 2060 c->state = ON;
1865 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 2061 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1866 c->state = OFF; 2062 c->state = OFF;
2063 return c->state;
1867}; 2064};
1868 2065
1869static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate) 2066static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2067 unsigned long parent_rate)
1870{ 2068{
2069 struct clk_tegra *c = to_clk_tegra(hw);
1871 u32 val; 2070 u32 val;
1872 unsigned long parent_rate = clk_get_rate(c->parent); 2071
1873 if (rate == parent_rate) { 2072 if (rate == parent_rate) {
1874 val = clk_readl(c->reg) | (0x1 << c->reg_shift); 2073 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
1875 clk_writel(val, c->reg); 2074 clk_writel(val, c->reg);
@@ -1886,108 +2085,139 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
1886 return -EINVAL; 2085 return -EINVAL;
1887} 2086}
1888 2087
1889struct clk_ops tegra30_clk_double_ops = { 2088static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
1890 .init = &tegra30_clk_double_init, 2089 unsigned long parent_rate)
1891 .enable = &tegra30_periph_clk_enable, 2090{
1892 .disable = &tegra30_periph_clk_disable, 2091 struct clk_tegra *c = to_clk_tegra(hw);
1893 .set_rate = &tegra30_clk_double_set_rate, 2092 u64 rate = parent_rate;
1894};
1895 2093
1896/* Audio sync clock ops */ 2094 u32 val = clk_readl(c->reg);
1897static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate) 2095 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2096 c->div = 1;
2097
2098 if (c->mul != 0 && c->div != 0) {
2099 rate *= c->mul;
2100 rate += c->div - 1; /* round up */
2101 do_div(rate, c->div);
2102 }
2103
2104 return rate;
2105}
2106
2107static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2108 unsigned long *prate)
1898{ 2109{
1899 c->rate = rate; 2110 unsigned long output_rate = *prate;
1900 return 0; 2111
2112 do_div(output_rate, 2);
2113 return output_rate;
1901} 2114}
1902 2115
2116struct clk_ops tegra30_clk_double_ops = {
2117 .is_enabled = tegra30_clk_double_is_enabled,
2118 .enable = tegra30_periph_clk_enable,
2119 .disable = tegra30_periph_clk_disable,
2120 .recalc_rate = tegra30_clk_double_recalc_rate,
2121 .round_rate = tegra30_clk_double_round_rate,
2122 .set_rate = tegra30_clk_double_set_rate,
2123};
2124
2125/* Audio sync clock ops */
1903struct clk_ops tegra_sync_source_ops = { 2126struct clk_ops tegra_sync_source_ops = {
1904 .set_rate = &tegra30_sync_source_set_rate, 2127 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1905}; 2128};
1906 2129
1907static void tegra30_audio_sync_clk_init(struct clk *c) 2130static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
1908{ 2131{
1909 int source; 2132 struct clk_tegra *c = to_clk_tegra(hw);
1910 const struct clk_mux_sel *sel;
1911 u32 val = clk_readl(c->reg); 2133 u32 val = clk_readl(c->reg);
1912 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; 2134 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
1913 source = val & AUDIO_SYNC_SOURCE_MASK; 2135 return c->state;
1914 for (sel = c->inputs; sel->input != NULL; sel++)
1915 if (sel->value == source)
1916 break;
1917 BUG_ON(sel->input == NULL);
1918 c->parent = sel->input;
1919} 2136}
1920 2137
1921static int tegra30_audio_sync_clk_enable(struct clk *c) 2138static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
1922{ 2139{
2140 struct clk_tegra *c = to_clk_tegra(hw);
1923 u32 val = clk_readl(c->reg); 2141 u32 val = clk_readl(c->reg);
1924 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); 2142 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
1925 return 0; 2143 return 0;
1926} 2144}
1927 2145
1928static void tegra30_audio_sync_clk_disable(struct clk *c) 2146static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
1929{ 2147{
2148 struct clk_tegra *c = to_clk_tegra(hw);
1930 u32 val = clk_readl(c->reg); 2149 u32 val = clk_readl(c->reg);
1931 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); 2150 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
1932} 2151}
1933 2152
1934static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p) 2153static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1935{ 2154{
2155 struct clk_tegra *c = to_clk_tegra(hw);
1936 u32 val; 2156 u32 val;
1937 const struct clk_mux_sel *sel;
1938 for (sel = c->inputs; sel->input != NULL; sel++) {
1939 if (sel->input == p) {
1940 val = clk_readl(c->reg);
1941 val &= ~AUDIO_SYNC_SOURCE_MASK;
1942 val |= sel->value;
1943
1944 if (c->refcnt)
1945 clk_enable(p);
1946 2157
1947 clk_writel(val, c->reg); 2158 val = clk_readl(c->reg);
2159 val &= ~AUDIO_SYNC_SOURCE_MASK;
2160 val |= index;
1948 2161
1949 if (c->refcnt && c->parent) 2162 clk_writel(val, c->reg);
1950 clk_disable(c->parent); 2163 return 0;
2164}
1951 2165
1952 clk_reparent(c, p); 2166static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
1953 return 0; 2167{
1954 } 2168 struct clk_tegra *c = to_clk_tegra(hw);
1955 } 2169 u32 val = clk_readl(c->reg);
2170 int source;
1956 2171
1957 return -EINVAL; 2172 source = val & AUDIO_SYNC_SOURCE_MASK;
2173 return source;
1958} 2174}
1959 2175
1960struct clk_ops tegra30_audio_sync_clk_ops = { 2176struct clk_ops tegra30_audio_sync_clk_ops = {
1961 .init = tegra30_audio_sync_clk_init, 2177 .is_enabled = tegra30_audio_sync_clk_is_enabled,
1962 .enable = tegra30_audio_sync_clk_enable, 2178 .enable = tegra30_audio_sync_clk_enable,
1963 .disable = tegra30_audio_sync_clk_disable, 2179 .disable = tegra30_audio_sync_clk_disable,
1964 .set_parent = tegra30_audio_sync_clk_set_parent, 2180 .set_parent = tegra30_audio_sync_clk_set_parent,
2181 .get_parent = tegra30_audio_sync_clk_get_parent,
2182 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1965}; 2183};
1966 2184
1967/* cml0 (pcie), and cml1 (sata) clock ops */ 2185/* cml0 (pcie), and cml1 (sata) clock ops */
1968static void tegra30_cml_clk_init(struct clk *c) 2186static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
1969{ 2187{
2188 struct clk_tegra *c = to_clk_tegra(hw);
1970 u32 val = clk_readl(c->reg); 2189 u32 val = clk_readl(c->reg);
1971 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; 2190 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2191 return c->state;
1972} 2192}
1973 2193
1974static int tegra30_cml_clk_enable(struct clk *c) 2194static int tegra30_cml_clk_enable(struct clk_hw *hw)
1975{ 2195{
2196 struct clk_tegra *c = to_clk_tegra(hw);
2197
1976 u32 val = clk_readl(c->reg); 2198 u32 val = clk_readl(c->reg);
1977 val |= (0x1 << c->u.periph.clk_num); 2199 val |= (0x1 << c->u.periph.clk_num);
1978 clk_writel(val, c->reg); 2200 clk_writel(val, c->reg);
2201
1979 return 0; 2202 return 0;
1980} 2203}
1981 2204
1982static void tegra30_cml_clk_disable(struct clk *c) 2205static void tegra30_cml_clk_disable(struct clk_hw *hw)
1983{ 2206{
2207 struct clk_tegra *c = to_clk_tegra(hw);
2208
1984 u32 val = clk_readl(c->reg); 2209 u32 val = clk_readl(c->reg);
1985 val &= ~(0x1 << c->u.periph.clk_num); 2210 val &= ~(0x1 << c->u.periph.clk_num);
1986 clk_writel(val, c->reg); 2211 clk_writel(val, c->reg);
1987} 2212}
1988 2213
1989struct clk_ops tegra_cml_clk_ops = { 2214struct clk_ops tegra_cml_clk_ops = {
1990 .init = &tegra30_cml_clk_init, 2215 .is_enabled = tegra30_cml_clk_is_enabled,
1991 .enable = &tegra30_cml_clk_enable, 2216 .enable = tegra30_cml_clk_enable,
1992 .disable = &tegra30_cml_clk_disable, 2217 .disable = tegra30_cml_clk_disable,
2218 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2219};
2220
2221struct clk_ops tegra_pciex_clk_ops = {
2222 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1993}; 2223};
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index f8c4df5f53f7..aeb4e963f632 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -17,6 +17,7 @@
17#ifndef __MACH_TEGRA30_CLOCK_H 17#ifndef __MACH_TEGRA30_CLOCK_H
18#define __MACH_TEGRA30_CLOCK_H 18#define __MACH_TEGRA30_CLOCK_H
19 19
20extern struct clk_ops tegra_clk_32k_ops;
20extern struct clk_ops tegra30_clk_m_ops; 21extern struct clk_ops tegra30_clk_m_ops;
21extern struct clk_ops tegra_clk_m_div_ops; 22extern struct clk_ops tegra_clk_m_div_ops;
22extern struct clk_ops tegra_pll_ref_ops; 23extern struct clk_ops tegra_pll_ref_ops;
@@ -27,17 +28,26 @@ extern struct clk_ops tegra30_plle_ops;
27extern struct clk_ops tegra_cml_clk_ops; 28extern struct clk_ops tegra_cml_clk_ops;
28extern struct clk_ops tegra_pciex_clk_ops; 29extern struct clk_ops tegra_pciex_clk_ops;
29extern struct clk_ops tegra_sync_source_ops; 30extern struct clk_ops tegra_sync_source_ops;
30extern struct clk_ops tegra30_audio_sync_clk_ops; 31extern struct clk_ops tegra_audio_sync_clk_ops;
31extern struct clk_ops tegra30_clk_double_ops; 32extern struct clk_ops tegra30_clk_double_ops;
32extern struct clk_ops tegra_clk_out_ops; 33extern struct clk_ops tegra_clk_out_ops;
33extern struct clk_ops tegra30_super_ops; 34extern struct clk_ops tegra30_super_ops;
34extern struct clk_ops tegra30_blink_clk_ops; 35extern struct clk_ops tegra30_blink_clk_ops;
35extern struct clk_ops tegra30_twd_ops; 36extern struct clk_ops tegra30_twd_ops;
36extern struct clk_ops tegra30_periph_clk_ops; 37extern struct clk_ops tegra30_periph_clk_ops;
37extern struct clk_ops tegra_dsib_clk_ops; 38extern struct clk_ops tegra30_dsib_clk_ops;
38extern struct clk_ops tegra_nand_clk_ops; 39extern struct clk_ops tegra_nand_clk_ops;
39extern struct clk_ops tegra_vi_clk_ops; 40extern struct clk_ops tegra_vi_clk_ops;
40extern struct clk_ops tegra_dtv_clk_ops; 41extern struct clk_ops tegra_dtv_clk_ops;
41extern struct clk_ops tegra_clk_shared_bus_ops; 42extern struct clk_ops tegra_clk_shared_bus_ops;
42 43
44int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
45 enum tegra_clk_ex_param p, u32 setting);
46void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
47int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
48 enum tegra_clk_ex_param p, u32 setting);
49int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
50 enum tegra_clk_ex_param p, u32 setting);
51int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
52 enum tegra_clk_ex_param p, u32 setting);
43#endif 53#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index b1243c9e8ef7..c924240cb693 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-tegra/tegra30_clocks_data.c 2 * arch/arm/mach-tegra/tegra30_clocks.c
3 * 3 *
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
18 * 18 *
19 */ 19 */
20 20
21#include <linux/clk-private.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
22#include <linux/module.h> 23#include <linux/module.h>
23#include <linux/list.h> 24#include <linux/list.h>
@@ -28,69 +29,165 @@
28#include <linux/clk.h> 29#include <linux/clk.h>
29#include <linux/cpufreq.h> 30#include <linux/cpufreq.h>
30 31
31#include <asm/clkdev.h>
32
33#include <mach/iomap.h>
34
35#include "clock.h" 32#include "clock.h"
36#include "fuse.h" 33#include "fuse.h"
37#include "tegra30_clocks.h" 34#include "tegra30_clocks.h"
38 35
39/* Clock definitions */ 36#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
37 _parent_names, _parents, _parent) \
38 static struct clk tegra_##_name = { \
39 .hw = &tegra_##_name##_hw.hw, \
40 .name = #_name, \
41 .rate = _rate, \
42 .ops = _ops, \
43 .flags = _flags, \
44 .parent_names = _parent_names, \
45 .parents = _parents, \
46 .num_parents = ARRAY_SIZE(_parent_names), \
47 .parent = _parent, \
48 };
49
50static struct clk tegra_clk_32k;
51static struct clk_tegra tegra_clk_32k_hw = {
52 .hw = {
53 .clk = &tegra_clk_32k,
54 },
55 .fixed_rate = 32768,
56};
40static struct clk tegra_clk_32k = { 57static struct clk tegra_clk_32k = {
41 .name = "clk_32k", 58 .name = "clk_32k",
42 .rate = 32768, 59 .hw = &tegra_clk_32k_hw.hw,
43 .ops = NULL, 60 .ops = &tegra_clk_32k_ops,
44 .max_rate = 32768, 61 .flags = CLK_IS_ROOT,
45}; 62};
46 63
47static struct clk tegra_clk_m = { 64static struct clk tegra_clk_m;
48 .name = "clk_m", 65static struct clk_tegra tegra_clk_m_hw = {
49 .flags = ENABLE_ON_INIT, 66 .hw = {
50 .ops = &tegra30_clk_m_ops, 67 .clk = &tegra_clk_m,
51 .reg = 0x1fc, 68 },
69 .flags = ENABLE_ON_INIT,
70 .reg = 0x1fc,
52 .reg_shift = 28, 71 .reg_shift = 28,
53 .max_rate = 48000000, 72 .max_rate = 48000000,
73};
74static struct clk tegra_clk_m = {
75 .name = "clk_m",
76 .hw = &tegra_clk_m_hw.hw,
77 .ops = &tegra30_clk_m_ops,
78 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
54}; 79};
55 80
56static struct clk tegra_clk_m_div2 = { 81static const char *clk_m_div_parent_names[] = {
57 .name = "clk_m_div2", 82 "clk_m",
58 .ops = &tegra_clk_m_div_ops,
59 .parent = &tegra_clk_m,
60 .mul = 1,
61 .div = 2,
62 .state = ON,
63 .max_rate = 24000000,
64}; 83};
65 84
66static struct clk tegra_clk_m_div4 = { 85static struct clk *clk_m_div_parents[] = {
67 .name = "clk_m_div4", 86 &tegra_clk_m,
68 .ops = &tegra_clk_m_div_ops,
69 .parent = &tegra_clk_m,
70 .mul = 1,
71 .div = 4,
72 .state = ON,
73 .max_rate = 12000000,
74}; 87};
75 88
76static struct clk tegra_pll_ref = { 89static struct clk tegra_clk_m_div2;
77 .name = "pll_ref", 90static struct clk_tegra tegra_clk_m_div2_hw = {
78 .flags = ENABLE_ON_INIT, 91 .hw = {
79 .ops = &tegra_pll_ref_ops, 92 .clk = &tegra_clk_m_div2,
80 .parent = &tegra_clk_m, 93 },
81 .max_rate = 26000000, 94 .mul = 1,
95 .div = 2,
96 .max_rate = 24000000,
97};
98DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
99 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
100
101static struct clk tegra_clk_m_div4;
102static struct clk_tegra tegra_clk_m_div4_hw = {
103 .hw = {
104 .clk = &tegra_clk_m_div4,
105 },
106 .mul = 1,
107 .div = 4,
108 .max_rate = 12000000,
82}; 109};
110DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
111 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
112
113static struct clk tegra_pll_ref;
114static struct clk_tegra tegra_pll_ref_hw = {
115 .hw = {
116 .clk = &tegra_pll_ref,
117 },
118 .flags = ENABLE_ON_INIT,
119 .max_rate = 26000000,
120};
121DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
122 clk_m_div_parents, &tegra_clk_m);
123
124#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
125 _input_max, _cf_min, _cf_max, _vco_min, \
126 _vco_max, _freq_table, _lock_delay, _ops, \
127 _fixed_rate, _clk_cfg_ex, _parent) \
128 static struct clk tegra_##_name; \
129 static const char *_name##_parent_names[] = { \
130 #_parent, \
131 }; \
132 static struct clk *_name##_parents[] = { \
133 &tegra_##_parent, \
134 }; \
135 static struct clk_tegra tegra_##_name##_hw = { \
136 .hw = { \
137 .clk = &tegra_##_name, \
138 }, \
139 .flags = _flags, \
140 .reg = _reg, \
141 .max_rate = _max_rate, \
142 .u.pll = { \
143 .input_min = _input_min, \
144 .input_max = _input_max, \
145 .cf_min = _cf_min, \
146 .cf_max = _cf_max, \
147 .vco_min = _vco_min, \
148 .vco_max = _vco_max, \
149 .freq_table = _freq_table, \
150 .lock_delay = _lock_delay, \
151 .fixed_rate = _fixed_rate, \
152 }, \
153 .clk_cfg_ex = _clk_cfg_ex, \
154 }; \
155 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
156 _name##_parent_names, _name##_parents, \
157 &tegra_##_parent);
158
159#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
160 _max_rate, _ops, _parent, _clk_flags) \
161 static const char *_name##_parent_names[] = { \
162 #_parent, \
163 }; \
164 static struct clk *_name##_parents[] = { \
165 &tegra_##_parent, \
166 }; \
167 static struct clk tegra_##_name; \
168 static struct clk_tegra tegra_##_name##_hw = { \
169 .hw = { \
170 .clk = &tegra_##_name, \
171 }, \
172 .flags = _flags, \
173 .reg = _reg, \
174 .max_rate = _max_rate, \
175 .reg_shift = _reg_shift, \
176 }; \
177 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
178 _clk_flags, _name##_parent_names, \
179 _name##_parents, &tegra_##_parent);
83 180
84static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { 181static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
85 { 12000000, 1040000000, 520, 6, 1, 8}, 182 { 12000000, 1040000000, 520, 6, 1, 8},
86 { 13000000, 1040000000, 480, 6, 1, 8}, 183 { 13000000, 1040000000, 480, 6, 1, 8},
87 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ 184 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
88 { 19200000, 1040000000, 325, 6, 1, 6}, 185 { 19200000, 1040000000, 325, 6, 1, 6},
89 { 26000000, 1040000000, 520, 13, 1, 8}, 186 { 26000000, 1040000000, 520, 13, 1, 8},
90 187
91 { 12000000, 832000000, 416, 6, 1, 8}, 188 { 12000000, 832000000, 416, 6, 1, 8},
92 { 13000000, 832000000, 832, 13, 1, 8}, 189 { 13000000, 832000000, 832, 13, 1, 8},
93 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ 190 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
94 { 19200000, 832000000, 260, 6, 1, 8}, 191 { 19200000, 832000000, 260, 6, 1, 8},
95 { 26000000, 832000000, 416, 13, 1, 8}, 192 { 26000000, 832000000, 416, 13, 1, 8},
96 193
@@ -108,46 +205,24 @@ static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
108 205
109 { 12000000, 520000000, 520, 12, 1, 8}, 206 { 12000000, 520000000, 520, 12, 1, 8},
110 { 13000000, 520000000, 520, 13, 1, 8}, 207 { 13000000, 520000000, 520, 13, 1, 8},
111 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ 208 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
112 { 19200000, 520000000, 325, 12, 1, 6}, 209 { 19200000, 520000000, 325, 12, 1, 6},
113 { 26000000, 520000000, 520, 26, 1, 8}, 210 { 26000000, 520000000, 520, 26, 1, 8},
114 211
115 { 12000000, 416000000, 416, 12, 1, 8}, 212 { 12000000, 416000000, 416, 12, 1, 8},
116 { 13000000, 416000000, 416, 13, 1, 8}, 213 { 13000000, 416000000, 416, 13, 1, 8},
117 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ 214 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
118 { 19200000, 416000000, 260, 12, 1, 6}, 215 { 19200000, 416000000, 260, 12, 1, 6},
119 { 26000000, 416000000, 416, 26, 1, 8}, 216 { 26000000, 416000000, 416, 26, 1, 8},
120 { 0, 0, 0, 0, 0, 0 }, 217 { 0, 0, 0, 0, 0, 0 },
121}; 218};
122 219
123static struct clk tegra_pll_c = { 220DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
124 .name = "pll_c", 221 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
125 .flags = PLL_HAS_CPCON, 222 tegra30_pll_ops, 0, NULL, pll_ref);
126 .ops = &tegra30_pll_ops,
127 .reg = 0x80,
128 .parent = &tegra_pll_ref,
129 .max_rate = 1400000000,
130 .u.pll = {
131 .input_min = 2000000,
132 .input_max = 31000000,
133 .cf_min = 1000000,
134 .cf_max = 6000000,
135 .vco_min = 20000000,
136 .vco_max = 1400000000,
137 .freq_table = tegra_pll_c_freq_table,
138 .lock_delay = 300,
139 },
140};
141 223
142static struct clk tegra_pll_c_out1 = { 224DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
143 .name = "pll_c_out1", 225 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
144 .ops = &tegra30_pll_div_ops,
145 .flags = DIV_U71,
146 .parent = &tegra_pll_c,
147 .reg = 0x84,
148 .reg_shift = 0,
149 .max_rate = 700000000,
150};
151 226
152static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { 227static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
153 { 12000000, 666000000, 666, 12, 1, 8}, 228 { 12000000, 666000000, 666, 12, 1, 8},
@@ -163,34 +238,12 @@ static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
163 { 0, 0, 0, 0, 0, 0 }, 238 { 0, 0, 0, 0, 0, 0 },
164}; 239};
165 240
166static struct clk tegra_pll_m = { 241DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
167 .name = "pll_m", 242 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
168 .flags = PLL_HAS_CPCON | PLLM, 243 300, tegra30_pll_ops, 0, NULL, pll_ref);
169 .ops = &tegra30_pll_ops,
170 .reg = 0x90,
171 .parent = &tegra_pll_ref,
172 .max_rate = 800000000,
173 .u.pll = {
174 .input_min = 2000000,
175 .input_max = 31000000,
176 .cf_min = 1000000,
177 .cf_max = 6000000,
178 .vco_min = 20000000,
179 .vco_max = 1200000000,
180 .freq_table = tegra_pll_m_freq_table,
181 .lock_delay = 300,
182 },
183};
184 244
185static struct clk tegra_pll_m_out1 = { 245DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
186 .name = "pll_m_out1", 246 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
187 .ops = &tegra30_pll_div_ops,
188 .flags = DIV_U71,
189 .parent = &tegra_pll_m,
190 .reg = 0x94,
191 .reg_shift = 0,
192 .max_rate = 600000000,
193};
194 247
195static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { 248static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
196 { 12000000, 216000000, 432, 12, 2, 8}, 249 { 12000000, 216000000, 432, 12, 2, 8},
@@ -201,65 +254,19 @@ static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
201 { 0, 0, 0, 0, 0, 0 }, 254 { 0, 0, 0, 0, 0, 0 },
202}; 255};
203 256
204static struct clk tegra_pll_p = { 257DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
205 .name = "pll_p", 258 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
206 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 259 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
207 .ops = &tegra30_pll_ops, 260 pll_ref);
208 .reg = 0xa0,
209 .parent = &tegra_pll_ref,
210 .max_rate = 432000000,
211 .u.pll = {
212 .input_min = 2000000,
213 .input_max = 31000000,
214 .cf_min = 1000000,
215 .cf_max = 6000000,
216 .vco_min = 20000000,
217 .vco_max = 1400000000,
218 .freq_table = tegra_pll_p_freq_table,
219 .lock_delay = 300,
220 .fixed_rate = 408000000,
221 },
222};
223 261
224static struct clk tegra_pll_p_out1 = { 262DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
225 .name = "pll_p_out1", 263 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
226 .ops = &tegra30_pll_div_ops, 264DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
227 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 265 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
228 .parent = &tegra_pll_p, 266DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
229 .reg = 0xa4, 267 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
230 .reg_shift = 0, 268DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
231 .max_rate = 432000000, 269 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
232};
233
234static struct clk tegra_pll_p_out2 = {
235 .name = "pll_p_out2",
236 .ops = &tegra30_pll_div_ops,
237 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
238 .parent = &tegra_pll_p,
239 .reg = 0xa4,
240 .reg_shift = 16,
241 .max_rate = 432000000,
242};
243
244static struct clk tegra_pll_p_out3 = {
245 .name = "pll_p_out3",
246 .ops = &tegra30_pll_div_ops,
247 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
248 .parent = &tegra_pll_p,
249 .reg = 0xa8,
250 .reg_shift = 0,
251 .max_rate = 432000000,
252};
253
254static struct clk tegra_pll_p_out4 = {
255 .name = "pll_p_out4",
256 .ops = &tegra30_pll_div_ops,
257 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
258 .parent = &tegra_pll_p,
259 .reg = 0xa8,
260 .reg_shift = 16,
261 .max_rate = 432000000,
262};
263 270
264static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { 271static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
265 { 9600000, 564480000, 294, 5, 1, 4}, 272 { 9600000, 564480000, 294, 5, 1, 4},
@@ -272,34 +279,12 @@ static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
272 { 0, 0, 0, 0, 0, 0 }, 279 { 0, 0, 0, 0, 0, 0 },
273}; 280};
274 281
275static struct clk tegra_pll_a = { 282DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
276 .name = "pll_a", 283 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
277 .flags = PLL_HAS_CPCON, 284 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
278 .ops = &tegra30_pll_ops,
279 .reg = 0xb0,
280 .parent = &tegra_pll_p_out1,
281 .max_rate = 700000000,
282 .u.pll = {
283 .input_min = 2000000,
284 .input_max = 31000000,
285 .cf_min = 1000000,
286 .cf_max = 6000000,
287 .vco_min = 20000000,
288 .vco_max = 1400000000,
289 .freq_table = tegra_pll_a_freq_table,
290 .lock_delay = 300,
291 },
292};
293 285
294static struct clk tegra_pll_a_out0 = { 286DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
295 .name = "pll_a_out0", 287 pll_a, CLK_IGNORE_UNUSED);
296 .ops = &tegra30_pll_div_ops,
297 .flags = DIV_U71,
298 .parent = &tegra_pll_a,
299 .reg = 0xb4,
300 .reg_shift = 0,
301 .max_rate = 100000000,
302};
303 288
304static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { 289static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
305 { 12000000, 216000000, 216, 12, 1, 4}, 290 { 12000000, 216000000, 216, 12, 1, 4},
@@ -322,59 +307,20 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
322 { 0, 0, 0, 0, 0, 0 }, 307 { 0, 0, 0, 0, 0, 0 },
323}; 308};
324 309
325static struct clk tegra_pll_d = { 310DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
326 .name = "pll_d", 311 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
327 .flags = PLL_HAS_CPCON | PLLD, 312 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
328 .ops = &tegra_plld_ops,
329 .reg = 0xd0,
330 .parent = &tegra_pll_ref,
331 .max_rate = 1000000000,
332 .u.pll = {
333 .input_min = 2000000,
334 .input_max = 40000000,
335 .cf_min = 1000000,
336 .cf_max = 6000000,
337 .vco_min = 40000000,
338 .vco_max = 1000000000,
339 .freq_table = tegra_pll_d_freq_table,
340 .lock_delay = 1000,
341 },
342};
343 313
344static struct clk tegra_pll_d_out0 = { 314DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
345 .name = "pll_d_out0", 315 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
346 .ops = &tegra30_pll_div_ops,
347 .flags = DIV_2 | PLLD,
348 .parent = &tegra_pll_d,
349 .max_rate = 500000000,
350};
351
352static struct clk tegra_pll_d2 = {
353 .name = "pll_d2",
354 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
355 .ops = &tegra_plld_ops,
356 .reg = 0x4b8,
357 .parent = &tegra_pll_ref,
358 .max_rate = 1000000000,
359 .u.pll = {
360 .input_min = 2000000,
361 .input_max = 40000000,
362 .cf_min = 1000000,
363 .cf_max = 6000000,
364 .vco_min = 40000000,
365 .vco_max = 1000000000,
366 .freq_table = tegra_pll_d_freq_table,
367 .lock_delay = 1000,
368 },
369};
370 316
371static struct clk tegra_pll_d2_out0 = { 317DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
372 .name = "pll_d2_out0", 318 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
373 .ops = &tegra30_pll_div_ops, 319 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
374 .flags = DIV_2 | PLLD, 320 pll_ref);
375 .parent = &tegra_pll_d2, 321
376 .max_rate = 500000000, 322DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
377}; 323 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
378 324
379static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { 325static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
380 { 12000000, 480000000, 960, 12, 2, 12}, 326 { 12000000, 480000000, 960, 12, 2, 12},
@@ -385,24 +331,9 @@ static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
385 { 0, 0, 0, 0, 0, 0 }, 331 { 0, 0, 0, 0, 0, 0 },
386}; 332};
387 333
388static struct clk tegra_pll_u = { 334DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
389 .name = "pll_u", 335 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
390 .flags = PLL_HAS_CPCON | PLLU, 336 1000, tegra30_pll_ops, 0, NULL, pll_ref);
391 .ops = &tegra30_pll_ops,
392 .reg = 0xc0,
393 .parent = &tegra_pll_ref,
394 .max_rate = 480000000,
395 .u.pll = {
396 .input_min = 2000000,
397 .input_max = 40000000,
398 .cf_min = 1000000,
399 .cf_max = 6000000,
400 .vco_min = 480000000,
401 .vco_max = 960000000,
402 .freq_table = tegra_pll_u_freq_table,
403 .lock_delay = 1000,
404 },
405};
406 337
407static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { 338static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
408 /* 1.7 GHz */ 339 /* 1.7 GHz */
@@ -464,33 +395,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
464 { 0, 0, 0, 0, 0, 0 }, 395 { 0, 0, 0, 0, 0, 0 },
465}; 396};
466 397
467static struct clk tegra_pll_x = { 398DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
468 .name = "pll_x", 399 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
469 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 400 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
470 .ops = &tegra30_pll_ops,
471 .reg = 0xe0,
472 .parent = &tegra_pll_ref,
473 .max_rate = 1700000000,
474 .u.pll = {
475 .input_min = 2000000,
476 .input_max = 31000000,
477 .cf_min = 1000000,
478 .cf_max = 6000000,
479 .vco_min = 20000000,
480 .vco_max = 1700000000,
481 .freq_table = tegra_pll_x_freq_table,
482 .lock_delay = 300,
483 },
484};
485
486static struct clk tegra_pll_x_out0 = {
487 .name = "pll_x_out0",
488 .ops = &tegra30_pll_div_ops,
489 .flags = DIV_2 | PLLX,
490 .parent = &tegra_pll_x,
491 .max_rate = 850000000,
492};
493 401
402DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
403 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
494 404
495static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { 405static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
496 /* PLLE special case: use cpcon field to store cml divider value */ 406 /* PLLE special case: use cpcon field to store cml divider value */
@@ -499,518 +409,835 @@ static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
499 { 0, 0, 0, 0, 0, 0 }, 409 { 0, 0, 0, 0, 0, 0 },
500}; 410};
501 411
502static struct clk tegra_pll_e = { 412DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
503 .name = "pll_e", 413 12000000, 12000000, 1200000000, 2400000000U,
504 .flags = PLL_ALT_MISC_REG, 414 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
505 .ops = &tegra30_plle_ops, 415 pll_ref);
506 .reg = 0xe8, 416
507 .max_rate = 100000000, 417static const char *mux_plle[] = {
508 .u.pll = { 418 "pll_e",
509 .input_min = 12000000, 419};
510 .input_max = 216000000, 420
511 .cf_min = 12000000, 421static struct clk *mux_plle_p[] = {
512 .cf_max = 12000000, 422 &tegra_pll_e,
513 .vco_min = 1200000000,
514 .vco_max = 2400000000U,
515 .freq_table = tegra_pll_e_freq_table,
516 .lock_delay = 300,
517 .fixed_rate = 100000000,
518 },
519}; 423};
520 424
521static struct clk tegra_cml0_clk = { 425static struct clk tegra_cml0;
522 .name = "cml0", 426static struct clk_tegra tegra_cml0_hw = {
523 .parent = &tegra_pll_e, 427 .hw = {
524 .ops = &tegra_cml_clk_ops, 428 .clk = &tegra_cml0,
525 .reg = 0x48c, 429 },
526 .max_rate = 100000000, 430 .reg = 0x48c,
527 .u.periph = { 431 .fixed_rate = 100000000,
432 .u.periph = {
528 .clk_num = 0, 433 .clk_num = 0,
529 }, 434 },
530}; 435};
436DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
437 mux_plle_p, &tegra_pll_e);
531 438
532static struct clk tegra_cml1_clk = { 439static struct clk tegra_cml1;
533 .name = "cml1", 440static struct clk_tegra tegra_cml1_hw = {
534 .parent = &tegra_pll_e, 441 .hw = {
535 .ops = &tegra_cml_clk_ops, 442 .clk = &tegra_cml1,
536 .reg = 0x48c, 443 },
537 .max_rate = 100000000, 444 .reg = 0x48c,
538 .u.periph = { 445 .fixed_rate = 100000000,
539 .clk_num = 1, 446 .u.periph = {
447 .clk_num = 1,
540 }, 448 },
541}; 449};
450DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
451 mux_plle_p, &tegra_pll_e);
542 452
543static struct clk tegra_pciex_clk = { 453static struct clk tegra_pciex;
544 .name = "pciex", 454static struct clk_tegra tegra_pciex_hw = {
545 .parent = &tegra_pll_e, 455 .hw = {
546 .ops = &tegra_pciex_clk_ops, 456 .clk = &tegra_pciex,
547 .max_rate = 100000000, 457 },
548 .u.periph = { 458 .reg = 0x48c,
549 .clk_num = 74, 459 .fixed_rate = 100000000,
460 .reset = tegra30_periph_clk_reset,
461 .u.periph = {
462 .clk_num = 74,
550 }, 463 },
551}; 464};
465DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
466 mux_plle_p, &tegra_pll_e);
552 467
553/* Audio sync clocks */ 468#define SYNC_SOURCE(_name) \
554#define SYNC_SOURCE(_id) \ 469 static struct clk tegra_##_name##_sync; \
555 { \ 470 static struct clk_tegra tegra_##_name##_sync_hw = { \
556 .name = #_id "_sync", \ 471 .hw = { \
557 .rate = 24000000, \ 472 .clk = &tegra_##_name##_sync, \
558 .max_rate = 24000000, \ 473 }, \
559 .ops = &tegra_sync_source_ops \ 474 .max_rate = 24000000, \
560 } 475 .fixed_rate = 24000000, \
561static struct clk tegra_sync_source_list[] = { 476 }; \
562 SYNC_SOURCE(spdif_in), 477 static struct clk tegra_##_name##_sync = { \
563 SYNC_SOURCE(i2s0), 478 .name = #_name "_sync", \
564 SYNC_SOURCE(i2s1), 479 .hw = &tegra_##_name##_sync_hw.hw, \
565 SYNC_SOURCE(i2s2), 480 .ops = &tegra_sync_source_ops, \
566 SYNC_SOURCE(i2s3), 481 .flags = CLK_IS_ROOT, \
567 SYNC_SOURCE(i2s4), 482 };
568 SYNC_SOURCE(vimclk), 483
569}; 484SYNC_SOURCE(spdif_in);
570 485SYNC_SOURCE(i2s0);
571static struct clk_mux_sel mux_audio_sync_clk[] = { 486SYNC_SOURCE(i2s1);
572 { .input = &tegra_sync_source_list[0], .value = 0}, 487SYNC_SOURCE(i2s2);
573 { .input = &tegra_sync_source_list[1], .value = 1}, 488SYNC_SOURCE(i2s3);
574 { .input = &tegra_sync_source_list[2], .value = 2}, 489SYNC_SOURCE(i2s4);
575 { .input = &tegra_sync_source_list[3], .value = 3}, 490SYNC_SOURCE(vimclk);
576 { .input = &tegra_sync_source_list[4], .value = 4}, 491
577 { .input = &tegra_sync_source_list[5], .value = 5}, 492static struct clk *tegra_sync_source_list[] = {
578 { .input = &tegra_pll_a_out0, .value = 6}, 493 &tegra_spdif_in_sync,
579 { .input = &tegra_sync_source_list[6], .value = 7}, 494 &tegra_i2s0_sync,
580 { 0, 0 } 495 &tegra_i2s1_sync,
581}; 496 &tegra_i2s2_sync,
582 497 &tegra_i2s3_sync,
583#define AUDIO_SYNC_CLK(_id, _index) \ 498 &tegra_i2s4_sync,
584 { \ 499 &tegra_vimclk_sync,
585 .name = #_id, \ 500};
586 .inputs = mux_audio_sync_clk, \ 501
587 .reg = 0x4A0 + (_index) * 4, \ 502static const char *mux_audio_sync_clk[] = {
588 .max_rate = 24000000, \ 503 "spdif_in_sync",
589 .ops = &tegra30_audio_sync_clk_ops \ 504 "i2s0_sync",
590 } 505 "i2s1_sync",
591static struct clk tegra_clk_audio_list[] = { 506 "i2s2_sync",
592 AUDIO_SYNC_CLK(audio0, 0), 507 "i2s3_sync",
593 AUDIO_SYNC_CLK(audio1, 1), 508 "i2s4_sync",
594 AUDIO_SYNC_CLK(audio2, 2), 509 "vimclk_sync",
595 AUDIO_SYNC_CLK(audio3, 3), 510};
596 AUDIO_SYNC_CLK(audio4, 4), 511
597 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */ 512#define AUDIO_SYNC_CLK(_name, _index) \
598}; 513 static struct clk tegra_##_name; \
599 514 static struct clk_tegra tegra_##_name##_hw = { \
600#define AUDIO_SYNC_2X_CLK(_id, _index) \ 515 .hw = { \
601 { \ 516 .clk = &tegra_##_name, \
602 .name = #_id "_2x", \ 517 }, \
603 .flags = PERIPH_NO_RESET, \ 518 .max_rate = 24000000, \
604 .max_rate = 48000000, \ 519 .reg = 0x4A0 + (_index) * 4, \
605 .ops = &tegra30_clk_double_ops, \ 520 }; \
606 .reg = 0x49C, \ 521 static struct clk tegra_##_name = { \
522 .name = #_name, \
523 .ops = &tegra_audio_sync_clk_ops, \
524 .hw = &tegra_##_name##_hw.hw, \
525 .parent_names = mux_audio_sync_clk, \
526 .parents = tegra_sync_source_list, \
527 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
528 };
529
530AUDIO_SYNC_CLK(audio0, 0);
531AUDIO_SYNC_CLK(audio1, 1);
532AUDIO_SYNC_CLK(audio2, 2);
533AUDIO_SYNC_CLK(audio3, 3);
534AUDIO_SYNC_CLK(audio4, 4);
535AUDIO_SYNC_CLK(audio5, 5);
536
537static struct clk *tegra_clk_audio_list[] = {
538 &tegra_audio0,
539 &tegra_audio1,
540 &tegra_audio2,
541 &tegra_audio3,
542 &tegra_audio4,
543 &tegra_audio5, /* SPDIF */
544};
545
546#define AUDIO_SYNC_2X_CLK(_name, _index) \
547 static const char *_name##_parent_names[] = { \
548 "tegra_" #_name, \
549 }; \
550 static struct clk *_name##_parents[] = { \
551 &tegra_##_name, \
552 }; \
553 static struct clk tegra_##_name##_2x; \
554 static struct clk_tegra tegra_##_name##_2x_hw = { \
555 .hw = { \
556 .clk = &tegra_##_name##_2x, \
557 }, \
558 .flags = PERIPH_NO_RESET, \
559 .max_rate = 48000000, \
560 .reg = 0x49C, \
607 .reg_shift = 24 + (_index), \ 561 .reg_shift = 24 + (_index), \
608 .parent = &tegra_clk_audio_list[(_index)], \
609 .u.periph = { \ 562 .u.periph = { \
610 .clk_num = 113 + (_index), \ 563 .clk_num = 113 + (_index), \
611 }, \ 564 }, \
612 } 565 }; \
613static struct clk tegra_clk_audio_2x_list[] = { 566 static struct clk tegra_##_name##_2x = { \
614 AUDIO_SYNC_2X_CLK(audio0, 0), 567 .name = #_name "_2x", \
615 AUDIO_SYNC_2X_CLK(audio1, 1), 568 .ops = &tegra30_clk_double_ops, \
616 AUDIO_SYNC_2X_CLK(audio2, 2), 569 .hw = &tegra_##_name##_2x_hw.hw, \
617 AUDIO_SYNC_2X_CLK(audio3, 3), 570 .parent_names = _name##_parent_names, \
618 AUDIO_SYNC_2X_CLK(audio4, 4), 571 .parents = _name##_parents, \
619 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */ 572 .parent = &tegra_##_name, \
620}; 573 .num_parents = 1, \
621 574 };
622#define MUX_I2S_SPDIF(_id, _index) \ 575
623static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ 576AUDIO_SYNC_2X_CLK(audio0, 0);
624 {.input = &tegra_pll_a_out0, .value = 0}, \ 577AUDIO_SYNC_2X_CLK(audio1, 1);
625 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ 578AUDIO_SYNC_2X_CLK(audio2, 2);
626 {.input = &tegra_pll_p, .value = 2}, \ 579AUDIO_SYNC_2X_CLK(audio3, 3);
627 {.input = &tegra_clk_m, .value = 3}, \ 580AUDIO_SYNC_2X_CLK(audio4, 4);
628 { 0, 0}, \ 581AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
629} 582
630MUX_I2S_SPDIF(audio0, 0); 583static struct clk *tegra_clk_audio_2x_list[] = {
631MUX_I2S_SPDIF(audio1, 1); 584 &tegra_audio0_2x,
632MUX_I2S_SPDIF(audio2, 2); 585 &tegra_audio1_2x,
633MUX_I2S_SPDIF(audio3, 3); 586 &tegra_audio2_2x,
634MUX_I2S_SPDIF(audio4, 4); 587 &tegra_audio3_2x,
635MUX_I2S_SPDIF(audio, 5); /* SPDIF */ 588 &tegra_audio4_2x,
589 &tegra_audio5_2x, /* SPDIF */
590};
591
592#define MUX_I2S_SPDIF(_id) \
593static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
594 "pll_a_out0", \
595 #_id "_2x", \
596 "pll_p", \
597 "clk_m", \
598}; \
599static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
600 &tegra_pll_a_out0, \
601 &tegra_##_id##_2x, \
602 &tegra_pll_p, \
603 &tegra_clk_m, \
604};
605
606MUX_I2S_SPDIF(audio0);
607MUX_I2S_SPDIF(audio1);
608MUX_I2S_SPDIF(audio2);
609MUX_I2S_SPDIF(audio3);
610MUX_I2S_SPDIF(audio4);
611MUX_I2S_SPDIF(audio5); /* SPDIF */
612
613static struct clk tegra_extern1;
614static struct clk tegra_extern2;
615static struct clk tegra_extern3;
636 616
637/* External clock outputs (through PMC) */ 617/* External clock outputs (through PMC) */
638#define MUX_EXTERN_OUT(_id) \ 618#define MUX_EXTERN_OUT(_id) \
639static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \ 619static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
640 {.input = &tegra_clk_m, .value = 0}, \ 620 "clk_m", \
641 {.input = &tegra_clk_m_div2, .value = 1}, \ 621 "clk_m_div2", \
642 {.input = &tegra_clk_m_div4, .value = 2}, \ 622 "clk_m_div4", \
643 {.input = NULL, .value = 3}, /* placeholder */ \ 623 "extern" #_id, \
644 { 0, 0}, \ 624}; \
645} 625static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
626 &tegra_clk_m, \
627 &tegra_clk_m_div2, \
628 &tegra_clk_m_div4, \
629 &tegra_extern##_id, \
630};
631
646MUX_EXTERN_OUT(1); 632MUX_EXTERN_OUT(1);
647MUX_EXTERN_OUT(2); 633MUX_EXTERN_OUT(2);
648MUX_EXTERN_OUT(3); 634MUX_EXTERN_OUT(3);
649 635
650static struct clk_mux_sel *mux_extern_out_list[] = { 636#define CLK_OUT_CLK(_name, _index) \
651 mux_clkm_clkm2_clkm4_extern1, 637 static struct clk tegra_##_name; \
652 mux_clkm_clkm2_clkm4_extern2, 638 static struct clk_tegra tegra_##_name##_hw = { \
653 mux_clkm_clkm2_clkm4_extern3, 639 .hw = { \
640 .clk = &tegra_##_name, \
641 }, \
642 .lookup = { \
643 .dev_id = #_name, \
644 .con_id = "extern" #_index, \
645 }, \
646 .flags = MUX_CLK_OUT, \
647 .fixed_rate = 216000000, \
648 .reg = 0x1a8, \
649 .u.periph = { \
650 .clk_num = (_index - 1) * 8 + 2, \
651 }, \
652 }; \
653 static struct clk tegra_##_name = { \
654 .name = #_name, \
655 .ops = &tegra_clk_out_ops, \
656 .hw = &tegra_##_name##_hw.hw, \
657 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
658 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
659 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
660 };
661
662CLK_OUT_CLK(clk_out_1, 1);
663CLK_OUT_CLK(clk_out_2, 2);
664CLK_OUT_CLK(clk_out_3, 3);
665
666static struct clk *tegra_clk_out_list[] = {
667 &tegra_clk_out_1,
668 &tegra_clk_out_2,
669 &tegra_clk_out_3,
670};
671
672static const char *mux_sclk[] = {
673 "clk_m",
674 "pll_c_out1",
675 "pll_p_out4",
676 "pll_p_out3",
677 "pll_p_out2",
678 "dummy",
679 "clk_32k",
680 "pll_m_out1",
681};
682
683static struct clk *mux_sclk_p[] = {
684 &tegra_clk_m,
685 &tegra_pll_c_out1,
686 &tegra_pll_p_out4,
687 &tegra_pll_p_out3,
688 &tegra_pll_p_out2,
689 NULL,
690 &tegra_clk_32k,
691 &tegra_pll_m_out1,
654}; 692};
655 693
656#define CLK_OUT_CLK(_id) \ 694static struct clk tegra_clk_sclk;
657 { \ 695static struct clk_tegra tegra_clk_sclk_hw = {
658 .name = "clk_out_" #_id, \ 696 .hw = {
659 .lookup = { \ 697 .clk = &tegra_clk_sclk,
660 .dev_id = "clk_out_" #_id, \ 698 },
661 .con_id = "extern" #_id, \ 699 .reg = 0x28,
662 }, \ 700 .max_rate = 334000000,
663 .ops = &tegra_clk_out_ops, \ 701 .min_rate = 40000000,
664 .reg = 0x1a8, \
665 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
666 .flags = MUX_CLK_OUT, \
667 .max_rate = 216000000, \
668 .u.periph = { \
669 .clk_num = (_id - 1) * 8 + 2, \
670 }, \
671 }
672static struct clk tegra_clk_out_list[] = {
673 CLK_OUT_CLK(1),
674 CLK_OUT_CLK(2),
675 CLK_OUT_CLK(3),
676}; 702};
677 703
678/* called after peripheral external clocks are initialized */ 704static struct clk tegra_clk_sclk = {
679static void init_clk_out_mux(void) 705 .name = "sclk",
680{ 706 .ops = &tegra30_super_ops,
681 int i; 707 .hw = &tegra_clk_sclk_hw.hw,
682 struct clk *c; 708 .parent_names = mux_sclk,
683 709 .parents = mux_sclk_p,
684 /* output clock con_id is the name of peripheral 710 .num_parents = ARRAY_SIZE(mux_sclk),
685 external clock connected to input 3 of the output mux */ 711};
686 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
687 c = tegra_get_clock_by_name(
688 tegra_clk_out_list[i].lookup.con_id);
689 if (!c)
690 pr_err("%s: could not find clk %s\n", __func__,
691 tegra_clk_out_list[i].lookup.con_id);
692 mux_extern_out_list[i][3].input = c;
693 }
694}
695 712
696/* Peripheral muxes */ 713static const char *mux_blink[] = {
697static struct clk_mux_sel mux_sclk[] = { 714 "clk_32k",
698 { .input = &tegra_clk_m, .value = 0},
699 { .input = &tegra_pll_c_out1, .value = 1},
700 { .input = &tegra_pll_p_out4, .value = 2},
701 { .input = &tegra_pll_p_out3, .value = 3},
702 { .input = &tegra_pll_p_out2, .value = 4},
703 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
704 { .input = &tegra_clk_32k, .value = 6},
705 { .input = &tegra_pll_m_out1, .value = 7},
706 { 0, 0},
707}; 715};
708 716
709static struct clk tegra_clk_sclk = { 717static struct clk *mux_blink_p[] = {
710 .name = "sclk", 718 &tegra_clk_32k,
711 .inputs = mux_sclk,
712 .reg = 0x28,
713 .ops = &tegra30_super_ops,
714 .max_rate = 334000000,
715 .min_rate = 40000000,
716}; 719};
717 720
721static struct clk tegra_clk_blink;
722static struct clk_tegra tegra_clk_blink_hw = {
723 .hw = {
724 .clk = &tegra_clk_blink,
725 },
726 .reg = 0x40,
727 .max_rate = 32768,
728};
718static struct clk tegra_clk_blink = { 729static struct clk tegra_clk_blink = {
719 .name = "blink", 730 .name = "blink",
720 .parent = &tegra_clk_32k, 731 .ops = &tegra30_blink_clk_ops,
721 .reg = 0x40, 732 .hw = &tegra_clk_blink_hw.hw,
722 .ops = &tegra30_blink_clk_ops, 733 .parent = &tegra_clk_32k,
723 .max_rate = 32768, 734 .parent_names = mux_blink,
735 .parents = mux_blink_p,
736 .num_parents = ARRAY_SIZE(mux_blink),
724}; 737};
725 738
726static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { 739static const char *mux_pllm_pllc_pllp_plla[] = {
727 { .input = &tegra_pll_m, .value = 0}, 740 "pll_m",
728 { .input = &tegra_pll_c, .value = 1}, 741 "pll_c",
729 { .input = &tegra_pll_p, .value = 2}, 742 "pll_p",
730 { .input = &tegra_pll_a_out0, .value = 3}, 743 "pll_a_out0",
731 { 0, 0},
732}; 744};
733 745
734static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { 746static const char *mux_pllp_pllc_pllm_clkm[] = {
735 { .input = &tegra_pll_p, .value = 0}, 747 "pll_p",
736 { .input = &tegra_pll_c, .value = 1}, 748 "pll_c",
737 { .input = &tegra_pll_m, .value = 2}, 749 "pll_m",
738 { .input = &tegra_clk_m, .value = 3}, 750 "clk_m",
739 { 0, 0},
740}; 751};
741 752
742static struct clk_mux_sel mux_pllp_clkm[] = { 753static const char *mux_pllp_clkm[] = {
743 { .input = &tegra_pll_p, .value = 0}, 754 "pll_p",
744 { .input = &tegra_clk_m, .value = 3}, 755 "dummy",
745 { 0, 0}, 756 "dummy",
757 "clk_m",
746}; 758};
747 759
748static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { 760static const char *mux_pllp_plld_pllc_clkm[] = {
749 {.input = &tegra_pll_p, .value = 0}, 761 "pll_p",
750 {.input = &tegra_pll_d_out0, .value = 1}, 762 "pll_d_out0",
751 {.input = &tegra_pll_c, .value = 2}, 763 "pll_c",
752 {.input = &tegra_clk_m, .value = 3}, 764 "clk_m",
753 { 0, 0},
754}; 765};
755 766
756static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 767static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
757 {.input = &tegra_pll_p, .value = 0}, 768 "pll_p",
758 {.input = &tegra_pll_m, .value = 1}, 769 "pll_m",
759 {.input = &tegra_pll_d_out0, .value = 2}, 770 "pll_d_out0",
760 {.input = &tegra_pll_a_out0, .value = 3}, 771 "pll_a_out0",
761 {.input = &tegra_pll_c, .value = 4}, 772 "pll_c",
762 {.input = &tegra_pll_d2_out0, .value = 5}, 773 "pll_d2_out0",
763 {.input = &tegra_clk_m, .value = 6}, 774 "clk_m",
764 { 0, 0},
765}; 775};
766 776
767static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = { 777static const char *mux_plla_pllc_pllp_clkm[] = {
768 { .input = &tegra_pll_a_out0, .value = 0}, 778 "pll_a_out0",
769 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */ 779 "dummy",
770 { .input = &tegra_pll_p, .value = 2}, 780 "pll_p",
771 { .input = &tegra_clk_m, .value = 3}, 781 "clk_m"
772 { 0, 0},
773}; 782};
774 783
775static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = { 784static const char *mux_pllp_pllc_clk32_clkm[] = {
776 {.input = &tegra_pll_p, .value = 0}, 785 "pll_p",
777 {.input = &tegra_pll_c, .value = 1}, 786 "pll_c",
778 {.input = &tegra_clk_32k, .value = 2}, 787 "clk_32k",
779 {.input = &tegra_clk_m, .value = 3}, 788 "clk_m",
780 { 0, 0},
781}; 789};
782 790
783static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = { 791static const char *mux_pllp_pllc_clkm_clk32[] = {
784 {.input = &tegra_pll_p, .value = 0}, 792 "pll_p",
785 {.input = &tegra_pll_c, .value = 1}, 793 "pll_c",
786 {.input = &tegra_clk_m, .value = 2}, 794 "clk_m",
787 {.input = &tegra_clk_32k, .value = 3}, 795 "clk_32k",
788 { 0, 0},
789}; 796};
790 797
791static struct clk_mux_sel mux_pllp_pllc_pllm[] = { 798static const char *mux_pllp_pllc_pllm[] = {
792 {.input = &tegra_pll_p, .value = 0}, 799 "pll_p",
793 {.input = &tegra_pll_c, .value = 1}, 800 "pll_c",
794 {.input = &tegra_pll_m, .value = 2}, 801 "pll_m",
795 { 0, 0},
796}; 802};
797 803
798static struct clk_mux_sel mux_clk_m[] = { 804static const char *mux_clk_m[] = {
799 { .input = &tegra_clk_m, .value = 0}, 805 "clk_m",
800 { 0, 0},
801}; 806};
802 807
803static struct clk_mux_sel mux_pllp_out3[] = { 808static const char *mux_pllp_out3[] = {
804 { .input = &tegra_pll_p_out3, .value = 0}, 809 "pll_p_out3",
805 { 0, 0},
806}; 810};
807 811
808static struct clk_mux_sel mux_plld_out0[] = { 812static const char *mux_plld_out0[] = {
809 { .input = &tegra_pll_d_out0, .value = 0}, 813 "pll_d_out0",
810 { 0, 0},
811}; 814};
812 815
813static struct clk_mux_sel mux_plld_out0_plld2_out0[] = { 816static const char *mux_plld_out0_plld2_out0[] = {
814 { .input = &tegra_pll_d_out0, .value = 0}, 817 "pll_d_out0",
815 { .input = &tegra_pll_d2_out0, .value = 1}, 818 "pll_d2_out0",
816 { 0, 0},
817}; 819};
818 820
819static struct clk_mux_sel mux_clk_32k[] = { 821static const char *mux_clk_32k[] = {
820 { .input = &tegra_clk_32k, .value = 0}, 822 "clk_32k",
821 { 0, 0},
822}; 823};
823 824
824static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = { 825static const char *mux_plla_clk32_pllp_clkm_plle[] = {
825 { .input = &tegra_pll_a_out0, .value = 0}, 826 "pll_a_out0",
826 { .input = &tegra_clk_32k, .value = 1}, 827 "clk_32k",
827 { .input = &tegra_pll_p, .value = 2}, 828 "pll_p",
828 { .input = &tegra_clk_m, .value = 3}, 829 "clk_m",
829 { .input = &tegra_pll_e, .value = 4}, 830 "pll_e",
830 { 0, 0},
831}; 831};
832 832
833static struct clk_mux_sel mux_cclk_g[] = { 833static const char *mux_cclk_g[] = {
834 { .input = &tegra_clk_m, .value = 0}, 834 "clk_m",
835 { .input = &tegra_pll_c, .value = 1}, 835 "pll_c",
836 { .input = &tegra_clk_32k, .value = 2}, 836 "clk_32k",
837 { .input = &tegra_pll_m, .value = 3}, 837 "pll_m",
838 { .input = &tegra_pll_p, .value = 4}, 838 "pll_p",
839 { .input = &tegra_pll_p_out4, .value = 5}, 839 "pll_p_out4",
840 { .input = &tegra_pll_p_out3, .value = 6}, 840 "pll_p_out3",
841 { .input = &tegra_pll_x, .value = 8}, 841 "dummy",
842 { 0, 0}, 842 "pll_x",
843}; 843};
844 844
845static struct clk tegra_clk_cclk_g = { 845static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
846 .name = "cclk_g", 846 &tegra_pll_m,
847 .flags = DIV_U71 | DIV_U71_INT, 847 &tegra_pll_c,
848 .inputs = mux_cclk_g, 848 &tegra_pll_p,
849 .reg = 0x368, 849 &tegra_pll_a_out0,
850 .ops = &tegra30_super_ops, 850};
851
852static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
853 &tegra_pll_p,
854 &tegra_pll_c,
855 &tegra_pll_m,
856 &tegra_clk_m,
857};
858
859static struct clk *mux_pllp_clkm_p[] = {
860 &tegra_pll_p,
861 NULL,
862 NULL,
863 &tegra_clk_m,
864};
865
866static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
867 &tegra_pll_p,
868 &tegra_pll_d_out0,
869 &tegra_pll_c,
870 &tegra_clk_m,
871};
872
873static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
874 &tegra_pll_p,
875 &tegra_pll_m,
876 &tegra_pll_d_out0,
877 &tegra_pll_a_out0,
878 &tegra_pll_c,
879 &tegra_pll_d2_out0,
880 &tegra_clk_m,
881};
882
883static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
884 &tegra_pll_a_out0,
885 NULL,
886 &tegra_pll_p,
887 &tegra_clk_m,
888};
889
890static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
891 &tegra_pll_p,
892 &tegra_pll_c,
893 &tegra_clk_32k,
894 &tegra_clk_m,
895};
896
897static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
898 &tegra_pll_p,
899 &tegra_pll_c,
900 &tegra_clk_m,
901 &tegra_clk_32k,
902};
903
904static struct clk *mux_pllp_pllc_pllm_p[] = {
905 &tegra_pll_p,
906 &tegra_pll_c,
907 &tegra_pll_m,
908};
909
910static struct clk *mux_clk_m_p[] = {
911 &tegra_clk_m,
912};
913
914static struct clk *mux_pllp_out3_p[] = {
915 &tegra_pll_p_out3,
916};
917
918static struct clk *mux_plld_out0_p[] = {
919 &tegra_pll_d_out0,
920};
921
922static struct clk *mux_plld_out0_plld2_out0_p[] = {
923 &tegra_pll_d_out0,
924 &tegra_pll_d2_out0,
925};
926
927static struct clk *mux_clk_32k_p[] = {
928 &tegra_clk_32k,
929};
930
931static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
932 &tegra_pll_a_out0,
933 &tegra_clk_32k,
934 &tegra_pll_p,
935 &tegra_clk_m,
936 &tegra_pll_e,
937};
938
939static struct clk *mux_cclk_g_p[] = {
940 &tegra_clk_m,
941 &tegra_pll_c,
942 &tegra_clk_32k,
943 &tegra_pll_m,
944 &tegra_pll_p,
945 &tegra_pll_p_out4,
946 &tegra_pll_p_out3,
947 NULL,
948 &tegra_pll_x,
949};
950
951static struct clk tegra_clk_cclk_g;
952static struct clk_tegra tegra_clk_cclk_g_hw = {
953 .hw = {
954 .clk = &tegra_clk_cclk_g,
955 },
956 .flags = DIV_U71 | DIV_U71_INT,
957 .reg = 0x368,
851 .max_rate = 1700000000, 958 .max_rate = 1700000000,
852}; 959};
960static struct clk tegra_clk_cclk_g = {
961 .name = "cclk_g",
962 .ops = &tegra30_super_ops,
963 .hw = &tegra_clk_cclk_g_hw.hw,
964 .parent_names = mux_cclk_g,
965 .parents = mux_cclk_g_p,
966 .num_parents = ARRAY_SIZE(mux_cclk_g),
967};
853 968
854static struct clk tegra30_clk_twd = { 969static const char *mux_twd[] = {
855 .parent = &tegra_clk_cclk_g, 970 "cclk_g",
856 .name = "twd", 971};
857 .ops = &tegra30_twd_ops,
858 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
859 .mul = 1,
860 .div = 2,
861};
862
863#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
864 { \
865 .name = _name, \
866 .lookup = { \
867 .dev_id = _dev, \
868 .con_id = _con, \
869 }, \
870 .ops = &tegra30_periph_clk_ops, \
871 .reg = _reg, \
872 .inputs = _inputs, \
873 .flags = _flags, \
874 .max_rate = _max, \
875 .u.periph = { \
876 .clk_num = _clk_num, \
877 }, \
878 }
879 972
880#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \ 973static struct clk *mux_twd_p[] = {
881 _flags, _ops) \ 974 &tegra_clk_cclk_g,
882 { \ 975};
883 .name = _name, \
884 .lookup = { \
885 .dev_id = _dev, \
886 .con_id = _con, \
887 }, \
888 .ops = _ops, \
889 .reg = _reg, \
890 .inputs = _inputs, \
891 .flags = _flags, \
892 .max_rate = _max, \
893 .u.periph = { \
894 .clk_num = _clk_num, \
895 }, \
896 }
897 976
898#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ 977static struct clk tegra30_clk_twd;
899 { \ 978static struct clk_tegra tegra30_clk_twd_hw = {
900 .name = _name, \ 979 .hw = {
901 .lookup = { \ 980 .clk = &tegra30_clk_twd,
902 .dev_id = _dev, \ 981 },
903 .con_id = _con, \ 982 .max_rate = 1400000000,
904 }, \ 983 .mul = 1,
905 .ops = &tegra_clk_shared_bus_ops, \ 984 .div = 2,
906 .parent = _parent, \ 985};
907 .u.shared_bus_user = { \ 986
908 .client_id = _id, \ 987static struct clk tegra30_clk_twd = {
909 .client_div = _div, \ 988 .name = "twd",
910 .mode = _mode, \ 989 .ops = &tegra30_twd_ops,
990 .hw = &tegra30_clk_twd_hw.hw,
991 .parent = &tegra_clk_cclk_g,
992 .parent_names = mux_twd,
993 .parents = mux_twd_p,
994 .num_parents = ARRAY_SIZE(mux_twd),
995};
996
997#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
998 _max, _inputs, _flags) \
999 static struct clk tegra_##_name; \
1000 static struct clk_tegra tegra_##_name##_hw = { \
1001 .hw = { \
1002 .clk = &tegra_##_name, \
911 }, \ 1003 }, \
912 } 1004 .lookup = { \
913struct clk tegra_list_clks[] = {
914 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
915 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
916 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
917 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
918 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
919 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
920 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
921 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
922 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
923 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
924 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
925 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
926 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
927 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
928 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
929 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
930 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
931 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
932 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
933 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
934 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
935 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
936 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
937 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
938 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
939 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
940 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
941 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
942 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
943 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
944 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
945 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
946 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
947 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
948 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
949 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
950 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
951 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
952 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
953 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
954 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
955 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
956 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
957 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
958 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
959 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
960 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
961 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
962 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
963 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
964 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
965 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
966 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
967 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
968 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
969 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
970 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
971 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
972 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
973 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
974 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
975 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
976 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
977 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
978 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
979 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
980 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
981 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
982 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
983 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
984 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
985 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
986 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
987 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
988 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
989 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
990 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
991 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
992 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
993 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
994 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
995
996 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
997 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
998 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
999 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
1000 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
1001 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
1002 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
1003 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
1004 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
1005};
1006
1007#define CLK_DUPLICATE(_name, _dev, _con) \
1008 { \
1009 .name = _name, \
1010 .lookup = { \
1011 .dev_id = _dev, \ 1005 .dev_id = _dev, \
1012 .con_id = _con, \ 1006 .con_id = _con, \
1013 }, \ 1007 }, \
1008 .reg = _reg, \
1009 .flags = _flags, \
1010 .max_rate = _max, \
1011 .u.periph = { \
1012 .clk_num = _clk_num, \
1013 }, \
1014 .reset = &tegra30_periph_clk_reset, \
1015 }; \
1016 static struct clk tegra_##_name = { \
1017 .name = #_name, \
1018 .ops = &tegra30_periph_clk_ops, \
1019 .hw = &tegra_##_name##_hw.hw, \
1020 .parent_names = _inputs, \
1021 .parents = _inputs##_p, \
1022 .num_parents = ARRAY_SIZE(_inputs), \
1023 };
1024
1025PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1026PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1027PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1028PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1029PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1030PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1031PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1032PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1033PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1034PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1035PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1036PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1037PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1038PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1039PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1040PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1041PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1042PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1043PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1044PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1045PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1046PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1047PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1048PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1049PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1050PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1051PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1052PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1053PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1054PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1055PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1056PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1057PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1058PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1059PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1060PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1061PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1062PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1063PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1064PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1065PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1066PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1067PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1068PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1069PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1070PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1071PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1072PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1073PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1074PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1075PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1076PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1077PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1078PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1079PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1080PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1081PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1082PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1083PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1084PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1085PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1086PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1087PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1088PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1089PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1090PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1091PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1092PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1093PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1094PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1095PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1096PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1097PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1098PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1099PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1100PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1101PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1102PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1103PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1104PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1105PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1106PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1107PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1108PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1109PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1110PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1111PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1112PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1113PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1114
1115static struct clk tegra_dsib;
1116static struct clk_tegra tegra_dsib_hw = {
1117 .hw = {
1118 .clk = &tegra_dsib,
1119 },
1120 .lookup = {
1121 .dev_id = "tegradc.1",
1122 .con_id = "dsib",
1123 },
1124 .reg = 0xd0,
1125 .flags = MUX | PLLD,
1126 .max_rate = 500000000,
1127 .u.periph = {
1128 .clk_num = 82,
1129 },
1130 .reset = &tegra30_periph_clk_reset,
1131};
1132static struct clk tegra_dsib = {
1133 .name = "dsib",
1134 .ops = &tegra30_dsib_clk_ops,
1135 .hw = &tegra_dsib_hw.hw,
1136 .parent_names = mux_plld_out0_plld2_out0,
1137 .parents = mux_plld_out0_plld2_out0_p,
1138 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1139};
1140
1141struct clk *tegra_list_clks[] = {
1142 &tegra_apbdma,
1143 &tegra_rtc,
1144 &tegra_kbc,
1145 &tegra_timer,
1146 &tegra_kfuse,
1147 &tegra_fuse,
1148 &tegra_fuse_burn,
1149 &tegra_apbif,
1150 &tegra_i2s0,
1151 &tegra_i2s1,
1152 &tegra_i2s2,
1153 &tegra_i2s3,
1154 &tegra_i2s4,
1155 &tegra_spdif_out,
1156 &tegra_spdif_in,
1157 &tegra_pwm,
1158 &tegra_d_audio,
1159 &tegra_dam0,
1160 &tegra_dam1,
1161 &tegra_dam2,
1162 &tegra_hda,
1163 &tegra_hda2codec_2x,
1164 &tegra_hda2hdmi,
1165 &tegra_sbc1,
1166 &tegra_sbc2,
1167 &tegra_sbc3,
1168 &tegra_sbc4,
1169 &tegra_sbc5,
1170 &tegra_sbc6,
1171 &tegra_sata_oob,
1172 &tegra_sata,
1173 &tegra_sata_cold,
1174 &tegra_ndflash,
1175 &tegra_ndspeed,
1176 &tegra_vfir,
1177 &tegra_sdmmc1,
1178 &tegra_sdmmc2,
1179 &tegra_sdmmc3,
1180 &tegra_sdmmc4,
1181 &tegra_vcp,
1182 &tegra_bsea,
1183 &tegra_bsev,
1184 &tegra_vde,
1185 &tegra_csite,
1186 &tegra_la,
1187 &tegra_owr,
1188 &tegra_nor,
1189 &tegra_mipi,
1190 &tegra_i2c1,
1191 &tegra_i2c2,
1192 &tegra_i2c3,
1193 &tegra_i2c4,
1194 &tegra_i2c5,
1195 &tegra_uarta,
1196 &tegra_uartb,
1197 &tegra_uartc,
1198 &tegra_uartd,
1199 &tegra_uarte,
1200 &tegra_vi,
1201 &tegra_3d,
1202 &tegra_3d2,
1203 &tegra_2d,
1204 &tegra_vi_sensor,
1205 &tegra_epp,
1206 &tegra_mpe,
1207 &tegra_host1x,
1208 &tegra_cve,
1209 &tegra_tvo,
1210 &tegra_dtv,
1211 &tegra_hdmi,
1212 &tegra_tvdac,
1213 &tegra_disp1,
1214 &tegra_disp2,
1215 &tegra_usbd,
1216 &tegra_usb2,
1217 &tegra_usb3,
1218 &tegra_dsia,
1219 &tegra_dsib,
1220 &tegra_csi,
1221 &tegra_isp,
1222 &tegra_csus,
1223 &tegra_tsensor,
1224 &tegra_actmon,
1225 &tegra_extern1,
1226 &tegra_extern2,
1227 &tegra_extern3,
1228 &tegra_i2cslow,
1229 &tegra_pcie,
1230 &tegra_afi,
1231 &tegra_se,
1232};
1233
1234#define CLK_DUPLICATE(_name, _dev, _con) \
1235 { \
1236 .name = _name, \
1237 .lookup = { \
1238 .dev_id = _dev, \
1239 .con_id = _con, \
1240 }, \
1014 } 1241 }
1015 1242
1016/* Some clocks may be used by different drivers depending on the board 1243/* Some clocks may be used by different drivers depending on the board
@@ -1088,23 +1315,24 @@ struct clk *tegra_ptr_clks[] = {
1088 &tegra_pll_x_out0, 1315 &tegra_pll_x_out0,
1089 &tegra_pll_e, 1316 &tegra_pll_e,
1090 &tegra_clk_cclk_g, 1317 &tegra_clk_cclk_g,
1091 &tegra_cml0_clk, 1318 &tegra_cml0,
1092 &tegra_cml1_clk, 1319 &tegra_cml1,
1093 &tegra_pciex_clk, 1320 &tegra_pciex,
1094 &tegra_clk_sclk, 1321 &tegra_clk_sclk,
1095 &tegra_clk_blink, 1322 &tegra_clk_blink,
1096 &tegra30_clk_twd, 1323 &tegra30_clk_twd,
1097}; 1324};
1098 1325
1099
1100static void tegra30_init_one_clock(struct clk *c) 1326static void tegra30_init_one_clock(struct clk *c)
1101{ 1327{
1102 clk_init(c); 1328 struct clk_tegra *clk = to_clk_tegra(c->hw);
1103 INIT_LIST_HEAD(&c->shared_bus_list); 1329 __clk_init(NULL, c);
1104 if (!c->lookup.dev_id && !c->lookup.con_id) 1330 INIT_LIST_HEAD(&clk->shared_bus_list);
1105 c->lookup.con_id = c->name; 1331 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1106 c->lookup.clk = c; 1332 clk->lookup.con_id = c->name;
1107 clkdev_add(&c->lookup); 1333 clk->lookup.clk = c;
1334 clkdev_add(&clk->lookup);
1335 tegra_clk_add(c);
1108} 1336}
1109 1337
1110void __init tegra30_init_clocks(void) 1338void __init tegra30_init_clocks(void)
@@ -1116,7 +1344,7 @@ void __init tegra30_init_clocks(void)
1116 tegra30_init_one_clock(tegra_ptr_clks[i]); 1344 tegra30_init_one_clock(tegra_ptr_clks[i]);
1117 1345
1118 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) 1346 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1119 tegra30_init_one_clock(&tegra_list_clks[i]); 1347 tegra30_init_one_clock(tegra_list_clks[i]);
1120 1348
1121 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { 1349 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1122 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); 1350 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
@@ -1131,14 +1359,12 @@ void __init tegra30_init_clocks(void)
1131 } 1359 }
1132 1360
1133 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) 1361 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1134 tegra30_init_one_clock(&tegra_sync_source_list[i]); 1362 tegra30_init_one_clock(tegra_sync_source_list[i]);
1135 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) 1363 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1136 tegra30_init_one_clock(&tegra_clk_audio_list[i]); 1364 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1137 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) 1365 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1138 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]); 1366 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1139 1367
1140 init_clk_out_mux();
1141 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) 1368 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1142 tegra30_init_one_clock(&tegra_clk_out_list[i]); 1369 tegra30_init_one_clock(tegra_clk_out_list[i]);
1143
1144} 1370}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 04:42:10 -0400