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authorPrashant Gaikwad <pgaikwad@nvidia.com>2012-08-06 02:27:39 -0400
committerStephen Warren <swarren@nvidia.com>2012-09-06 13:47:19 -0400
commit88e790a445b35cf137a62e590ced5315defad060 (patch)
treec24784a714c678794081c3785ad09616f1448b77 /arch/arm/mach-tegra
parenteb70e1bdd8a633e058cfb6186d45d4c8bdbdf534 (diff)
ARM: tegra30: Separate out clk ops and clk data
Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c1155
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h43
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1144
4 files changed, 1210 insertions, 1133 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303b9ac8..0b62a9b7297a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_SMP) += reset.o 20obj-$(CONFIG_SMP) += reset.o
20obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 21obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..645ef6900a0e 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c 2 * arch/arm/mach-tegra/tegra30_clocks.c
3 * 3 *
4 * Copyright (c) 2010-2011 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -533,13 +533,13 @@ static void tegra30_clk_m_disable(struct clk *c)
533 WARN(1, "Attempting to disable main SoC clock\n"); 533 WARN(1, "Attempting to disable main SoC clock\n");
534} 534}
535 535
536static struct clk_ops tegra_clk_m_ops = { 536struct clk_ops tegra30_clk_m_ops = {
537 .init = tegra30_clk_m_init, 537 .init = tegra30_clk_m_init,
538 .enable = tegra30_clk_m_enable, 538 .enable = tegra30_clk_m_enable,
539 .disable = tegra30_clk_m_disable, 539 .disable = tegra30_clk_m_disable,
540}; 540};
541 541
542static struct clk_ops tegra_clk_m_div_ops = { 542struct clk_ops tegra_clk_m_div_ops = {
543 .enable = tegra30_clk_m_enable, 543 .enable = tegra30_clk_m_enable,
544}; 544};
545 545
@@ -567,7 +567,7 @@ static void tegra30_pll_ref_init(struct clk *c)
567 c->state = ON; 567 c->state = ON;
568} 568}
569 569
570static struct clk_ops tegra_pll_ref_ops = { 570struct clk_ops tegra_pll_ref_ops = {
571 .init = tegra30_pll_ref_init, 571 .init = tegra30_pll_ref_init,
572 .enable = tegra30_clk_m_enable, 572 .enable = tegra30_clk_m_enable,
573 .disable = tegra30_clk_m_disable, 573 .disable = tegra30_clk_m_disable,
@@ -707,7 +707,7 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
707 return clk_set_rate(c->parent, rate); 707 return clk_set_rate(c->parent, rate);
708} 708}
709 709
710static struct clk_ops tegra_super_ops = { 710struct clk_ops tegra30_super_ops = {
711 .init = tegra30_super_clk_init, 711 .init = tegra30_super_clk_init,
712 .enable = tegra30_super_clk_enable, 712 .enable = tegra30_super_clk_enable,
713 .disable = tegra30_super_clk_disable, 713 .disable = tegra30_super_clk_disable,
@@ -722,7 +722,7 @@ static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
722 return 0; 722 return 0;
723} 723}
724 724
725static struct clk_ops tegra30_twd_ops = { 725struct clk_ops tegra30_twd_ops = {
726 .set_rate = tegra30_twd_clk_set_rate, 726 .set_rate = tegra30_twd_clk_set_rate,
727}; 727};
728 728
@@ -801,7 +801,7 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
801 return 0; 801 return 0;
802} 802}
803 803
804static struct clk_ops tegra_blink_clk_ops = { 804struct clk_ops tegra30_blink_clk_ops = {
805 .init = &tegra30_blink_clk_init, 805 .init = &tegra30_blink_clk_init,
806 .enable = &tegra30_blink_clk_enable, 806 .enable = &tegra30_blink_clk_enable,
807 .disable = &tegra30_blink_clk_disable, 807 .disable = &tegra30_blink_clk_disable,
@@ -829,7 +829,6 @@ static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
829 return 0; 829 return 0;
830} 830}
831 831
832
833static void tegra30_utmi_param_configure(struct clk *c) 832static void tegra30_utmi_param_configure(struct clk *c)
834{ 833{
835 u32 reg; 834 u32 reg;
@@ -1100,7 +1099,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1100 return 0; 1099 return 0;
1101} 1100}
1102 1101
1103static struct clk_ops tegra_pll_ops = { 1102struct clk_ops tegra30_pll_ops = {
1104 .init = tegra30_pll_clk_init, 1103 .init = tegra30_pll_clk_init,
1105 .enable = tegra30_pll_clk_enable, 1104 .enable = tegra30_pll_clk_enable,
1106 .disable = tegra30_pll_clk_disable, 1105 .disable = tegra30_pll_clk_disable,
@@ -1141,7 +1140,7 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1141 return 0; 1140 return 0;
1142} 1141}
1143 1142
1144static struct clk_ops tegra_plld_ops = { 1143struct clk_ops tegra_plld_ops = {
1145 .init = tegra30_pll_clk_init, 1144 .init = tegra30_pll_clk_init,
1146 .enable = tegra30_pll_clk_enable, 1145 .enable = tegra30_pll_clk_enable,
1147 .disable = tegra30_pll_clk_disable, 1146 .disable = tegra30_pll_clk_disable,
@@ -1258,7 +1257,7 @@ static int tegra30_plle_clk_enable(struct clk *c)
1258 return tegra30_plle_configure(c, !c->set); 1257 return tegra30_plle_configure(c, !c->set);
1259} 1258}
1260 1259
1261static struct clk_ops tegra_plle_ops = { 1260struct clk_ops tegra30_plle_ops = {
1262 .init = tegra30_plle_clk_init, 1261 .init = tegra30_plle_clk_init,
1263 .enable = tegra30_plle_clk_enable, 1262 .enable = tegra30_plle_clk_enable,
1264 .disable = tegra30_plle_clk_disable, 1263 .disable = tegra30_plle_clk_disable,
@@ -1386,7 +1385,7 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1386 return -EINVAL; 1385 return -EINVAL;
1387} 1386}
1388 1387
1389static struct clk_ops tegra_pll_div_ops = { 1388struct clk_ops tegra30_pll_div_ops = {
1390 .init = tegra30_pll_div_clk_init, 1389 .init = tegra30_pll_div_clk_init,
1391 .enable = tegra30_pll_div_clk_enable, 1390 .enable = tegra30_pll_div_clk_enable,
1392 .disable = tegra30_pll_div_clk_disable, 1391 .disable = tegra30_pll_div_clk_disable,
@@ -1634,7 +1633,7 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
1634 return -EINVAL; 1633 return -EINVAL;
1635} 1634}
1636 1635
1637static struct clk_ops tegra_periph_clk_ops = { 1636struct clk_ops tegra30_periph_clk_ops = {
1638 .init = &tegra30_periph_clk_init, 1637 .init = &tegra30_periph_clk_init,
1639 .enable = &tegra30_periph_clk_enable, 1638 .enable = &tegra30_periph_clk_enable,
1640 .disable = &tegra30_periph_clk_disable, 1639 .disable = &tegra30_periph_clk_disable,
@@ -1644,7 +1643,6 @@ static struct clk_ops tegra_periph_clk_ops = {
1644 .reset = &tegra30_periph_clk_reset, 1643 .reset = &tegra30_periph_clk_reset,
1645}; 1644};
1646 1645
1647
1648/* Periph extended clock configuration ops */ 1646/* Periph extended clock configuration ops */
1649static int 1647static int
1650tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1648tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
@@ -1660,7 +1658,7 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1660 return -EINVAL; 1658 return -EINVAL;
1661} 1659}
1662 1660
1663static struct clk_ops tegra_vi_clk_ops = { 1661struct clk_ops tegra_vi_clk_ops = {
1664 .init = &tegra30_periph_clk_init, 1662 .init = &tegra30_periph_clk_init,
1665 .enable = &tegra30_periph_clk_enable, 1663 .enable = &tegra30_periph_clk_enable,
1666 .disable = &tegra30_periph_clk_disable, 1664 .disable = &tegra30_periph_clk_disable,
@@ -1686,7 +1684,7 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1686 return -EINVAL; 1684 return -EINVAL;
1687} 1685}
1688 1686
1689static struct clk_ops tegra_nand_clk_ops = { 1687struct clk_ops tegra_nand_clk_ops = {
1690 .init = &tegra30_periph_clk_init, 1688 .init = &tegra30_periph_clk_init,
1691 .enable = &tegra30_periph_clk_enable, 1689 .enable = &tegra30_periph_clk_enable,
1692 .disable = &tegra30_periph_clk_disable, 1690 .disable = &tegra30_periph_clk_disable,
@@ -1697,7 +1695,6 @@ static struct clk_ops tegra_nand_clk_ops = {
1697 .reset = &tegra30_periph_clk_reset, 1695 .reset = &tegra30_periph_clk_reset,
1698}; 1696};
1699 1697
1700
1701static int 1698static int
1702tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1699tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1703{ 1700{
@@ -1713,7 +1710,7 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1713 return -EINVAL; 1710 return -EINVAL;
1714} 1711}
1715 1712
1716static struct clk_ops tegra_dtv_clk_ops = { 1713struct clk_ops tegra_dtv_clk_ops = {
1717 .init = &tegra30_periph_clk_init, 1714 .init = &tegra30_periph_clk_init,
1718 .enable = &tegra30_periph_clk_enable, 1715 .enable = &tegra30_periph_clk_enable,
1719 .disable = &tegra30_periph_clk_disable, 1716 .disable = &tegra30_periph_clk_disable,
@@ -1753,7 +1750,7 @@ static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
1753 return -EINVAL; 1750 return -EINVAL;
1754} 1751}
1755 1752
1756static struct clk_ops tegra_dsib_clk_ops = { 1753struct clk_ops tegra_dsib_clk_ops = {
1757 .init = &tegra30_periph_clk_init, 1754 .init = &tegra30_periph_clk_init,
1758 .enable = &tegra30_periph_clk_enable, 1755 .enable = &tegra30_periph_clk_enable,
1759 .disable = &tegra30_periph_clk_disable, 1756 .disable = &tegra30_periph_clk_disable,
@@ -1764,7 +1761,7 @@ static struct clk_ops tegra_dsib_clk_ops = {
1764}; 1761};
1765 1762
1766/* pciex clock support only reset function */ 1763/* pciex clock support only reset function */
1767static struct clk_ops tegra_pciex_clk_ops = { 1764struct clk_ops tegra_pciex_clk_ops = {
1768 .reset = tegra30_periph_clk_reset, 1765 .reset = tegra30_periph_clk_reset,
1769}; 1766};
1770 1767
@@ -1851,14 +1848,13 @@ static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
1851 return -EINVAL; 1848 return -EINVAL;
1852} 1849}
1853 1850
1854static struct clk_ops tegra_clk_out_ops = { 1851struct clk_ops tegra_clk_out_ops = {
1855 .init = &tegra30_clk_out_init, 1852 .init = &tegra30_clk_out_init,
1856 .enable = &tegra30_clk_out_enable, 1853 .enable = &tegra30_clk_out_enable,
1857 .disable = &tegra30_clk_out_disable, 1854 .disable = &tegra30_clk_out_disable,
1858 .set_parent = &tegra30_clk_out_set_parent, 1855 .set_parent = &tegra30_clk_out_set_parent,
1859}; 1856};
1860 1857
1861
1862/* Clock doubler ops */ 1858/* Clock doubler ops */
1863static void tegra30_clk_double_init(struct clk *c) 1859static void tegra30_clk_double_init(struct clk *c)
1864{ 1860{
@@ -1890,7 +1886,7 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
1890 return -EINVAL; 1886 return -EINVAL;
1891} 1887}
1892 1888
1893static struct clk_ops tegra_clk_double_ops = { 1889struct clk_ops tegra30_clk_double_ops = {
1894 .init = &tegra30_clk_double_init, 1890 .init = &tegra30_clk_double_init,
1895 .enable = &tegra30_periph_clk_enable, 1891 .enable = &tegra30_periph_clk_enable,
1896 .disable = &tegra30_periph_clk_disable, 1892 .disable = &tegra30_periph_clk_disable,
@@ -1904,7 +1900,7 @@ static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
1904 return 0; 1900 return 0;
1905} 1901}
1906 1902
1907static struct clk_ops tegra_sync_source_ops = { 1903struct clk_ops tegra_sync_source_ops = {
1908 .set_rate = &tegra30_sync_source_set_rate, 1904 .set_rate = &tegra30_sync_source_set_rate,
1909}; 1905};
1910 1906
@@ -1961,7 +1957,7 @@ static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1961 return -EINVAL; 1957 return -EINVAL;
1962} 1958}
1963 1959
1964static struct clk_ops tegra_audio_sync_clk_ops = { 1960struct clk_ops tegra30_audio_sync_clk_ops = {
1965 .init = tegra30_audio_sync_clk_init, 1961 .init = tegra30_audio_sync_clk_init,
1966 .enable = tegra30_audio_sync_clk_enable, 1962 .enable = tegra30_audio_sync_clk_enable,
1967 .disable = tegra30_audio_sync_clk_disable, 1963 .disable = tegra30_audio_sync_clk_disable,
@@ -1990,1115 +1986,8 @@ static void tegra30_cml_clk_disable(struct clk *c)
1990 clk_writel(val, c->reg); 1986 clk_writel(val, c->reg);
1991} 1987}
1992 1988
1993static struct clk_ops tegra_cml_clk_ops = { 1989struct clk_ops tegra_cml_clk_ops = {
1994 .init = &tegra30_cml_clk_init, 1990 .init = &tegra30_cml_clk_init,
1995 .enable = &tegra30_cml_clk_enable, 1991 .enable = &tegra30_cml_clk_enable,
1996 .disable = &tegra30_cml_clk_disable, 1992 .disable = &tegra30_cml_clk_disable,
1997}; 1993};
1998
1999/* Clock definitions */
2000static struct clk tegra_clk_32k = {
2001 .name = "clk_32k",
2002 .rate = 32768,
2003 .ops = NULL,
2004 .max_rate = 32768,
2005};
2006
2007static struct clk tegra_clk_m = {
2008 .name = "clk_m",
2009 .flags = ENABLE_ON_INIT,
2010 .ops = &tegra_clk_m_ops,
2011 .reg = 0x1fc,
2012 .reg_shift = 28,
2013 .max_rate = 48000000,
2014};
2015
2016static struct clk tegra_clk_m_div2 = {
2017 .name = "clk_m_div2",
2018 .ops = &tegra_clk_m_div_ops,
2019 .parent = &tegra_clk_m,
2020 .mul = 1,
2021 .div = 2,
2022 .state = ON,
2023 .max_rate = 24000000,
2024};
2025
2026static struct clk tegra_clk_m_div4 = {
2027 .name = "clk_m_div4",
2028 .ops = &tegra_clk_m_div_ops,
2029 .parent = &tegra_clk_m,
2030 .mul = 1,
2031 .div = 4,
2032 .state = ON,
2033 .max_rate = 12000000,
2034};
2035
2036static struct clk tegra_pll_ref = {
2037 .name = "pll_ref",
2038 .flags = ENABLE_ON_INIT,
2039 .ops = &tegra_pll_ref_ops,
2040 .parent = &tegra_clk_m,
2041 .max_rate = 26000000,
2042};
2043
2044static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
2045 { 12000000, 1040000000, 520, 6, 1, 8},
2046 { 13000000, 1040000000, 480, 6, 1, 8},
2047 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
2048 { 19200000, 1040000000, 325, 6, 1, 6},
2049 { 26000000, 1040000000, 520, 13, 1, 8},
2050
2051 { 12000000, 832000000, 416, 6, 1, 8},
2052 { 13000000, 832000000, 832, 13, 1, 8},
2053 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
2054 { 19200000, 832000000, 260, 6, 1, 8},
2055 { 26000000, 832000000, 416, 13, 1, 8},
2056
2057 { 12000000, 624000000, 624, 12, 1, 8},
2058 { 13000000, 624000000, 624, 13, 1, 8},
2059 { 16800000, 600000000, 520, 14, 1, 8},
2060 { 19200000, 624000000, 520, 16, 1, 8},
2061 { 26000000, 624000000, 624, 26, 1, 8},
2062
2063 { 12000000, 600000000, 600, 12, 1, 8},
2064 { 13000000, 600000000, 600, 13, 1, 8},
2065 { 16800000, 600000000, 500, 14, 1, 8},
2066 { 19200000, 600000000, 375, 12, 1, 6},
2067 { 26000000, 600000000, 600, 26, 1, 8},
2068
2069 { 12000000, 520000000, 520, 12, 1, 8},
2070 { 13000000, 520000000, 520, 13, 1, 8},
2071 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
2072 { 19200000, 520000000, 325, 12, 1, 6},
2073 { 26000000, 520000000, 520, 26, 1, 8},
2074
2075 { 12000000, 416000000, 416, 12, 1, 8},
2076 { 13000000, 416000000, 416, 13, 1, 8},
2077 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
2078 { 19200000, 416000000, 260, 12, 1, 6},
2079 { 26000000, 416000000, 416, 26, 1, 8},
2080 { 0, 0, 0, 0, 0, 0 },
2081};
2082
2083static struct clk tegra_pll_c = {
2084 .name = "pll_c",
2085 .flags = PLL_HAS_CPCON,
2086 .ops = &tegra_pll_ops,
2087 .reg = 0x80,
2088 .parent = &tegra_pll_ref,
2089 .max_rate = 1400000000,
2090 .u.pll = {
2091 .input_min = 2000000,
2092 .input_max = 31000000,
2093 .cf_min = 1000000,
2094 .cf_max = 6000000,
2095 .vco_min = 20000000,
2096 .vco_max = 1400000000,
2097 .freq_table = tegra_pll_c_freq_table,
2098 .lock_delay = 300,
2099 },
2100};
2101
2102static struct clk tegra_pll_c_out1 = {
2103 .name = "pll_c_out1",
2104 .ops = &tegra_pll_div_ops,
2105 .flags = DIV_U71,
2106 .parent = &tegra_pll_c,
2107 .reg = 0x84,
2108 .reg_shift = 0,
2109 .max_rate = 700000000,
2110};
2111
2112static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
2113 { 12000000, 666000000, 666, 12, 1, 8},
2114 { 13000000, 666000000, 666, 13, 1, 8},
2115 { 16800000, 666000000, 555, 14, 1, 8},
2116 { 19200000, 666000000, 555, 16, 1, 8},
2117 { 26000000, 666000000, 666, 26, 1, 8},
2118 { 12000000, 600000000, 600, 12, 1, 8},
2119 { 13000000, 600000000, 600, 13, 1, 8},
2120 { 16800000, 600000000, 500, 14, 1, 8},
2121 { 19200000, 600000000, 375, 12, 1, 6},
2122 { 26000000, 600000000, 600, 26, 1, 8},
2123 { 0, 0, 0, 0, 0, 0 },
2124};
2125
2126static struct clk tegra_pll_m = {
2127 .name = "pll_m",
2128 .flags = PLL_HAS_CPCON | PLLM,
2129 .ops = &tegra_pll_ops,
2130 .reg = 0x90,
2131 .parent = &tegra_pll_ref,
2132 .max_rate = 800000000,
2133 .u.pll = {
2134 .input_min = 2000000,
2135 .input_max = 31000000,
2136 .cf_min = 1000000,
2137 .cf_max = 6000000,
2138 .vco_min = 20000000,
2139 .vco_max = 1200000000,
2140 .freq_table = tegra_pll_m_freq_table,
2141 .lock_delay = 300,
2142 },
2143};
2144
2145static struct clk tegra_pll_m_out1 = {
2146 .name = "pll_m_out1",
2147 .ops = &tegra_pll_div_ops,
2148 .flags = DIV_U71,
2149 .parent = &tegra_pll_m,
2150 .reg = 0x94,
2151 .reg_shift = 0,
2152 .max_rate = 600000000,
2153};
2154
2155static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
2156 { 12000000, 216000000, 432, 12, 2, 8},
2157 { 13000000, 216000000, 432, 13, 2, 8},
2158 { 16800000, 216000000, 360, 14, 2, 8},
2159 { 19200000, 216000000, 360, 16, 2, 8},
2160 { 26000000, 216000000, 432, 26, 2, 8},
2161 { 0, 0, 0, 0, 0, 0 },
2162};
2163
2164static struct clk tegra_pll_p = {
2165 .name = "pll_p",
2166 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
2167 .ops = &tegra_pll_ops,
2168 .reg = 0xa0,
2169 .parent = &tegra_pll_ref,
2170 .max_rate = 432000000,
2171 .u.pll = {
2172 .input_min = 2000000,
2173 .input_max = 31000000,
2174 .cf_min = 1000000,
2175 .cf_max = 6000000,
2176 .vco_min = 20000000,
2177 .vco_max = 1400000000,
2178 .freq_table = tegra_pll_p_freq_table,
2179 .lock_delay = 300,
2180 .fixed_rate = 408000000,
2181 },
2182};
2183
2184static struct clk tegra_pll_p_out1 = {
2185 .name = "pll_p_out1",
2186 .ops = &tegra_pll_div_ops,
2187 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2188 .parent = &tegra_pll_p,
2189 .reg = 0xa4,
2190 .reg_shift = 0,
2191 .max_rate = 432000000,
2192};
2193
2194static struct clk tegra_pll_p_out2 = {
2195 .name = "pll_p_out2",
2196 .ops = &tegra_pll_div_ops,
2197 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2198 .parent = &tegra_pll_p,
2199 .reg = 0xa4,
2200 .reg_shift = 16,
2201 .max_rate = 432000000,
2202};
2203
2204static struct clk tegra_pll_p_out3 = {
2205 .name = "pll_p_out3",
2206 .ops = &tegra_pll_div_ops,
2207 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2208 .parent = &tegra_pll_p,
2209 .reg = 0xa8,
2210 .reg_shift = 0,
2211 .max_rate = 432000000,
2212};
2213
2214static struct clk tegra_pll_p_out4 = {
2215 .name = "pll_p_out4",
2216 .ops = &tegra_pll_div_ops,
2217 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2218 .parent = &tegra_pll_p,
2219 .reg = 0xa8,
2220 .reg_shift = 16,
2221 .max_rate = 432000000,
2222};
2223
2224static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
2225 { 9600000, 564480000, 294, 5, 1, 4},
2226 { 9600000, 552960000, 288, 5, 1, 4},
2227 { 9600000, 24000000, 5, 2, 1, 1},
2228
2229 { 28800000, 56448000, 49, 25, 1, 1},
2230 { 28800000, 73728000, 64, 25, 1, 1},
2231 { 28800000, 24000000, 5, 6, 1, 1},
2232 { 0, 0, 0, 0, 0, 0 },
2233};
2234
2235static struct clk tegra_pll_a = {
2236 .name = "pll_a",
2237 .flags = PLL_HAS_CPCON,
2238 .ops = &tegra_pll_ops,
2239 .reg = 0xb0,
2240 .parent = &tegra_pll_p_out1,
2241 .max_rate = 700000000,
2242 .u.pll = {
2243 .input_min = 2000000,
2244 .input_max = 31000000,
2245 .cf_min = 1000000,
2246 .cf_max = 6000000,
2247 .vco_min = 20000000,
2248 .vco_max = 1400000000,
2249 .freq_table = tegra_pll_a_freq_table,
2250 .lock_delay = 300,
2251 },
2252};
2253
2254static struct clk tegra_pll_a_out0 = {
2255 .name = "pll_a_out0",
2256 .ops = &tegra_pll_div_ops,
2257 .flags = DIV_U71,
2258 .parent = &tegra_pll_a,
2259 .reg = 0xb4,
2260 .reg_shift = 0,
2261 .max_rate = 100000000,
2262};
2263
2264static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
2265 { 12000000, 216000000, 216, 12, 1, 4},
2266 { 13000000, 216000000, 216, 13, 1, 4},
2267 { 16800000, 216000000, 180, 14, 1, 4},
2268 { 19200000, 216000000, 180, 16, 1, 4},
2269 { 26000000, 216000000, 216, 26, 1, 4},
2270
2271 { 12000000, 594000000, 594, 12, 1, 8},
2272 { 13000000, 594000000, 594, 13, 1, 8},
2273 { 16800000, 594000000, 495, 14, 1, 8},
2274 { 19200000, 594000000, 495, 16, 1, 8},
2275 { 26000000, 594000000, 594, 26, 1, 8},
2276
2277 { 12000000, 1000000000, 1000, 12, 1, 12},
2278 { 13000000, 1000000000, 1000, 13, 1, 12},
2279 { 19200000, 1000000000, 625, 12, 1, 8},
2280 { 26000000, 1000000000, 1000, 26, 1, 12},
2281
2282 { 0, 0, 0, 0, 0, 0 },
2283};
2284
2285static struct clk tegra_pll_d = {
2286 .name = "pll_d",
2287 .flags = PLL_HAS_CPCON | PLLD,
2288 .ops = &tegra_plld_ops,
2289 .reg = 0xd0,
2290 .parent = &tegra_pll_ref,
2291 .max_rate = 1000000000,
2292 .u.pll = {
2293 .input_min = 2000000,
2294 .input_max = 40000000,
2295 .cf_min = 1000000,
2296 .cf_max = 6000000,
2297 .vco_min = 40000000,
2298 .vco_max = 1000000000,
2299 .freq_table = tegra_pll_d_freq_table,
2300 .lock_delay = 1000,
2301 },
2302};
2303
2304static struct clk tegra_pll_d_out0 = {
2305 .name = "pll_d_out0",
2306 .ops = &tegra_pll_div_ops,
2307 .flags = DIV_2 | PLLD,
2308 .parent = &tegra_pll_d,
2309 .max_rate = 500000000,
2310};
2311
2312static struct clk tegra_pll_d2 = {
2313 .name = "pll_d2",
2314 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
2315 .ops = &tegra_plld_ops,
2316 .reg = 0x4b8,
2317 .parent = &tegra_pll_ref,
2318 .max_rate = 1000000000,
2319 .u.pll = {
2320 .input_min = 2000000,
2321 .input_max = 40000000,
2322 .cf_min = 1000000,
2323 .cf_max = 6000000,
2324 .vco_min = 40000000,
2325 .vco_max = 1000000000,
2326 .freq_table = tegra_pll_d_freq_table,
2327 .lock_delay = 1000,
2328 },
2329};
2330
2331static struct clk tegra_pll_d2_out0 = {
2332 .name = "pll_d2_out0",
2333 .ops = &tegra_pll_div_ops,
2334 .flags = DIV_2 | PLLD,
2335 .parent = &tegra_pll_d2,
2336 .max_rate = 500000000,
2337};
2338
2339static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
2340 { 12000000, 480000000, 960, 12, 2, 12},
2341 { 13000000, 480000000, 960, 13, 2, 12},
2342 { 16800000, 480000000, 400, 7, 2, 5},
2343 { 19200000, 480000000, 200, 4, 2, 3},
2344 { 26000000, 480000000, 960, 26, 2, 12},
2345 { 0, 0, 0, 0, 0, 0 },
2346};
2347
2348static struct clk tegra_pll_u = {
2349 .name = "pll_u",
2350 .flags = PLL_HAS_CPCON | PLLU,
2351 .ops = &tegra_pll_ops,
2352 .reg = 0xc0,
2353 .parent = &tegra_pll_ref,
2354 .max_rate = 480000000,
2355 .u.pll = {
2356 .input_min = 2000000,
2357 .input_max = 40000000,
2358 .cf_min = 1000000,
2359 .cf_max = 6000000,
2360 .vco_min = 480000000,
2361 .vco_max = 960000000,
2362 .freq_table = tegra_pll_u_freq_table,
2363 .lock_delay = 1000,
2364 },
2365};
2366
2367static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
2368 /* 1.7 GHz */
2369 { 12000000, 1700000000, 850, 6, 1, 8},
2370 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
2371 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
2372 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
2373 { 26000000, 1700000000, 850, 13, 1, 8},
2374
2375 /* 1.6 GHz */
2376 { 12000000, 1600000000, 800, 6, 1, 8},
2377 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
2378 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
2379 { 19200000, 1600000000, 500, 6, 1, 8},
2380 { 26000000, 1600000000, 800, 13, 1, 8},
2381
2382 /* 1.5 GHz */
2383 { 12000000, 1500000000, 750, 6, 1, 8},
2384 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
2385 { 16800000, 1500000000, 625, 7, 1, 8},
2386 { 19200000, 1500000000, 625, 8, 1, 8},
2387 { 26000000, 1500000000, 750, 13, 1, 8},
2388
2389 /* 1.4 GHz */
2390 { 12000000, 1400000000, 700, 6, 1, 8},
2391 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
2392 { 16800000, 1400000000, 1000, 12, 1, 8},
2393 { 19200000, 1400000000, 875, 12, 1, 8},
2394 { 26000000, 1400000000, 700, 13, 1, 8},
2395
2396 /* 1.3 GHz */
2397 { 12000000, 1300000000, 975, 9, 1, 8},
2398 { 13000000, 1300000000, 1000, 10, 1, 8},
2399 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
2400 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
2401 { 26000000, 1300000000, 650, 13, 1, 8},
2402
2403 /* 1.2 GHz */
2404 { 12000000, 1200000000, 1000, 10, 1, 8},
2405 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
2406 { 16800000, 1200000000, 1000, 14, 1, 8},
2407 { 19200000, 1200000000, 1000, 16, 1, 8},
2408 { 26000000, 1200000000, 600, 13, 1, 8},
2409
2410 /* 1.1 GHz */
2411 { 12000000, 1100000000, 825, 9, 1, 8},
2412 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
2413 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
2414 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
2415 { 26000000, 1100000000, 550, 13, 1, 8},
2416
2417 /* 1 GHz */
2418 { 12000000, 1000000000, 1000, 12, 1, 8},
2419 { 13000000, 1000000000, 1000, 13, 1, 8},
2420 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
2421 { 19200000, 1000000000, 625, 12, 1, 8},
2422 { 26000000, 1000000000, 1000, 26, 1, 8},
2423
2424 { 0, 0, 0, 0, 0, 0 },
2425};
2426
2427static struct clk tegra_pll_x = {
2428 .name = "pll_x",
2429 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
2430 .ops = &tegra_pll_ops,
2431 .reg = 0xe0,
2432 .parent = &tegra_pll_ref,
2433 .max_rate = 1700000000,
2434 .u.pll = {
2435 .input_min = 2000000,
2436 .input_max = 31000000,
2437 .cf_min = 1000000,
2438 .cf_max = 6000000,
2439 .vco_min = 20000000,
2440 .vco_max = 1700000000,
2441 .freq_table = tegra_pll_x_freq_table,
2442 .lock_delay = 300,
2443 },
2444};
2445
2446static struct clk tegra_pll_x_out0 = {
2447 .name = "pll_x_out0",
2448 .ops = &tegra_pll_div_ops,
2449 .flags = DIV_2 | PLLX,
2450 .parent = &tegra_pll_x,
2451 .max_rate = 850000000,
2452};
2453
2454
2455static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
2456 /* PLLE special case: use cpcon field to store cml divider value */
2457 { 12000000, 100000000, 150, 1, 18, 11},
2458 { 216000000, 100000000, 200, 18, 24, 13},
2459 { 0, 0, 0, 0, 0, 0 },
2460};
2461
2462static struct clk tegra_pll_e = {
2463 .name = "pll_e",
2464 .flags = PLL_ALT_MISC_REG,
2465 .ops = &tegra_plle_ops,
2466 .reg = 0xe8,
2467 .max_rate = 100000000,
2468 .u.pll = {
2469 .input_min = 12000000,
2470 .input_max = 216000000,
2471 .cf_min = 12000000,
2472 .cf_max = 12000000,
2473 .vco_min = 1200000000,
2474 .vco_max = 2400000000U,
2475 .freq_table = tegra_pll_e_freq_table,
2476 .lock_delay = 300,
2477 .fixed_rate = 100000000,
2478 },
2479};
2480
2481static struct clk tegra_cml0_clk = {
2482 .name = "cml0",
2483 .parent = &tegra_pll_e,
2484 .ops = &tegra_cml_clk_ops,
2485 .reg = PLLE_AUX,
2486 .max_rate = 100000000,
2487 .u.periph = {
2488 .clk_num = 0,
2489 },
2490};
2491
2492static struct clk tegra_cml1_clk = {
2493 .name = "cml1",
2494 .parent = &tegra_pll_e,
2495 .ops = &tegra_cml_clk_ops,
2496 .reg = PLLE_AUX,
2497 .max_rate = 100000000,
2498 .u.periph = {
2499 .clk_num = 1,
2500 },
2501};
2502
2503static struct clk tegra_pciex_clk = {
2504 .name = "pciex",
2505 .parent = &tegra_pll_e,
2506 .ops = &tegra_pciex_clk_ops,
2507 .max_rate = 100000000,
2508 .u.periph = {
2509 .clk_num = 74,
2510 },
2511};
2512
2513/* Audio sync clocks */
2514#define SYNC_SOURCE(_id) \
2515 { \
2516 .name = #_id "_sync", \
2517 .rate = 24000000, \
2518 .max_rate = 24000000, \
2519 .ops = &tegra_sync_source_ops \
2520 }
2521static struct clk tegra_sync_source_list[] = {
2522 SYNC_SOURCE(spdif_in),
2523 SYNC_SOURCE(i2s0),
2524 SYNC_SOURCE(i2s1),
2525 SYNC_SOURCE(i2s2),
2526 SYNC_SOURCE(i2s3),
2527 SYNC_SOURCE(i2s4),
2528 SYNC_SOURCE(vimclk),
2529};
2530
2531static struct clk_mux_sel mux_audio_sync_clk[] = {
2532 { .input = &tegra_sync_source_list[0], .value = 0},
2533 { .input = &tegra_sync_source_list[1], .value = 1},
2534 { .input = &tegra_sync_source_list[2], .value = 2},
2535 { .input = &tegra_sync_source_list[3], .value = 3},
2536 { .input = &tegra_sync_source_list[4], .value = 4},
2537 { .input = &tegra_sync_source_list[5], .value = 5},
2538 { .input = &tegra_pll_a_out0, .value = 6},
2539 { .input = &tegra_sync_source_list[6], .value = 7},
2540 { 0, 0 }
2541};
2542
2543#define AUDIO_SYNC_CLK(_id, _index) \
2544 { \
2545 .name = #_id, \
2546 .inputs = mux_audio_sync_clk, \
2547 .reg = 0x4A0 + (_index) * 4, \
2548 .max_rate = 24000000, \
2549 .ops = &tegra_audio_sync_clk_ops \
2550 }
2551static struct clk tegra_clk_audio_list[] = {
2552 AUDIO_SYNC_CLK(audio0, 0),
2553 AUDIO_SYNC_CLK(audio1, 1),
2554 AUDIO_SYNC_CLK(audio2, 2),
2555 AUDIO_SYNC_CLK(audio3, 3),
2556 AUDIO_SYNC_CLK(audio4, 4),
2557 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
2558};
2559
2560#define AUDIO_SYNC_2X_CLK(_id, _index) \
2561 { \
2562 .name = #_id "_2x", \
2563 .flags = PERIPH_NO_RESET, \
2564 .max_rate = 48000000, \
2565 .ops = &tegra_clk_double_ops, \
2566 .reg = 0x49C, \
2567 .reg_shift = 24 + (_index), \
2568 .parent = &tegra_clk_audio_list[(_index)], \
2569 .u.periph = { \
2570 .clk_num = 113 + (_index), \
2571 }, \
2572 }
2573static struct clk tegra_clk_audio_2x_list[] = {
2574 AUDIO_SYNC_2X_CLK(audio0, 0),
2575 AUDIO_SYNC_2X_CLK(audio1, 1),
2576 AUDIO_SYNC_2X_CLK(audio2, 2),
2577 AUDIO_SYNC_2X_CLK(audio3, 3),
2578 AUDIO_SYNC_2X_CLK(audio4, 4),
2579 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
2580};
2581
2582#define MUX_I2S_SPDIF(_id, _index) \
2583static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
2584 {.input = &tegra_pll_a_out0, .value = 0}, \
2585 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
2586 {.input = &tegra_pll_p, .value = 2}, \
2587 {.input = &tegra_clk_m, .value = 3}, \
2588 { 0, 0}, \
2589}
2590MUX_I2S_SPDIF(audio0, 0);
2591MUX_I2S_SPDIF(audio1, 1);
2592MUX_I2S_SPDIF(audio2, 2);
2593MUX_I2S_SPDIF(audio3, 3);
2594MUX_I2S_SPDIF(audio4, 4);
2595MUX_I2S_SPDIF(audio, 5); /* SPDIF */
2596
2597/* External clock outputs (through PMC) */
2598#define MUX_EXTERN_OUT(_id) \
2599static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
2600 {.input = &tegra_clk_m, .value = 0}, \
2601 {.input = &tegra_clk_m_div2, .value = 1}, \
2602 {.input = &tegra_clk_m_div4, .value = 2}, \
2603 {.input = NULL, .value = 3}, /* placeholder */ \
2604 { 0, 0}, \
2605}
2606MUX_EXTERN_OUT(1);
2607MUX_EXTERN_OUT(2);
2608MUX_EXTERN_OUT(3);
2609
2610static struct clk_mux_sel *mux_extern_out_list[] = {
2611 mux_clkm_clkm2_clkm4_extern1,
2612 mux_clkm_clkm2_clkm4_extern2,
2613 mux_clkm_clkm2_clkm4_extern3,
2614};
2615
2616#define CLK_OUT_CLK(_id) \
2617 { \
2618 .name = "clk_out_" #_id, \
2619 .lookup = { \
2620 .dev_id = "clk_out_" #_id, \
2621 .con_id = "extern" #_id, \
2622 }, \
2623 .ops = &tegra_clk_out_ops, \
2624 .reg = 0x1a8, \
2625 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
2626 .flags = MUX_CLK_OUT, \
2627 .max_rate = 216000000, \
2628 .u.periph = { \
2629 .clk_num = (_id - 1) * 8 + 2, \
2630 }, \
2631 }
2632static struct clk tegra_clk_out_list[] = {
2633 CLK_OUT_CLK(1),
2634 CLK_OUT_CLK(2),
2635 CLK_OUT_CLK(3),
2636};
2637
2638/* called after peripheral external clocks are initialized */
2639static void init_clk_out_mux(void)
2640{
2641 int i;
2642 struct clk *c;
2643
2644 /* output clock con_id is the name of peripheral
2645 external clock connected to input 3 of the output mux */
2646 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
2647 c = tegra_get_clock_by_name(
2648 tegra_clk_out_list[i].lookup.con_id);
2649 if (!c)
2650 pr_err("%s: could not find clk %s\n", __func__,
2651 tegra_clk_out_list[i].lookup.con_id);
2652 mux_extern_out_list[i][3].input = c;
2653 }
2654}
2655
2656/* Peripheral muxes */
2657static struct clk_mux_sel mux_sclk[] = {
2658 { .input = &tegra_clk_m, .value = 0},
2659 { .input = &tegra_pll_c_out1, .value = 1},
2660 { .input = &tegra_pll_p_out4, .value = 2},
2661 { .input = &tegra_pll_p_out3, .value = 3},
2662 { .input = &tegra_pll_p_out2, .value = 4},
2663 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
2664 { .input = &tegra_clk_32k, .value = 6},
2665 { .input = &tegra_pll_m_out1, .value = 7},
2666 { 0, 0},
2667};
2668
2669static struct clk tegra_clk_sclk = {
2670 .name = "sclk",
2671 .inputs = mux_sclk,
2672 .reg = 0x28,
2673 .ops = &tegra_super_ops,
2674 .max_rate = 334000000,
2675 .min_rate = 40000000,
2676};
2677
2678static struct clk tegra_clk_blink = {
2679 .name = "blink",
2680 .parent = &tegra_clk_32k,
2681 .reg = 0x40,
2682 .ops = &tegra_blink_clk_ops,
2683 .max_rate = 32768,
2684};
2685
2686static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2687 { .input = &tegra_pll_m, .value = 0},
2688 { .input = &tegra_pll_c, .value = 1},
2689 { .input = &tegra_pll_p, .value = 2},
2690 { .input = &tegra_pll_a_out0, .value = 3},
2691 { 0, 0},
2692};
2693
2694static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2695 { .input = &tegra_pll_p, .value = 0},
2696 { .input = &tegra_pll_c, .value = 1},
2697 { .input = &tegra_pll_m, .value = 2},
2698 { .input = &tegra_clk_m, .value = 3},
2699 { 0, 0},
2700};
2701
2702static struct clk_mux_sel mux_pllp_clkm[] = {
2703 { .input = &tegra_pll_p, .value = 0},
2704 { .input = &tegra_clk_m, .value = 3},
2705 { 0, 0},
2706};
2707
2708static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2709 {.input = &tegra_pll_p, .value = 0},
2710 {.input = &tegra_pll_d_out0, .value = 1},
2711 {.input = &tegra_pll_c, .value = 2},
2712 {.input = &tegra_clk_m, .value = 3},
2713 { 0, 0},
2714};
2715
2716static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
2717 {.input = &tegra_pll_p, .value = 0},
2718 {.input = &tegra_pll_m, .value = 1},
2719 {.input = &tegra_pll_d_out0, .value = 2},
2720 {.input = &tegra_pll_a_out0, .value = 3},
2721 {.input = &tegra_pll_c, .value = 4},
2722 {.input = &tegra_pll_d2_out0, .value = 5},
2723 {.input = &tegra_clk_m, .value = 6},
2724 { 0, 0},
2725};
2726
2727static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
2728 { .input = &tegra_pll_a_out0, .value = 0},
2729 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
2730 { .input = &tegra_pll_p, .value = 2},
2731 { .input = &tegra_clk_m, .value = 3},
2732 { 0, 0},
2733};
2734
2735static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
2736 {.input = &tegra_pll_p, .value = 0},
2737 {.input = &tegra_pll_c, .value = 1},
2738 {.input = &tegra_clk_32k, .value = 2},
2739 {.input = &tegra_clk_m, .value = 3},
2740 { 0, 0},
2741};
2742
2743static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
2744 {.input = &tegra_pll_p, .value = 0},
2745 {.input = &tegra_pll_c, .value = 1},
2746 {.input = &tegra_clk_m, .value = 2},
2747 {.input = &tegra_clk_32k, .value = 3},
2748 { 0, 0},
2749};
2750
2751static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2752 {.input = &tegra_pll_p, .value = 0},
2753 {.input = &tegra_pll_c, .value = 1},
2754 {.input = &tegra_pll_m, .value = 2},
2755 { 0, 0},
2756};
2757
2758static struct clk_mux_sel mux_clk_m[] = {
2759 { .input = &tegra_clk_m, .value = 0},
2760 { 0, 0},
2761};
2762
2763static struct clk_mux_sel mux_pllp_out3[] = {
2764 { .input = &tegra_pll_p_out3, .value = 0},
2765 { 0, 0},
2766};
2767
2768static struct clk_mux_sel mux_plld_out0[] = {
2769 { .input = &tegra_pll_d_out0, .value = 0},
2770 { 0, 0},
2771};
2772
2773static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
2774 { .input = &tegra_pll_d_out0, .value = 0},
2775 { .input = &tegra_pll_d2_out0, .value = 1},
2776 { 0, 0},
2777};
2778
2779static struct clk_mux_sel mux_clk_32k[] = {
2780 { .input = &tegra_clk_32k, .value = 0},
2781 { 0, 0},
2782};
2783
2784static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
2785 { .input = &tegra_pll_a_out0, .value = 0},
2786 { .input = &tegra_clk_32k, .value = 1},
2787 { .input = &tegra_pll_p, .value = 2},
2788 { .input = &tegra_clk_m, .value = 3},
2789 { .input = &tegra_pll_e, .value = 4},
2790 { 0, 0},
2791};
2792
2793static struct clk_mux_sel mux_cclk_g[] = {
2794 { .input = &tegra_clk_m, .value = 0},
2795 { .input = &tegra_pll_c, .value = 1},
2796 { .input = &tegra_clk_32k, .value = 2},
2797 { .input = &tegra_pll_m, .value = 3},
2798 { .input = &tegra_pll_p, .value = 4},
2799 { .input = &tegra_pll_p_out4, .value = 5},
2800 { .input = &tegra_pll_p_out3, .value = 6},
2801 { .input = &tegra_pll_x, .value = 8},
2802 { 0, 0},
2803};
2804
2805static struct clk tegra_clk_cclk_g = {
2806 .name = "cclk_g",
2807 .flags = DIV_U71 | DIV_U71_INT,
2808 .inputs = mux_cclk_g,
2809 .reg = 0x368,
2810 .ops = &tegra_super_ops,
2811 .max_rate = 1700000000,
2812};
2813
2814static struct clk tegra30_clk_twd = {
2815 .parent = &tegra_clk_cclk_g,
2816 .name = "twd",
2817 .ops = &tegra30_twd_ops,
2818 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
2819 .mul = 1,
2820 .div = 2,
2821};
2822
2823#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2824 { \
2825 .name = _name, \
2826 .lookup = { \
2827 .dev_id = _dev, \
2828 .con_id = _con, \
2829 }, \
2830 .ops = &tegra_periph_clk_ops, \
2831 .reg = _reg, \
2832 .inputs = _inputs, \
2833 .flags = _flags, \
2834 .max_rate = _max, \
2835 .u.periph = { \
2836 .clk_num = _clk_num, \
2837 }, \
2838 }
2839
2840#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
2841 _flags, _ops) \
2842 { \
2843 .name = _name, \
2844 .lookup = { \
2845 .dev_id = _dev, \
2846 .con_id = _con, \
2847 }, \
2848 .ops = _ops, \
2849 .reg = _reg, \
2850 .inputs = _inputs, \
2851 .flags = _flags, \
2852 .max_rate = _max, \
2853 .u.periph = { \
2854 .clk_num = _clk_num, \
2855 }, \
2856 }
2857
2858#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
2859 { \
2860 .name = _name, \
2861 .lookup = { \
2862 .dev_id = _dev, \
2863 .con_id = _con, \
2864 }, \
2865 .ops = &tegra_clk_shared_bus_ops, \
2866 .parent = _parent, \
2867 .u.shared_bus_user = { \
2868 .client_id = _id, \
2869 .client_div = _div, \
2870 .mode = _mode, \
2871 }, \
2872 }
2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2878 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
2879 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2880 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2881 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
2882 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2883 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2884 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2885 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2893 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2894 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2895 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2896 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
2897 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2898 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2899 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2900 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2901 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2902 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2903 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2904 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2905 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
2906 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
2907 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2908 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2909 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2910 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2911 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2912 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2913 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2914 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2915 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2916 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2917 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2918 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2919 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2920 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2921 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
2922 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2923 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2933 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2934 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2935 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
2936 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
2937 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2938 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2939 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2940 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2941 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2942 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
2943 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
2944 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2945 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2946 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2947 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2948 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2949 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2950 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
2951 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
2952 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
2953 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2954 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2955
2956 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
2957 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
2958 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2959 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2960 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2961 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2962 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
2963 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
2964 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2965};
2966
2967#define CLK_DUPLICATE(_name, _dev, _con) \
2968 { \
2969 .name = _name, \
2970 .lookup = { \
2971 .dev_id = _dev, \
2972 .con_id = _con, \
2973 }, \
2974 }
2975
2976/* Some clocks may be used by different drivers depending on the board
2977 * configuration. List those here to register them twice in the clock lookup
2978 * table under two names.
2979 */
2980struct clk_duplicate tegra_clk_duplicates[] = {
2981 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2982 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2983 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2984 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2985 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2989 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2994 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2995 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2996 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
2997 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
2998 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
2999 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
3000 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
3001 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
3002 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
3003 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
3004 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
3005 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
3006 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
3007 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
3008 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
3009 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
3010 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
3011 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
3012 CLK_DUPLICATE("twd", "smp_twd", NULL),
3013 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
3014 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
3015 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
3016 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
3017 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
3018 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
3019 CLK_DUPLICATE("dam0", NULL, "dam0"),
3020 CLK_DUPLICATE("dam1", NULL, "dam1"),
3021 CLK_DUPLICATE("dam2", NULL, "dam2"),
3022 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
3023};
3024
3025struct clk *tegra_ptr_clks[] = {
3026 &tegra_clk_32k,
3027 &tegra_clk_m,
3028 &tegra_clk_m_div2,
3029 &tegra_clk_m_div4,
3030 &tegra_pll_ref,
3031 &tegra_pll_m,
3032 &tegra_pll_m_out1,
3033 &tegra_pll_c,
3034 &tegra_pll_c_out1,
3035 &tegra_pll_p,
3036 &tegra_pll_p_out1,
3037 &tegra_pll_p_out2,
3038 &tegra_pll_p_out3,
3039 &tegra_pll_p_out4,
3040 &tegra_pll_a,
3041 &tegra_pll_a_out0,
3042 &tegra_pll_d,
3043 &tegra_pll_d_out0,
3044 &tegra_pll_d2,
3045 &tegra_pll_d2_out0,
3046 &tegra_pll_u,
3047 &tegra_pll_x,
3048 &tegra_pll_x_out0,
3049 &tegra_pll_e,
3050 &tegra_clk_cclk_g,
3051 &tegra_cml0_clk,
3052 &tegra_cml1_clk,
3053 &tegra_pciex_clk,
3054 &tegra_clk_sclk,
3055 &tegra_clk_blink,
3056 &tegra30_clk_twd,
3057};
3058
3059
3060static void tegra30_init_one_clock(struct clk *c)
3061{
3062 clk_init(c);
3063 INIT_LIST_HEAD(&c->shared_bus_list);
3064 if (!c->lookup.dev_id && !c->lookup.con_id)
3065 c->lookup.con_id = c->name;
3066 c->lookup.clk = c;
3067 clkdev_add(&c->lookup);
3068}
3069
3070void __init tegra30_init_clocks(void)
3071{
3072 int i;
3073 struct clk *c;
3074
3075 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
3076 tegra30_init_one_clock(tegra_ptr_clks[i]);
3077
3078 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
3079 tegra30_init_one_clock(&tegra_list_clks[i]);
3080
3081 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
3082 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
3083 if (!c) {
3084 pr_err("%s: Unknown duplicate clock %s\n", __func__,
3085 tegra_clk_duplicates[i].name);
3086 continue;
3087 }
3088
3089 tegra_clk_duplicates[i].lookup.clk = c;
3090 clkdev_add(&tegra_clk_duplicates[i].lookup);
3091 }
3092
3093 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
3094 tegra30_init_one_clock(&tegra_sync_source_list[i]);
3095 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
3096 tegra30_init_one_clock(&tegra_clk_audio_list[i]);
3097 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
3098 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
3099
3100 init_clk_out_mux();
3101 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
3102 tegra30_init_one_clock(&tegra_clk_out_list[i]);
3103
3104}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 000000000000..f8c4df5f53f7
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA30_CLOCK_H
18#define __MACH_TEGRA30_CLOCK_H
19
20extern struct clk_ops tegra30_clk_m_ops;
21extern struct clk_ops tegra_clk_m_div_ops;
22extern struct clk_ops tegra_pll_ref_ops;
23extern struct clk_ops tegra30_pll_ops;
24extern struct clk_ops tegra30_pll_div_ops;
25extern struct clk_ops tegra_plld_ops;
26extern struct clk_ops tegra30_plle_ops;
27extern struct clk_ops tegra_cml_clk_ops;
28extern struct clk_ops tegra_pciex_clk_ops;
29extern struct clk_ops tegra_sync_source_ops;
30extern struct clk_ops tegra30_audio_sync_clk_ops;
31extern struct clk_ops tegra30_clk_double_ops;
32extern struct clk_ops tegra_clk_out_ops;
33extern struct clk_ops tegra30_super_ops;
34extern struct clk_ops tegra30_blink_clk_ops;
35extern struct clk_ops tegra30_twd_ops;
36extern struct clk_ops tegra30_periph_clk_ops;
37extern struct clk_ops tegra_dsib_clk_ops;
38extern struct clk_ops tegra_nand_clk_ops;
39extern struct clk_ops tegra_vi_clk_ops;
40extern struct clk_ops tegra_dtv_clk_ops;
41extern struct clk_ops tegra_clk_shared_bus_ops;
42
43#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 000000000000..b1243c9e8ef7
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1144 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks_data.c
3 *
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29#include <linux/cpufreq.h>
30
31#include <asm/clkdev.h>
32
33#include <mach/iomap.h>
34
35#include "clock.h"
36#include "fuse.h"
37#include "tegra30_clocks.h"
38
39/* Clock definitions */
40static struct clk tegra_clk_32k = {
41 .name = "clk_32k",
42 .rate = 32768,
43 .ops = NULL,
44 .max_rate = 32768,
45};
46
47static struct clk tegra_clk_m = {
48 .name = "clk_m",
49 .flags = ENABLE_ON_INIT,
50 .ops = &tegra30_clk_m_ops,
51 .reg = 0x1fc,
52 .reg_shift = 28,
53 .max_rate = 48000000,
54};
55
56static struct clk tegra_clk_m_div2 = {
57 .name = "clk_m_div2",
58 .ops = &tegra_clk_m_div_ops,
59 .parent = &tegra_clk_m,
60 .mul = 1,
61 .div = 2,
62 .state = ON,
63 .max_rate = 24000000,
64};
65
66static struct clk tegra_clk_m_div4 = {
67 .name = "clk_m_div4",
68 .ops = &tegra_clk_m_div_ops,
69 .parent = &tegra_clk_m,
70 .mul = 1,
71 .div = 4,
72 .state = ON,
73 .max_rate = 12000000,
74};
75
76static struct clk tegra_pll_ref = {
77 .name = "pll_ref",
78 .flags = ENABLE_ON_INIT,
79 .ops = &tegra_pll_ref_ops,
80 .parent = &tegra_clk_m,
81 .max_rate = 26000000,
82};
83
84static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
85 { 12000000, 1040000000, 520, 6, 1, 8},
86 { 13000000, 1040000000, 480, 6, 1, 8},
87 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
88 { 19200000, 1040000000, 325, 6, 1, 6},
89 { 26000000, 1040000000, 520, 13, 1, 8},
90
91 { 12000000, 832000000, 416, 6, 1, 8},
92 { 13000000, 832000000, 832, 13, 1, 8},
93 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
94 { 19200000, 832000000, 260, 6, 1, 8},
95 { 26000000, 832000000, 416, 13, 1, 8},
96
97 { 12000000, 624000000, 624, 12, 1, 8},
98 { 13000000, 624000000, 624, 13, 1, 8},
99 { 16800000, 600000000, 520, 14, 1, 8},
100 { 19200000, 624000000, 520, 16, 1, 8},
101 { 26000000, 624000000, 624, 26, 1, 8},
102
103 { 12000000, 600000000, 600, 12, 1, 8},
104 { 13000000, 600000000, 600, 13, 1, 8},
105 { 16800000, 600000000, 500, 14, 1, 8},
106 { 19200000, 600000000, 375, 12, 1, 6},
107 { 26000000, 600000000, 600, 26, 1, 8},
108
109 { 12000000, 520000000, 520, 12, 1, 8},
110 { 13000000, 520000000, 520, 13, 1, 8},
111 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
112 { 19200000, 520000000, 325, 12, 1, 6},
113 { 26000000, 520000000, 520, 26, 1, 8},
114
115 { 12000000, 416000000, 416, 12, 1, 8},
116 { 13000000, 416000000, 416, 13, 1, 8},
117 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
118 { 19200000, 416000000, 260, 12, 1, 6},
119 { 26000000, 416000000, 416, 26, 1, 8},
120 { 0, 0, 0, 0, 0, 0 },
121};
122
123static struct clk tegra_pll_c = {
124 .name = "pll_c",
125 .flags = PLL_HAS_CPCON,
126 .ops = &tegra30_pll_ops,
127 .reg = 0x80,
128 .parent = &tegra_pll_ref,
129 .max_rate = 1400000000,
130 .u.pll = {
131 .input_min = 2000000,
132 .input_max = 31000000,
133 .cf_min = 1000000,
134 .cf_max = 6000000,
135 .vco_min = 20000000,
136 .vco_max = 1400000000,
137 .freq_table = tegra_pll_c_freq_table,
138 .lock_delay = 300,
139 },
140};
141
142static struct clk tegra_pll_c_out1 = {
143 .name = "pll_c_out1",
144 .ops = &tegra30_pll_div_ops,
145 .flags = DIV_U71,
146 .parent = &tegra_pll_c,
147 .reg = 0x84,
148 .reg_shift = 0,
149 .max_rate = 700000000,
150};
151
152static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
153 { 12000000, 666000000, 666, 12, 1, 8},
154 { 13000000, 666000000, 666, 13, 1, 8},
155 { 16800000, 666000000, 555, 14, 1, 8},
156 { 19200000, 666000000, 555, 16, 1, 8},
157 { 26000000, 666000000, 666, 26, 1, 8},
158 { 12000000, 600000000, 600, 12, 1, 8},
159 { 13000000, 600000000, 600, 13, 1, 8},
160 { 16800000, 600000000, 500, 14, 1, 8},
161 { 19200000, 600000000, 375, 12, 1, 6},
162 { 26000000, 600000000, 600, 26, 1, 8},
163 { 0, 0, 0, 0, 0, 0 },
164};
165
166static struct clk tegra_pll_m = {
167 .name = "pll_m",
168 .flags = PLL_HAS_CPCON | PLLM,
169 .ops = &tegra30_pll_ops,
170 .reg = 0x90,
171 .parent = &tegra_pll_ref,
172 .max_rate = 800000000,
173 .u.pll = {
174 .input_min = 2000000,
175 .input_max = 31000000,
176 .cf_min = 1000000,
177 .cf_max = 6000000,
178 .vco_min = 20000000,
179 .vco_max = 1200000000,
180 .freq_table = tegra_pll_m_freq_table,
181 .lock_delay = 300,
182 },
183};
184
185static struct clk tegra_pll_m_out1 = {
186 .name = "pll_m_out1",
187 .ops = &tegra30_pll_div_ops,
188 .flags = DIV_U71,
189 .parent = &tegra_pll_m,
190 .reg = 0x94,
191 .reg_shift = 0,
192 .max_rate = 600000000,
193};
194
195static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
196 { 12000000, 216000000, 432, 12, 2, 8},
197 { 13000000, 216000000, 432, 13, 2, 8},
198 { 16800000, 216000000, 360, 14, 2, 8},
199 { 19200000, 216000000, 360, 16, 2, 8},
200 { 26000000, 216000000, 432, 26, 2, 8},
201 { 0, 0, 0, 0, 0, 0 },
202};
203
204static struct clk tegra_pll_p = {
205 .name = "pll_p",
206 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
207 .ops = &tegra30_pll_ops,
208 .reg = 0xa0,
209 .parent = &tegra_pll_ref,
210 .max_rate = 432000000,
211 .u.pll = {
212 .input_min = 2000000,
213 .input_max = 31000000,
214 .cf_min = 1000000,
215 .cf_max = 6000000,
216 .vco_min = 20000000,
217 .vco_max = 1400000000,
218 .freq_table = tegra_pll_p_freq_table,
219 .lock_delay = 300,
220 .fixed_rate = 408000000,
221 },
222};
223
224static struct clk tegra_pll_p_out1 = {
225 .name = "pll_p_out1",
226 .ops = &tegra30_pll_div_ops,
227 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
228 .parent = &tegra_pll_p,
229 .reg = 0xa4,
230 .reg_shift = 0,
231 .max_rate = 432000000,
232};
233
234static struct clk tegra_pll_p_out2 = {
235 .name = "pll_p_out2",
236 .ops = &tegra30_pll_div_ops,
237 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
238 .parent = &tegra_pll_p,
239 .reg = 0xa4,
240 .reg_shift = 16,
241 .max_rate = 432000000,
242};
243
244static struct clk tegra_pll_p_out3 = {
245 .name = "pll_p_out3",
246 .ops = &tegra30_pll_div_ops,
247 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
248 .parent = &tegra_pll_p,
249 .reg = 0xa8,
250 .reg_shift = 0,
251 .max_rate = 432000000,
252};
253
254static struct clk tegra_pll_p_out4 = {
255 .name = "pll_p_out4",
256 .ops = &tegra30_pll_div_ops,
257 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
258 .parent = &tegra_pll_p,
259 .reg = 0xa8,
260 .reg_shift = 16,
261 .max_rate = 432000000,
262};
263
264static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
265 { 9600000, 564480000, 294, 5, 1, 4},
266 { 9600000, 552960000, 288, 5, 1, 4},
267 { 9600000, 24000000, 5, 2, 1, 1},
268
269 { 28800000, 56448000, 49, 25, 1, 1},
270 { 28800000, 73728000, 64, 25, 1, 1},
271 { 28800000, 24000000, 5, 6, 1, 1},
272 { 0, 0, 0, 0, 0, 0 },
273};
274
275static struct clk tegra_pll_a = {
276 .name = "pll_a",
277 .flags = PLL_HAS_CPCON,
278 .ops = &tegra30_pll_ops,
279 .reg = 0xb0,
280 .parent = &tegra_pll_p_out1,
281 .max_rate = 700000000,
282 .u.pll = {
283 .input_min = 2000000,
284 .input_max = 31000000,
285 .cf_min = 1000000,
286 .cf_max = 6000000,
287 .vco_min = 20000000,
288 .vco_max = 1400000000,
289 .freq_table = tegra_pll_a_freq_table,
290 .lock_delay = 300,
291 },
292};
293
294static struct clk tegra_pll_a_out0 = {
295 .name = "pll_a_out0",
296 .ops = &tegra30_pll_div_ops,
297 .flags = DIV_U71,
298 .parent = &tegra_pll_a,
299 .reg = 0xb4,
300 .reg_shift = 0,
301 .max_rate = 100000000,
302};
303
304static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
305 { 12000000, 216000000, 216, 12, 1, 4},
306 { 13000000, 216000000, 216, 13, 1, 4},
307 { 16800000, 216000000, 180, 14, 1, 4},
308 { 19200000, 216000000, 180, 16, 1, 4},
309 { 26000000, 216000000, 216, 26, 1, 4},
310
311 { 12000000, 594000000, 594, 12, 1, 8},
312 { 13000000, 594000000, 594, 13, 1, 8},
313 { 16800000, 594000000, 495, 14, 1, 8},
314 { 19200000, 594000000, 495, 16, 1, 8},
315 { 26000000, 594000000, 594, 26, 1, 8},
316
317 { 12000000, 1000000000, 1000, 12, 1, 12},
318 { 13000000, 1000000000, 1000, 13, 1, 12},
319 { 19200000, 1000000000, 625, 12, 1, 8},
320 { 26000000, 1000000000, 1000, 26, 1, 12},
321
322 { 0, 0, 0, 0, 0, 0 },
323};
324
325static struct clk tegra_pll_d = {
326 .name = "pll_d",
327 .flags = PLL_HAS_CPCON | PLLD,
328 .ops = &tegra_plld_ops,
329 .reg = 0xd0,
330 .parent = &tegra_pll_ref,
331 .max_rate = 1000000000,
332 .u.pll = {
333 .input_min = 2000000,
334 .input_max = 40000000,
335 .cf_min = 1000000,
336 .cf_max = 6000000,
337 .vco_min = 40000000,
338 .vco_max = 1000000000,
339 .freq_table = tegra_pll_d_freq_table,
340 .lock_delay = 1000,
341 },
342};
343
344static struct clk tegra_pll_d_out0 = {
345 .name = "pll_d_out0",
346 .ops = &tegra30_pll_div_ops,
347 .flags = DIV_2 | PLLD,
348 .parent = &tegra_pll_d,
349 .max_rate = 500000000,
350};
351
352static struct clk tegra_pll_d2 = {
353 .name = "pll_d2",
354 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
355 .ops = &tegra_plld_ops,
356 .reg = 0x4b8,
357 .parent = &tegra_pll_ref,
358 .max_rate = 1000000000,
359 .u.pll = {
360 .input_min = 2000000,
361 .input_max = 40000000,
362 .cf_min = 1000000,
363 .cf_max = 6000000,
364 .vco_min = 40000000,
365 .vco_max = 1000000000,
366 .freq_table = tegra_pll_d_freq_table,
367 .lock_delay = 1000,
368 },
369};
370
371static struct clk tegra_pll_d2_out0 = {
372 .name = "pll_d2_out0",
373 .ops = &tegra30_pll_div_ops,
374 .flags = DIV_2 | PLLD,
375 .parent = &tegra_pll_d2,
376 .max_rate = 500000000,
377};
378
379static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
380 { 12000000, 480000000, 960, 12, 2, 12},
381 { 13000000, 480000000, 960, 13, 2, 12},
382 { 16800000, 480000000, 400, 7, 2, 5},
383 { 19200000, 480000000, 200, 4, 2, 3},
384 { 26000000, 480000000, 960, 26, 2, 12},
385 { 0, 0, 0, 0, 0, 0 },
386};
387
388static struct clk tegra_pll_u = {
389 .name = "pll_u",
390 .flags = PLL_HAS_CPCON | PLLU,
391 .ops = &tegra30_pll_ops,
392 .reg = 0xc0,
393 .parent = &tegra_pll_ref,
394 .max_rate = 480000000,
395 .u.pll = {
396 .input_min = 2000000,
397 .input_max = 40000000,
398 .cf_min = 1000000,
399 .cf_max = 6000000,
400 .vco_min = 480000000,
401 .vco_max = 960000000,
402 .freq_table = tegra_pll_u_freq_table,
403 .lock_delay = 1000,
404 },
405};
406
407static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
408 /* 1.7 GHz */
409 { 12000000, 1700000000, 850, 6, 1, 8},
410 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
411 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
412 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
413 { 26000000, 1700000000, 850, 13, 1, 8},
414
415 /* 1.6 GHz */
416 { 12000000, 1600000000, 800, 6, 1, 8},
417 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
418 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
419 { 19200000, 1600000000, 500, 6, 1, 8},
420 { 26000000, 1600000000, 800, 13, 1, 8},
421
422 /* 1.5 GHz */
423 { 12000000, 1500000000, 750, 6, 1, 8},
424 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
425 { 16800000, 1500000000, 625, 7, 1, 8},
426 { 19200000, 1500000000, 625, 8, 1, 8},
427 { 26000000, 1500000000, 750, 13, 1, 8},
428
429 /* 1.4 GHz */
430 { 12000000, 1400000000, 700, 6, 1, 8},
431 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
432 { 16800000, 1400000000, 1000, 12, 1, 8},
433 { 19200000, 1400000000, 875, 12, 1, 8},
434 { 26000000, 1400000000, 700, 13, 1, 8},
435
436 /* 1.3 GHz */
437 { 12000000, 1300000000, 975, 9, 1, 8},
438 { 13000000, 1300000000, 1000, 10, 1, 8},
439 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
440 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
441 { 26000000, 1300000000, 650, 13, 1, 8},
442
443 /* 1.2 GHz */
444 { 12000000, 1200000000, 1000, 10, 1, 8},
445 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
446 { 16800000, 1200000000, 1000, 14, 1, 8},
447 { 19200000, 1200000000, 1000, 16, 1, 8},
448 { 26000000, 1200000000, 600, 13, 1, 8},
449
450 /* 1.1 GHz */
451 { 12000000, 1100000000, 825, 9, 1, 8},
452 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
453 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
454 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
455 { 26000000, 1100000000, 550, 13, 1, 8},
456
457 /* 1 GHz */
458 { 12000000, 1000000000, 1000, 12, 1, 8},
459 { 13000000, 1000000000, 1000, 13, 1, 8},
460 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
461 { 19200000, 1000000000, 625, 12, 1, 8},
462 { 26000000, 1000000000, 1000, 26, 1, 8},
463
464 { 0, 0, 0, 0, 0, 0 },
465};
466
467static struct clk tegra_pll_x = {
468 .name = "pll_x",
469 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
470 .ops = &tegra30_pll_ops,
471 .reg = 0xe0,
472 .parent = &tegra_pll_ref,
473 .max_rate = 1700000000,
474 .u.pll = {
475 .input_min = 2000000,
476 .input_max = 31000000,
477 .cf_min = 1000000,
478 .cf_max = 6000000,
479 .vco_min = 20000000,
480 .vco_max = 1700000000,
481 .freq_table = tegra_pll_x_freq_table,
482 .lock_delay = 300,
483 },
484};
485
486static struct clk tegra_pll_x_out0 = {
487 .name = "pll_x_out0",
488 .ops = &tegra30_pll_div_ops,
489 .flags = DIV_2 | PLLX,
490 .parent = &tegra_pll_x,
491 .max_rate = 850000000,
492};
493
494
495static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
496 /* PLLE special case: use cpcon field to store cml divider value */
497 { 12000000, 100000000, 150, 1, 18, 11},
498 { 216000000, 100000000, 200, 18, 24, 13},
499 { 0, 0, 0, 0, 0, 0 },
500};
501
502static struct clk tegra_pll_e = {
503 .name = "pll_e",
504 .flags = PLL_ALT_MISC_REG,
505 .ops = &tegra30_plle_ops,
506 .reg = 0xe8,
507 .max_rate = 100000000,
508 .u.pll = {
509 .input_min = 12000000,
510 .input_max = 216000000,
511 .cf_min = 12000000,
512 .cf_max = 12000000,
513 .vco_min = 1200000000,
514 .vco_max = 2400000000U,
515 .freq_table = tegra_pll_e_freq_table,
516 .lock_delay = 300,
517 .fixed_rate = 100000000,
518 },
519};
520
521static struct clk tegra_cml0_clk = {
522 .name = "cml0",
523 .parent = &tegra_pll_e,
524 .ops = &tegra_cml_clk_ops,
525 .reg = 0x48c,
526 .max_rate = 100000000,
527 .u.periph = {
528 .clk_num = 0,
529 },
530};
531
532static struct clk tegra_cml1_clk = {
533 .name = "cml1",
534 .parent = &tegra_pll_e,
535 .ops = &tegra_cml_clk_ops,
536 .reg = 0x48c,
537 .max_rate = 100000000,
538 .u.periph = {
539 .clk_num = 1,
540 },
541};
542
543static struct clk tegra_pciex_clk = {
544 .name = "pciex",
545 .parent = &tegra_pll_e,
546 .ops = &tegra_pciex_clk_ops,
547 .max_rate = 100000000,
548 .u.periph = {
549 .clk_num = 74,
550 },
551};
552
553/* Audio sync clocks */
554#define SYNC_SOURCE(_id) \
555 { \
556 .name = #_id "_sync", \
557 .rate = 24000000, \
558 .max_rate = 24000000, \
559 .ops = &tegra_sync_source_ops \
560 }
561static struct clk tegra_sync_source_list[] = {
562 SYNC_SOURCE(spdif_in),
563 SYNC_SOURCE(i2s0),
564 SYNC_SOURCE(i2s1),
565 SYNC_SOURCE(i2s2),
566 SYNC_SOURCE(i2s3),
567 SYNC_SOURCE(i2s4),
568 SYNC_SOURCE(vimclk),
569};
570
571static struct clk_mux_sel mux_audio_sync_clk[] = {
572 { .input = &tegra_sync_source_list[0], .value = 0},
573 { .input = &tegra_sync_source_list[1], .value = 1},
574 { .input = &tegra_sync_source_list[2], .value = 2},
575 { .input = &tegra_sync_source_list[3], .value = 3},
576 { .input = &tegra_sync_source_list[4], .value = 4},
577 { .input = &tegra_sync_source_list[5], .value = 5},
578 { .input = &tegra_pll_a_out0, .value = 6},
579 { .input = &tegra_sync_source_list[6], .value = 7},
580 { 0, 0 }
581};
582
583#define AUDIO_SYNC_CLK(_id, _index) \
584 { \
585 .name = #_id, \
586 .inputs = mux_audio_sync_clk, \
587 .reg = 0x4A0 + (_index) * 4, \
588 .max_rate = 24000000, \
589 .ops = &tegra30_audio_sync_clk_ops \
590 }
591static struct clk tegra_clk_audio_list[] = {
592 AUDIO_SYNC_CLK(audio0, 0),
593 AUDIO_SYNC_CLK(audio1, 1),
594 AUDIO_SYNC_CLK(audio2, 2),
595 AUDIO_SYNC_CLK(audio3, 3),
596 AUDIO_SYNC_CLK(audio4, 4),
597 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
598};
599
600#define AUDIO_SYNC_2X_CLK(_id, _index) \
601 { \
602 .name = #_id "_2x", \
603 .flags = PERIPH_NO_RESET, \
604 .max_rate = 48000000, \
605 .ops = &tegra30_clk_double_ops, \
606 .reg = 0x49C, \
607 .reg_shift = 24 + (_index), \
608 .parent = &tegra_clk_audio_list[(_index)], \
609 .u.periph = { \
610 .clk_num = 113 + (_index), \
611 }, \
612 }
613static struct clk tegra_clk_audio_2x_list[] = {
614 AUDIO_SYNC_2X_CLK(audio0, 0),
615 AUDIO_SYNC_2X_CLK(audio1, 1),
616 AUDIO_SYNC_2X_CLK(audio2, 2),
617 AUDIO_SYNC_2X_CLK(audio3, 3),
618 AUDIO_SYNC_2X_CLK(audio4, 4),
619 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
620};
621
622#define MUX_I2S_SPDIF(_id, _index) \
623static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
624 {.input = &tegra_pll_a_out0, .value = 0}, \
625 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
626 {.input = &tegra_pll_p, .value = 2}, \
627 {.input = &tegra_clk_m, .value = 3}, \
628 { 0, 0}, \
629}
630MUX_I2S_SPDIF(audio0, 0);
631MUX_I2S_SPDIF(audio1, 1);
632MUX_I2S_SPDIF(audio2, 2);
633MUX_I2S_SPDIF(audio3, 3);
634MUX_I2S_SPDIF(audio4, 4);
635MUX_I2S_SPDIF(audio, 5); /* SPDIF */
636
637/* External clock outputs (through PMC) */
638#define MUX_EXTERN_OUT(_id) \
639static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
640 {.input = &tegra_clk_m, .value = 0}, \
641 {.input = &tegra_clk_m_div2, .value = 1}, \
642 {.input = &tegra_clk_m_div4, .value = 2}, \
643 {.input = NULL, .value = 3}, /* placeholder */ \
644 { 0, 0}, \
645}
646MUX_EXTERN_OUT(1);
647MUX_EXTERN_OUT(2);
648MUX_EXTERN_OUT(3);
649
650static struct clk_mux_sel *mux_extern_out_list[] = {
651 mux_clkm_clkm2_clkm4_extern1,
652 mux_clkm_clkm2_clkm4_extern2,
653 mux_clkm_clkm2_clkm4_extern3,
654};
655
656#define CLK_OUT_CLK(_id) \
657 { \
658 .name = "clk_out_" #_id, \
659 .lookup = { \
660 .dev_id = "clk_out_" #_id, \
661 .con_id = "extern" #_id, \
662 }, \
663 .ops = &tegra_clk_out_ops, \
664 .reg = 0x1a8, \
665 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
666 .flags = MUX_CLK_OUT, \
667 .max_rate = 216000000, \
668 .u.periph = { \
669 .clk_num = (_id - 1) * 8 + 2, \
670 }, \
671 }
672static struct clk tegra_clk_out_list[] = {
673 CLK_OUT_CLK(1),
674 CLK_OUT_CLK(2),
675 CLK_OUT_CLK(3),
676};
677
678/* called after peripheral external clocks are initialized */
679static void init_clk_out_mux(void)
680{
681 int i;
682 struct clk *c;
683
684 /* output clock con_id is the name of peripheral
685 external clock connected to input 3 of the output mux */
686 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
687 c = tegra_get_clock_by_name(
688 tegra_clk_out_list[i].lookup.con_id);
689 if (!c)
690 pr_err("%s: could not find clk %s\n", __func__,
691 tegra_clk_out_list[i].lookup.con_id);
692 mux_extern_out_list[i][3].input = c;
693 }
694}
695
696/* Peripheral muxes */
697static struct clk_mux_sel mux_sclk[] = {
698 { .input = &tegra_clk_m, .value = 0},
699 { .input = &tegra_pll_c_out1, .value = 1},
700 { .input = &tegra_pll_p_out4, .value = 2},
701 { .input = &tegra_pll_p_out3, .value = 3},
702 { .input = &tegra_pll_p_out2, .value = 4},
703 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
704 { .input = &tegra_clk_32k, .value = 6},
705 { .input = &tegra_pll_m_out1, .value = 7},
706 { 0, 0},
707};
708
709static struct clk tegra_clk_sclk = {
710 .name = "sclk",
711 .inputs = mux_sclk,
712 .reg = 0x28,
713 .ops = &tegra30_super_ops,
714 .max_rate = 334000000,
715 .min_rate = 40000000,
716};
717
718static struct clk tegra_clk_blink = {
719 .name = "blink",
720 .parent = &tegra_clk_32k,
721 .reg = 0x40,
722 .ops = &tegra30_blink_clk_ops,
723 .max_rate = 32768,
724};
725
726static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
727 { .input = &tegra_pll_m, .value = 0},
728 { .input = &tegra_pll_c, .value = 1},
729 { .input = &tegra_pll_p, .value = 2},
730 { .input = &tegra_pll_a_out0, .value = 3},
731 { 0, 0},
732};
733
734static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
735 { .input = &tegra_pll_p, .value = 0},
736 { .input = &tegra_pll_c, .value = 1},
737 { .input = &tegra_pll_m, .value = 2},
738 { .input = &tegra_clk_m, .value = 3},
739 { 0, 0},
740};
741
742static struct clk_mux_sel mux_pllp_clkm[] = {
743 { .input = &tegra_pll_p, .value = 0},
744 { .input = &tegra_clk_m, .value = 3},
745 { 0, 0},
746};
747
748static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
749 {.input = &tegra_pll_p, .value = 0},
750 {.input = &tegra_pll_d_out0, .value = 1},
751 {.input = &tegra_pll_c, .value = 2},
752 {.input = &tegra_clk_m, .value = 3},
753 { 0, 0},
754};
755
756static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
757 {.input = &tegra_pll_p, .value = 0},
758 {.input = &tegra_pll_m, .value = 1},
759 {.input = &tegra_pll_d_out0, .value = 2},
760 {.input = &tegra_pll_a_out0, .value = 3},
761 {.input = &tegra_pll_c, .value = 4},
762 {.input = &tegra_pll_d2_out0, .value = 5},
763 {.input = &tegra_clk_m, .value = 6},
764 { 0, 0},
765};
766
767static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
768 { .input = &tegra_pll_a_out0, .value = 0},
769 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
770 { .input = &tegra_pll_p, .value = 2},
771 { .input = &tegra_clk_m, .value = 3},
772 { 0, 0},
773};
774
775static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
776 {.input = &tegra_pll_p, .value = 0},
777 {.input = &tegra_pll_c, .value = 1},
778 {.input = &tegra_clk_32k, .value = 2},
779 {.input = &tegra_clk_m, .value = 3},
780 { 0, 0},
781};
782
783static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
784 {.input = &tegra_pll_p, .value = 0},
785 {.input = &tegra_pll_c, .value = 1},
786 {.input = &tegra_clk_m, .value = 2},
787 {.input = &tegra_clk_32k, .value = 3},
788 { 0, 0},
789};
790
791static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
792 {.input = &tegra_pll_p, .value = 0},
793 {.input = &tegra_pll_c, .value = 1},
794 {.input = &tegra_pll_m, .value = 2},
795 { 0, 0},
796};
797
798static struct clk_mux_sel mux_clk_m[] = {
799 { .input = &tegra_clk_m, .value = 0},
800 { 0, 0},
801};
802
803static struct clk_mux_sel mux_pllp_out3[] = {
804 { .input = &tegra_pll_p_out3, .value = 0},
805 { 0, 0},
806};
807
808static struct clk_mux_sel mux_plld_out0[] = {
809 { .input = &tegra_pll_d_out0, .value = 0},
810 { 0, 0},
811};
812
813static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
814 { .input = &tegra_pll_d_out0, .value = 0},
815 { .input = &tegra_pll_d2_out0, .value = 1},
816 { 0, 0},
817};
818
819static struct clk_mux_sel mux_clk_32k[] = {
820 { .input = &tegra_clk_32k, .value = 0},
821 { 0, 0},
822};
823
824static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
825 { .input = &tegra_pll_a_out0, .value = 0},
826 { .input = &tegra_clk_32k, .value = 1},
827 { .input = &tegra_pll_p, .value = 2},
828 { .input = &tegra_clk_m, .value = 3},
829 { .input = &tegra_pll_e, .value = 4},
830 { 0, 0},
831};
832
833static struct clk_mux_sel mux_cclk_g[] = {
834 { .input = &tegra_clk_m, .value = 0},
835 { .input = &tegra_pll_c, .value = 1},
836 { .input = &tegra_clk_32k, .value = 2},
837 { .input = &tegra_pll_m, .value = 3},
838 { .input = &tegra_pll_p, .value = 4},
839 { .input = &tegra_pll_p_out4, .value = 5},
840 { .input = &tegra_pll_p_out3, .value = 6},
841 { .input = &tegra_pll_x, .value = 8},
842 { 0, 0},
843};
844
845static struct clk tegra_clk_cclk_g = {
846 .name = "cclk_g",
847 .flags = DIV_U71 | DIV_U71_INT,
848 .inputs = mux_cclk_g,
849 .reg = 0x368,
850 .ops = &tegra30_super_ops,
851 .max_rate = 1700000000,
852};
853
854static struct clk tegra30_clk_twd = {
855 .parent = &tegra_clk_cclk_g,
856 .name = "twd",
857 .ops = &tegra30_twd_ops,
858 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
859 .mul = 1,
860 .div = 2,
861};
862
863#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
864 { \
865 .name = _name, \
866 .lookup = { \
867 .dev_id = _dev, \
868 .con_id = _con, \
869 }, \
870 .ops = &tegra30_periph_clk_ops, \
871 .reg = _reg, \
872 .inputs = _inputs, \
873 .flags = _flags, \
874 .max_rate = _max, \
875 .u.periph = { \
876 .clk_num = _clk_num, \
877 }, \
878 }
879
880#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
881 _flags, _ops) \
882 { \
883 .name = _name, \
884 .lookup = { \
885 .dev_id = _dev, \
886 .con_id = _con, \
887 }, \
888 .ops = _ops, \
889 .reg = _reg, \
890 .inputs = _inputs, \
891 .flags = _flags, \
892 .max_rate = _max, \
893 .u.periph = { \
894 .clk_num = _clk_num, \
895 }, \
896 }
897
898#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
899 { \
900 .name = _name, \
901 .lookup = { \
902 .dev_id = _dev, \
903 .con_id = _con, \
904 }, \
905 .ops = &tegra_clk_shared_bus_ops, \
906 .parent = _parent, \
907 .u.shared_bus_user = { \
908 .client_id = _id, \
909 .client_div = _div, \
910 .mode = _mode, \
911 }, \
912 }
913struct clk tegra_list_clks[] = {
914 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
915 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
916 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
917 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
918 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
919 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
920 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
921 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
922 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
923 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
924 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
925 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
926 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
927 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
928 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
929 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
930 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
931 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
932 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
933 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
934 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
935 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
936 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
937 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
938 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
939 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
940 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
941 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
942 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
943 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
944 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
945 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
946 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
947 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
948 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
949 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
950 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
951 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
952 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
953 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
954 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
955 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
956 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
957 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
958 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
959 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
960 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
961 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
962 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
963 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
964 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
965 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
966 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
967 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
968 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
969 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
970 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
971 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
972 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
973 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
974 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
975 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
976 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
977 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
978 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
979 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
980 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
981 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
982 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
983 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
984 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
985 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
986 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
987 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
988 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
989 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
990 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
991 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
992 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
993 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
994 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
995
996 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
997 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
998 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
999 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
1000 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
1001 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
1002 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
1003 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
1004 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
1005};
1006
1007#define CLK_DUPLICATE(_name, _dev, _con) \
1008 { \
1009 .name = _name, \
1010 .lookup = { \
1011 .dev_id = _dev, \
1012 .con_id = _con, \
1013 }, \
1014 }
1015
1016/* Some clocks may be used by different drivers depending on the board
1017 * configuration. List those here to register them twice in the clock lookup
1018 * table under two names.
1019 */
1020struct clk_duplicate tegra_clk_duplicates[] = {
1021 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1022 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1023 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1024 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1025 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1026 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1027 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1028 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1029 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1030 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1031 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1032 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1033 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1034 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1035 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1036 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1037 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1038 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1039 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1040 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1041 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1042 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1043 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1044 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1045 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1046 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1047 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1048 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1049 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1050 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1051 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1052 CLK_DUPLICATE("twd", "smp_twd", NULL),
1053 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1054 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1055 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1056 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1057 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1058 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1059 CLK_DUPLICATE("dam0", NULL, "dam0"),
1060 CLK_DUPLICATE("dam1", NULL, "dam1"),
1061 CLK_DUPLICATE("dam2", NULL, "dam2"),
1062 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1063};
1064
1065struct clk *tegra_ptr_clks[] = {
1066 &tegra_clk_32k,
1067 &tegra_clk_m,
1068 &tegra_clk_m_div2,
1069 &tegra_clk_m_div4,
1070 &tegra_pll_ref,
1071 &tegra_pll_m,
1072 &tegra_pll_m_out1,
1073 &tegra_pll_c,
1074 &tegra_pll_c_out1,
1075 &tegra_pll_p,
1076 &tegra_pll_p_out1,
1077 &tegra_pll_p_out2,
1078 &tegra_pll_p_out3,
1079 &tegra_pll_p_out4,
1080 &tegra_pll_a,
1081 &tegra_pll_a_out0,
1082 &tegra_pll_d,
1083 &tegra_pll_d_out0,
1084 &tegra_pll_d2,
1085 &tegra_pll_d2_out0,
1086 &tegra_pll_u,
1087 &tegra_pll_x,
1088 &tegra_pll_x_out0,
1089 &tegra_pll_e,
1090 &tegra_clk_cclk_g,
1091 &tegra_cml0_clk,
1092 &tegra_cml1_clk,
1093 &tegra_pciex_clk,
1094 &tegra_clk_sclk,
1095 &tegra_clk_blink,
1096 &tegra30_clk_twd,
1097};
1098
1099
1100static void tegra30_init_one_clock(struct clk *c)
1101{
1102 clk_init(c);
1103 INIT_LIST_HEAD(&c->shared_bus_list);
1104 if (!c->lookup.dev_id && !c->lookup.con_id)
1105 c->lookup.con_id = c->name;
1106 c->lookup.clk = c;
1107 clkdev_add(&c->lookup);
1108}
1109
1110void __init tegra30_init_clocks(void)
1111{
1112 int i;
1113 struct clk *c;
1114
1115 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1116 tegra30_init_one_clock(tegra_ptr_clks[i]);
1117
1118 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1119 tegra30_init_one_clock(&tegra_list_clks[i]);
1120
1121 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1122 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1123 if (!c) {
1124 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1125 tegra_clk_duplicates[i].name);
1126 continue;
1127 }
1128
1129 tegra_clk_duplicates[i].lookup.clk = c;
1130 clkdev_add(&tegra_clk_duplicates[i].lookup);
1131 }
1132
1133 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1134 tegra30_init_one_clock(&tegra_sync_source_list[i]);
1135 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1136 tegra30_init_one_clock(&tegra_clk_audio_list[i]);
1137 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1138 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
1139
1140 init_clk_out_mux();
1141 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1142 tegra30_init_one_clock(&tegra_clk_out_list[i]);
1143
1144}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 21:31:10 -0500