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authorStephen Warren <swarren@nvidia.com>2012-10-23 13:40:25 -0400
committerStephen Warren <swarren@nvidia.com>2012-11-16 14:22:17 -0500
commit3a04931e3b6230926ebe200192545a8d952d787d (patch)
treedfd80f9f4d3219c49ee62f8bd2e5c3448aaa0930 /arch/arm/mach-tegra/timer.c
parent56415480e90a6ba31e9fdda2cc860c3fcaa80acc (diff)
ARM: tegra: enhance timer.c to get IO address from device tree
Modify Tegra's timer code to parse the IO address from device tree, hence removing the dependency on <mach/iomap.h>. This will allow the driver to be moved to drivers/clocksource/. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/timer.c')
-rw-r--r--arch/arm/mach-tegra/timer.c32
1 files changed, 28 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 026bad4ac57a..e4863f3e9ee7 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -26,6 +26,7 @@
26#include <linux/clocksource.h> 26#include <linux/clocksource.h>
27#include <linux/clk.h> 27#include <linux/clk.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/of_address.h>
29#include <linux/of_irq.h> 30#include <linux/of_irq.h>
30 31
31#include <asm/mach/time.h> 32#include <asm/mach/time.h>
@@ -33,8 +34,6 @@
33#include <asm/sched_clock.h> 34#include <asm/sched_clock.h>
34 35
35#include "board.h" 36#include "board.h"
36#include "clock.h"
37#include "iomap.h"
38 37
39#define RTC_SECONDS 0x08 38#define RTC_SECONDS 0x08
40#define RTC_SHADOW_SECONDS 0x0c 39#define RTC_SHADOW_SECONDS 0x0c
@@ -52,8 +51,8 @@
52#define TIMER_PTV 0x0 51#define TIMER_PTV 0x0
53#define TIMER_PCR 0x4 52#define TIMER_PCR 0x4
54 53
55static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); 54static void __iomem *timer_reg_base;
56static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE); 55static void __iomem *rtc_base;
57 56
58static struct timespec persistent_ts; 57static struct timespec persistent_ts;
59static u64 persistent_ms, last_persistent_ms; 58static u64 persistent_ms, last_persistent_ms;
@@ -164,6 +163,11 @@ static const struct of_device_id timer_match[] __initconst = {
164 {} 163 {}
165}; 164};
166 165
166static const struct of_device_id rtc_match[] __initconst = {
167 { .compatible = "nvidia,tegra20-rtc" },
168 {}
169};
170
167static void __init tegra_init_timer(void) 171static void __init tegra_init_timer(void)
168{ 172{
169 struct device_node *np; 173 struct device_node *np;
@@ -177,6 +181,12 @@ static void __init tegra_init_timer(void)
177 BUG(); 181 BUG();
178 } 182 }
179 183
184 timer_reg_base = of_iomap(np, 0);
185 if (!timer_reg_base) {
186 pr_err("Can't map timer registers");
187 BUG();
188 }
189
180 tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); 190 tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
181 if (tegra_timer_irq.irq <= 0) { 191 if (tegra_timer_irq.irq <= 0) {
182 pr_err("Failed to map timer IRQ\n"); 192 pr_err("Failed to map timer IRQ\n");
@@ -192,6 +202,20 @@ static void __init tegra_init_timer(void)
192 rate = clk_get_rate(clk); 202 rate = clk_get_rate(clk);
193 } 203 }
194 204
205 of_node_put(np);
206
207 np = of_find_matching_node(NULL, rtc_match);
208 if (!np) {
209 pr_err("Failed to find RTC DT node\n");
210 BUG();
211 }
212
213 rtc_base = of_iomap(np, 0);
214 if (!rtc_base) {
215 pr_err("Can't map RTC registers");
216 BUG();
217 }
218
195 /* 219 /*
196 * rtc registers are used by read_persistent_clock, keep the rtc clock 220 * rtc registers are used by read_persistent_clock, keep the rtc clock
197 * enabled 221 * enabled