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authorJoseph Lo <josephl@nvidia.com>2012-08-16 05:31:50 -0400
committerStephen Warren <swarren@nvidia.com>2012-09-13 13:41:06 -0400
commitc2be5bfcc986e688c0c9b427b9fb33be178437d8 (patch)
tree66d900ceb5b57fe3e8008e0d0480518b3046eb9c /arch/arm/mach-tegra/sleep.S
parentbb6032776d81d01cf6fecac7ccc27dd5abbffd7a (diff)
ARM: tegra: clean up the common assembly macros into sleep.h
There are some common macros for Tegra low-level assembly code. Clean up them into one header file and move the definitions that will be re-used into it as well. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
-rw-r--r--arch/arm/mach-tegra/sleep.S33
1 files changed, 1 insertions, 32 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156a8011..ea81554c4833 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
29#include <mach/iomap.h> 29#include <mach/iomap.h>
30 30
31#include "flowctrl.h" 31#include "flowctrl.h"
32#include "sleep.h"
32 33
33#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
34 + IO_PPSB_VIRT)
35
36/* returns the offset of the flow controller halt register for a cpu */
37.macro cpu_to_halt_reg rd, rcpu
38 cmp \rcpu, #0
39 subne \rd, \rcpu, #1
40 movne \rd, \rd, lsl #3
41 addne \rd, \rd, #0x14
42 moveq \rd, #0
43.endm
44
45/* returns the offset of the flow controller csr register for a cpu */
46.macro cpu_to_csr_reg rd, rcpu
47 cmp \rcpu, #0
48 subne \rd, \rcpu, #1
49 movne \rd, \rd, lsl #3
50 addne \rd, \rd, #0x18
51 moveq \rd, #8
52.endm
53
54/* returns the ID of the current processor */
55.macro cpu_id, rd
56 mrc p15, 0, \rd, c0, c0, 5
57 and \rd, \rd, #0xF
58.endm
59
60/* loads a 32-bit value into a register without a data access */
61.macro mov32, reg, val
62 movw \reg, #:lower16:\val
63 movt \reg, #:upper16:\val
64.endm