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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-12-04 11:01:03 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-14 14:21:40 -0500
commit384895330e0f3954d9478fd0853145f9c169df12 (patch)
treec90f70f4e070b640a1f1f2a76cf4acf864354093 /arch/arm/mach-tegra/platsmp.c
parentb580b899dd05a007ad232ee49a07b32d91876462 (diff)
ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-tegra/platsmp.c')
-rw-r--r--arch/arm/mach-tegra/platsmp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1c0fd92cab39..3b7376c4f356 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -48,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
48 * core (e.g. timer irq), then they will not have been enabled 48 * core (e.g. timer irq), then they will not have been enabled
49 * for us: do so 49 * for us: do so
50 */ 50 */
51 gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100); 51 gic_secondary_init(0);
52 52
53 /* 53 /*
54 * Synchronise with the boot thread. 54 * Synchronise with the boot thread.