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authorGary King <gking@nvidia.com>2010-04-05 23:30:59 -0400
committerColin Cross <ccross@android.com>2010-10-21 21:11:31 -0400
commit460907bc26f5565aced3cf35a10e3579c671ef50 (patch)
tree8e13848797444538c38e749d6539657319bcb0ce /arch/arm/mach-tegra/include
parent8726e4f50e3f445601c19a851c62586f5dc7dd49 (diff)
[ARM] tegra: add suspend and mirror irqs to legacy controller
mirror IRQ enable and disable operations on the legacy PPI system interrupt controller, since the legacy controller is responsible for responding to wakeup interrupts when the CPU is in LP2 idle mode save the irq controller state on suspend and restore on resume Signed-off-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/include')
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 20f640edaa0d..71bbf3422953 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,6 +25,7 @@
25 25
26#define IRQ_LOCALTIMER 29 26#define IRQ_LOCALTIMER 29
27 27
28#ifdef CONFIG_ARCH_TEGRA_2x_SOC
28/* Primary Interrupt Controller */ 29/* Primary Interrupt Controller */
29#define INT_PRI_BASE (INT_GIC_BASE + 32) 30#define INT_PRI_BASE (INT_GIC_BASE + 32)
30#define INT_TMR1 (INT_PRI_BASE + 0) 31#define INT_TMR1 (INT_PRI_BASE + 0)
@@ -169,5 +170,6 @@
169#define INT_GPIO_NR (28 * 8) 170#define INT_GPIO_NR (28 * 8)
170 171
171#define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) 172#define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
173#endif
172 174
173#endif 175#endif