ARM: tegra: add support for tegra30 interrupts

Tegra30 has 1 extra legacy interrupt controller. Use the GIC ITLinesNumber
field to determine how many interrupt controllers we have and initialize
appropriately. Also make room for the extra tegra30 interrupts by moving
the GPIO IRQ base. This shouldn't affect existing code as it determines the
correct IRQ number for GPIOs using TEGRA_GPIO_TO_IRQ().

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

2 files changed, 7 insertions, 3 deletions

diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 19dec3ac0854..67644c905d8e 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -74,6 +74,9 @@
 #define TEGRA_QUATERNARY_ICTLR_BASE     0x60004300
 #define TEGRA_QUATERNARY_ICTLR_SIZE     SZ_64
 
+#define TEGRA_QUINARY_ICTLR_BASE        0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE        SZ_64
+
 #define TEGRA_TMR1_BASE                 0x60005000
 #define TEGRA_TMR1_SIZE                 SZ_8
 
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index a2146cd6867d..aad1a2c1d714 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -165,11 +165,12 @@
 #define INT_QUAD_RES_30                 (INT_QUAD_BASE + 30)
 #define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
 
-#define INT_MAIN_NR                     (INT_QUAD_BASE + 32 - INT_PRI_BASE)
-
+/* Tegra30 has 5 banks of 32 IRQs */
+#define INT_MAIN_NR                     (32 * 5)
 #define INT_GPIO_BASE                   (INT_PRI_BASE + INT_MAIN_NR)
 
-#define INT_GPIO_NR                     (28 * 8)
+/* Tegra30 has 8 banks of 32 GPIOs */
+#define INT_GPIO_NR                     (32 * 8)
 
 #define TEGRA_NR_IRQS                   (INT_GPIO_BASE + INT_GPIO_NR)