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authorArnd Bergmann <arnd@arndb.de>2012-03-04 15:55:46 -0500
committerArnd Bergmann <arnd@arndb.de>2012-03-04 15:57:06 -0500
commitc71656c018c8551eca45b2f873b239f0303d74cb (patch)
treebab4825a6ed993c98ac4967f2aa976536f58568a /arch/arm/mach-tegra/include/mach
parentcb66bb1d6fab2d91960c20f256c6986d5afac1a1 (diff)
parente186ad74c0941f5caeda28bde76dab903b342c1c (diff)
Merge tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/soc
From: Olof Johansson <olof@lixom.net> SoC new development for tegra SoCs, mostly tegra30 core support. It also includes one stray bugfix that was misapplied (should have been in soc-drivers), but it went out to the stable branches before I noticed so I've left it in. * tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra: ARM: tegra: Demote EMC clock inconsistency BUG to WARN ARM: tegra: Avoid compiling cpuidle code when not configured ARM: tegra: cpuidle driver for tegra ARM: tegra: assembler code for LP3 ARM: tegra: definitions for flow controller ARM: tegra: initialize basic system clocks ARM: tegra: enable tegra30 clock framework ARM: tegra: implement basic tegra30 clock framework ARM: tegra: add support for new clock framework features ARM: tegra: add support for tegra30 interrupts Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach')
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h10
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h3
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h7
3 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index fc3ecb66de08..d97e403303a0 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -22,10 +22,20 @@
22 22
23struct clk; 23struct clk;
24 24
25enum tegra_clk_ex_param {
26 TEGRA_CLK_VI_INP_SEL,
27 TEGRA_CLK_DTV_INVERT,
28 TEGRA_CLK_NAND_PAD_DIV2_ENB,
29 TEGRA_CLK_PLLD_CSI_OUT_ENB,
30 TEGRA_CLK_PLLD_DSI_OUT_ENB,
31 TEGRA_CLK_PLLD_MIPI_MUX_SEL,
32};
33
25void tegra_periph_reset_deassert(struct clk *c); 34void tegra_periph_reset_deassert(struct clk *c);
26void tegra_periph_reset_assert(struct clk *c); 35void tegra_periph_reset_assert(struct clk *c);
27 36
28unsigned long clk_get_rate_all_locked(struct clk *c); 37unsigned long clk_get_rate_all_locked(struct clk *c);
29void tegra2_sdmmc_tap_delay(struct clk *c, int delay); 38void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
39int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
30 40
31#endif 41#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 19dec3ac0854..67644c905d8e 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -74,6 +74,9 @@
74#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 74#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
75#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 75#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
76 76
77#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
78#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
79
77#define TEGRA_TMR1_BASE 0x60005000 80#define TEGRA_TMR1_BASE 0x60005000
78#define TEGRA_TMR1_SIZE SZ_8 81#define TEGRA_TMR1_SIZE SZ_8
79 82
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index a2146cd6867d..aad1a2c1d714 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -165,11 +165,12 @@
165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) 165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) 166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
167 167
168#define INT_MAIN_NR (INT_QUAD_BASE + 32 - INT_PRI_BASE) 168/* Tegra30 has 5 banks of 32 IRQs */
169 169#define INT_MAIN_NR (32 * 5)
170#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR) 170#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
171 171
172#define INT_GPIO_NR (28 * 8) 172/* Tegra30 has 8 banks of 32 GPIOs */
173#define INT_GPIO_NR (32 * 8)
173 174
174#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) 175#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
175 176