diff options
author | Colin Cross <ccross@android.com> | 2010-10-04 00:24:28 -0400 |
---|---|---|
committer | Colin Cross <ccross@android.com> | 2011-02-10 00:57:01 -0500 |
commit | 538bd3cc196f55b02614b3b19c48656251464b74 (patch) | |
tree | 7023c7ca748e7f3017e46374c30783085375b997 /arch/arm/mach-tegra/include/mach | |
parent | ce1e32626951957729d5a1bbe3fa7e5d734df6c0 (diff) |
ARM: tegra: irqs: Update irq list
Fixes typo in INT_CPU1_PMU_INTR (original fix from Will Deacon)
Adds board irqs
Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach')
-rw-r--r-- | arch/arm/mach-tegra/include/mach/irqs.h | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h index 71bbf3422953..73265af4dda3 100644 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ b/arch/arm/mach-tegra/include/mach/irqs.h | |||
@@ -88,7 +88,7 @@ | |||
88 | #define INT_SYS_STATS_MON (INT_SEC_BASE + 22) | 88 | #define INT_SYS_STATS_MON (INT_SEC_BASE + 22) |
89 | #define INT_GPIO5 (INT_SEC_BASE + 23) | 89 | #define INT_GPIO5 (INT_SEC_BASE + 23) |
90 | #define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) | 90 | #define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) |
91 | #define INT_CPU2_PMU_INTR (INT_SEC_BASE + 25) | 91 | #define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25) |
92 | #define INT_SEC_RES_26 (INT_SEC_BASE + 26) | 92 | #define INT_SEC_RES_26 (INT_SEC_BASE + 26) |
93 | #define INT_S_LINK1 (INT_SEC_BASE + 27) | 93 | #define INT_S_LINK1 (INT_SEC_BASE + 27) |
94 | #define INT_APB_DMA_COP (INT_SEC_BASE + 28) | 94 | #define INT_APB_DMA_COP (INT_SEC_BASE + 28) |
@@ -166,10 +166,18 @@ | |||
166 | #define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) | 166 | #define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) |
167 | #define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) | 167 | #define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) |
168 | 168 | ||
169 | #define INT_GPIO_BASE (INT_QUAD_BASE + 32) | 169 | #define INT_MAIN_NR (INT_QUAD_BASE + 32 - INT_PRI_BASE) |
170 | |||
171 | #define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR) | ||
172 | |||
170 | #define INT_GPIO_NR (28 * 8) | 173 | #define INT_GPIO_NR (28 * 8) |
171 | 174 | ||
172 | #define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) | 175 | #define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) |
176 | |||
177 | #define INT_BOARD_BASE TEGRA_NR_IRQS | ||
178 | #define NR_BOARD_IRQS 32 | ||
179 | |||
180 | #define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) | ||
173 | #endif | 181 | #endif |
174 | 182 | ||
175 | #endif | 183 | #endif |