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authorColin Cross <ccross@android.com>2010-07-28 00:34:38 -0400
committerColin Cross <ccross@android.com>2010-10-21 21:11:24 -0400
commitc231d6976a161ae7b5b3aba4a1821b2e9c00c02c (patch)
tree4c831bd313e1c29144afe3b5d2d5f9fd653348b9 /arch/arm/mach-tegra/include/mach/iomap.h
parentb5153163ed580e00c67bdfecb02b2e3843817b3e (diff)
[ARM] tegra: update iomap
Add missing io address map entries from datasheet. Add the IRAM area to the statically mapped io regions. Correct the onewire, USB, and statmon addresses Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/iomap.h')
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h33
1 files changed, 27 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 1741f7dd7a9b..44a4f4bcf91f 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -23,9 +23,15 @@
23 23
24#include <asm/sizes.h> 24#include <asm/sizes.h>
25 25
26#define TEGRA_IRAM_BASE 0x40000000
27#define TEGRA_IRAM_SIZE SZ_256K
28
26#define TEGRA_ARM_PERIF_BASE 0x50040000 29#define TEGRA_ARM_PERIF_BASE 0x50040000
27#define TEGRA_ARM_PERIF_SIZE SZ_8K 30#define TEGRA_ARM_PERIF_SIZE SZ_8K
28 31
32#define TEGRA_ARM_PL310_BASE 0x50043000
33#define TEGRA_ARM_PL310_SIZE SZ_4K
34
29#define TEGRA_ARM_INT_DIST_BASE 0x50041000 35#define TEGRA_ARM_INT_DIST_BASE 0x50041000
30#define TEGRA_ARM_INT_DIST_SIZE SZ_4K 36#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
31 37
@@ -68,7 +74,22 @@
68#define TEGRA_FLOW_CTRL_BASE 0x60007000 74#define TEGRA_FLOW_CTRL_BASE 0x60007000
69#define TEGRA_FLOW_CTRL_SIZE 20 75#define TEGRA_FLOW_CTRL_SIZE 20
70 76
71#define TEGRA_STATMON_BASE 0x6000C4000 77#define TEGRA_AHB_DMA_BASE 0x60008000
78#define TEGRA_AHB_DMA_SIZE SZ_4K
79
80#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
81#define TEGRA_AHB_DMA_CH0_SIZE 32
82
83#define TEGRA_APB_DMA_BASE 0x6000A000
84#define TEGRA_APB_DMA_SIZE SZ_4K
85
86#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
87#define TEGRA_APB_DMA_CH0_SIZE 32
88
89#define TEGRA_AHB_GIZMO_BASE 0x6000C004
90#define TEGRA_AHB_GIZMO_SIZE 0x10C
91
92#define TEGRA_STATMON_BASE 0x6000C400
72#define TEGRA_STATMON_SIZE SZ_1K 93#define TEGRA_STATMON_SIZE SZ_1K
73 94
74#define TEGRA_GPIO_BASE 0x6000D000 95#define TEGRA_GPIO_BASE 0x6000D000
@@ -137,7 +158,7 @@
137#define TEGRA_I2C3_BASE 0x7000C500 158#define TEGRA_I2C3_BASE 0x7000C500
138#define TEGRA_I2C3_SIZE SZ_256 159#define TEGRA_I2C3_SIZE SZ_256
139 160
140#define TEGRA_OWR_BASE 0x7000D000 161#define TEGRA_OWR_BASE 0x7000C600
141#define TEGRA_OWR_SIZE 80 162#define TEGRA_OWR_SIZE 80
142 163
143#define TEGRA_DVC_BASE 0x7000D000 164#define TEGRA_DVC_BASE 0x7000D000
@@ -182,12 +203,12 @@
182#define TEGRA_USB_BASE 0xC5000000 203#define TEGRA_USB_BASE 0xC5000000
183#define TEGRA_USB_SIZE SZ_16K 204#define TEGRA_USB_SIZE SZ_16K
184 205
185#define TEGRA_USB1_BASE 0xC5004000 206#define TEGRA_USB2_BASE 0xC5004000
186#define TEGRA_USB1_SIZE SZ_16K
187
188#define TEGRA_USB2_BASE 0xC5008000
189#define TEGRA_USB2_SIZE SZ_16K 207#define TEGRA_USB2_SIZE SZ_16K
190 208
209#define TEGRA_USB3_BASE 0xC5008000
210#define TEGRA_USB3_SIZE SZ_16K
211
191#define TEGRA_SDMMC1_BASE 0xC8000000 212#define TEGRA_SDMMC1_BASE 0xC8000000
192#define TEGRA_SDMMC1_SIZE SZ_512 213#define TEGRA_SDMMC1_SIZE SZ_512
193 214