diff options
author | Danny Huang <dahuang@nvidia.com> | 2012-11-15 02:42:32 -0500 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2012-11-15 16:16:46 -0500 |
commit | 1f851a262baf7cbd4096d4d279c73cb697021773 (patch) | |
tree | 02374f20236ff7a38b27c716d6bbafd104a9199c /arch/arm/mach-tegra/fuse.c | |
parent | fd072a86bde1c5f7cf04618903c5ce8658011c1c (diff) |
ARM: tegra: flexible spare fuse read function
Change the spare fuse base from a definition to a variable.
It provides flexibilty to read spare fuse on different chip.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/fuse.c')
-rw-r--r-- | arch/arm/mach-tegra/fuse.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 6c752e8f1f06..bd19c2f53a97 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c | |||
@@ -28,7 +28,8 @@ | |||
28 | #define FUSE_UID_LOW 0x108 | 28 | #define FUSE_UID_LOW 0x108 |
29 | #define FUSE_UID_HIGH 0x10c | 29 | #define FUSE_UID_HIGH 0x10c |
30 | #define FUSE_SKU_INFO 0x110 | 30 | #define FUSE_SKU_INFO 0x110 |
31 | #define FUSE_SPARE_BIT 0x200 | 31 | |
32 | #define TEGRA20_FUSE_SPARE_BIT 0x200 | ||
32 | 33 | ||
33 | int tegra_sku_id; | 34 | int tegra_sku_id; |
34 | int tegra_cpu_process_id; | 35 | int tegra_cpu_process_id; |
@@ -36,6 +37,8 @@ int tegra_core_process_id; | |||
36 | int tegra_chip_id; | 37 | int tegra_chip_id; |
37 | enum tegra_revision tegra_revision; | 38 | enum tegra_revision tegra_revision; |
38 | 39 | ||
40 | static int tegra_fuse_spare_bit; | ||
41 | |||
39 | /* The BCT to use at boot is specified by board straps that can be read | 42 | /* The BCT to use at boot is specified by board straps that can be read |
40 | * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. | 43 | * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. |
41 | */ | 44 | */ |
@@ -56,14 +59,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { | |||
56 | [TEGRA_REVISION_A04] = "A04", | 59 | [TEGRA_REVISION_A04] = "A04", |
57 | }; | 60 | }; |
58 | 61 | ||
59 | static inline u32 tegra_fuse_readl(unsigned long offset) | 62 | u32 tegra_fuse_readl(unsigned long offset) |
60 | { | 63 | { |
61 | return tegra_apb_readl(TEGRA_FUSE_BASE + offset); | 64 | return tegra_apb_readl(TEGRA_FUSE_BASE + offset); |
62 | } | 65 | } |
63 | 66 | ||
64 | static inline bool get_spare_fuse(int bit) | 67 | bool tegra_spare_fuse(int bit) |
65 | { | 68 | { |
66 | return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); | 69 | return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); |
67 | } | 70 | } |
68 | 71 | ||
69 | static enum tegra_revision tegra_get_revision(u32 id) | 72 | static enum tegra_revision tegra_get_revision(u32 id) |
@@ -77,7 +80,7 @@ static enum tegra_revision tegra_get_revision(u32 id) | |||
77 | return TEGRA_REVISION_A02; | 80 | return TEGRA_REVISION_A02; |
78 | case 3: | 81 | case 3: |
79 | if (tegra_chip_id == TEGRA20 && | 82 | if (tegra_chip_id == TEGRA20 && |
80 | (get_spare_fuse(18) || get_spare_fuse(19))) | 83 | (tegra_spare_fuse(18) || tegra_spare_fuse(19))) |
81 | return TEGRA_REVISION_A03p; | 84 | return TEGRA_REVISION_A03p; |
82 | else | 85 | else |
83 | return TEGRA_REVISION_A03; | 86 | return TEGRA_REVISION_A03; |
@@ -99,10 +102,12 @@ void tegra_init_fuse(void) | |||
99 | reg = tegra_fuse_readl(FUSE_SKU_INFO); | 102 | reg = tegra_fuse_readl(FUSE_SKU_INFO); |
100 | tegra_sku_id = reg & 0xFF; | 103 | tegra_sku_id = reg & 0xFF; |
101 | 104 | ||
102 | reg = tegra_fuse_readl(FUSE_SPARE_BIT); | 105 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; |
106 | |||
107 | reg = tegra_fuse_readl(tegra_fuse_spare_bit); | ||
103 | tegra_cpu_process_id = (reg >> 6) & 3; | 108 | tegra_cpu_process_id = (reg >> 6) & 3; |
104 | 109 | ||
105 | reg = tegra_fuse_readl(FUSE_SPARE_BIT); | 110 | reg = tegra_fuse_readl(tegra_fuse_spare_bit); |
106 | tegra_core_process_id = (reg >> 12) & 3; | 111 | tegra_core_process_id = (reg >> 12) & 3; |
107 | 112 | ||
108 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); | 113 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); |