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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-06 16:30:06 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-06 16:30:06 -0400 |
commit | b4b50fd78b1e31989940dfc647e64453d0f7176a (patch) | |
tree | 1a55f110e021c02963b63759f3f18ea7ba3aa228 /arch/arm/mach-tegra/flowctrl.h | |
parent | dccfd1e439c11422d7aca0d834b0430d24650e85 (diff) | |
parent | f97c43bbdf8a1ea42477b1a804a48e7e368cb13c (diff) |
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This branch contains mostly additions and changes to platform
enablement and SoC-level drivers. Since there's sometimes a
dependency on device-tree changes, there's also a fair amount of
those in this branch.
Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad
Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.
The code that touches other architectures are patches moving MSI
arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
ARM: dts: vf610-twr: enable i2c0 device
ARM: dts: i.MX51: Add one more I2C2 pinmux entry
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
ARM: dts: i.MX27: Disable AUDMUX in the template
ARM: dts: wandboard: Add support for SDIO bcm4329
ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
ARM: dts: imx53-qsb: Make USBH1 functional
ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
ARM: dts: imx6qdl-sabresd: Add touchscreen support
ARM: imx: add ocram clock for imx53
ARM: dts: imx: ocram size is different between imx6q and imx6dl
ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
ARM: dts: i.MX27: Remove clock name from CPU node
...
Diffstat (limited to 'arch/arm/mach-tegra/flowctrl.h')
-rw-r--r-- | arch/arm/mach-tegra/flowctrl.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 7a29bae799a7..c89aac60a143 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h | |||
@@ -28,9 +28,18 @@ | |||
28 | #define FLOW_CTRL_SCLK_RESUME (1 << 27) | 28 | #define FLOW_CTRL_SCLK_RESUME (1 << 27) |
29 | #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) | 29 | #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) |
30 | #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) | 30 | #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) |
31 | #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) | ||
32 | #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) | ||
33 | #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) | ||
34 | #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) | ||
31 | #define FLOW_CTRL_CPU0_CSR 0x8 | 35 | #define FLOW_CTRL_CPU0_CSR 0x8 |
32 | #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) | 36 | #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) |
33 | #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) | 37 | #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) |
38 | #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) | ||
39 | #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) | ||
40 | #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ | ||
41 | FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ | ||
42 | FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) | ||
34 | #define FLOW_CTRL_CSR_ENABLE (1 << 0) | 43 | #define FLOW_CTRL_CSR_ENABLE (1 << 0) |
35 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 | 44 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 |
36 | #define FLOW_CTRL_CPU1_CSR 0x18 | 45 | #define FLOW_CTRL_CPU1_CSR 0x18 |