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authorStephen Warren <swarren@nvidia.com>2012-04-12 16:09:39 -0400
committerStephen Warren <swarren@nvidia.com>2012-04-25 17:22:09 -0400
commit60f975b98cf41476ba0e156f7523b197b046cf2b (patch)
tree1af645f32f8aa377307e18876b4296586c18df95 /arch/arm/mach-tegra/common.c
parentc8b62ab41f76218efca5e4baa5c22ef52a9fe3a5 (diff)
ARM: tegra: reparent sclk to pll_c_out1
pll_p_out4 needs to be used for other purposes. Reparent sclk so that it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this is the lowest precise rate that can be achieved by dividing the pll_c rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909..., 600/6=100). Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r--arch/arm/mach-tegra/common.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 22df10fb9972..e96900418682 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
83 { "pll_p_out2", "pll_p", 48000000, true }, 83 { "pll_p_out2", "pll_p", 48000000, true },
84 { "pll_p_out3", "pll_p", 72000000, true }, 84 { "pll_p_out3", "pll_p", 72000000, true },
85 { "pll_p_out4", "pll_p", 108000000, true }, 85 { "pll_p_out4", "pll_p", 108000000, true },
86 { "sclk", "pll_p_out4", 108000000, true }, 86 { "pll_c", "clk_m", 600000000, true },
87 { "hclk", "sclk", 108000000, true }, 87 { "pll_c_out1", "pll_c", 120000000, true },
88 { "sclk", "pll_c_out1", 120000000, true },
89 { "hclk", "sclk", 120000000, true },
88 { "pclk", "hclk", 54000000, true }, 90 { "pclk", "hclk", 54000000, true },
89 { "csite", NULL, 0, true }, 91 { "csite", NULL, 0, true },
90 { "emc", NULL, 0, true }, 92 { "emc", NULL, 0, true },