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authorPeter De Schrijver <pdeschrijver@nvidia.com>2012-01-09 00:35:11 -0500
committerOlof Johansson <olof@lixom.net>2012-02-06 12:16:15 -0500
commit4fccf75ba3bee0bb3be7828caa03625d4ac100a2 (patch)
treeac2445c017187a1f68fbf642c1712706c0903c0b /arch/arm/mach-tegra/clock.h
parentcaa4868ee07029e60450909960652b96a50ebfbd (diff)
ARM: tegra: add support for new clock framework features
Add support for new clock framework features implemented in tegra30. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
-rw-r--r--arch/arm/mach-tegra/clock.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 5c44106616c5..18f8b857361d 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -24,6 +24,8 @@
24#include <linux/list.h> 24#include <linux/list.h>
25#include <linux/spinlock.h> 25#include <linux/spinlock.h>
26 26
27#include <mach/clk.h>
28
27#define DIV_BUS (1 << 0) 29#define DIV_BUS (1 << 0)
28#define DIV_U71 (1 << 1) 30#define DIV_U71 (1 << 1)
29#define DIV_U71_FIXED (1 << 2) 31#define DIV_U71_FIXED (1 << 2)
@@ -39,7 +41,16 @@
39#define PERIPH_MANUAL_RESET (1 << 12) 41#define PERIPH_MANUAL_RESET (1 << 12)
40#define PLL_ALT_MISC_REG (1 << 13) 42#define PLL_ALT_MISC_REG (1 << 13)
41#define PLLU (1 << 14) 43#define PLLU (1 << 14)
44#define PLLX (1 << 15)
45#define MUX_PWM (1 << 16)
46#define MUX8 (1 << 17)
47#define DIV_U71_UART (1 << 18)
48#define MUX_CLK_OUT (1 << 19)
49#define PLLM (1 << 20)
50#define DIV_U71_INT (1 << 21)
51#define DIV_U71_IDLE (1 << 22)
42#define ENABLE_ON_INIT (1 << 28) 52#define ENABLE_ON_INIT (1 << 28)
53#define PERIPH_ON_APB (1 << 29)
43 54
44struct clk; 55struct clk;
45 56
@@ -65,6 +76,8 @@ struct clk_ops {
65 int (*set_rate)(struct clk *, unsigned long); 76 int (*set_rate)(struct clk *, unsigned long);
66 long (*round_rate)(struct clk *, unsigned long); 77 long (*round_rate)(struct clk *, unsigned long);
67 void (*reset)(struct clk *, bool); 78 void (*reset)(struct clk *, bool);
79 int (*clk_cfg_ex)(struct clk *,
80 enum tegra_clk_ex_param, u32);
68}; 81};
69 82
70enum clk_state { 83enum clk_state {
@@ -114,6 +127,7 @@ struct clk {
114 unsigned long vco_max; 127 unsigned long vco_max;
115 const struct clk_pll_freq_table *freq_table; 128 const struct clk_pll_freq_table *freq_table;
116 int lock_delay; 129 int lock_delay;
130 unsigned long fixed_rate;
117 } pll; 131 } pll;
118 struct { 132 struct {
119 u32 sel; 133 u32 sel;