Merge branch 'for-next' of git://android.git.kernel.org/kernel/tegra

* 'for-next' of git://android.git.kernel.org/kernel/tegra:
  spi: tegra: fix error setting on timeout
  spi: add spi_tegra driver
  tegra: harmony: enable PCI Express
  tegra: add PCI Express support
  tegra: add PCI Express clocks
  [ARM] tegra: Add APB DMA support
  [ARM] tegra: Add cpufreq support
  [ARM] tegra: common: Update common clock init table
  [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups
  [ARM] tegra: Add support for reading fuses
  [ARM] tegra: gpio: Add suspend and wake support
  [ARM] tegra: pinmux: add safe values, move tegra2, add suspend
  [ARM] tegra: add suspend and mirror irqs to legacy controller
  [ARM] tegra: Add legacy irq support
  [ARM] tegra: update iomap

1 files changed, 42 insertions, 16 deletions

diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index af7c70e2a3ba..94fd859770f1 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -27,18 +27,43 @@
 #define DIV_U71                 (1 << 1)
 #define DIV_U71_FIXED           (1 << 2)
 #define DIV_2                   (1 << 3)
-#define PLL_FIXED               (1 << 4)
-#define PLL_HAS_CPCON           (1 << 5)
-#define MUX                     (1 << 6)
-#define PLLD                    (1 << 7)
-#define PERIPH_NO_RESET         (1 << 8)
-#define PERIPH_NO_ENB           (1 << 9)
-#define PERIPH_EMC_ENB          (1 << 10)
-#define PERIPH_MANUAL_RESET     (1 << 11)
-#define PLL_ALT_MISC_REG        (1 << 12)
+#define DIV_U16                 (1 << 4)
+#define PLL_FIXED               (1 << 5)
+#define PLL_HAS_CPCON           (1 << 6)
+#define MUX                     (1 << 7)
+#define PLLD                    (1 << 8)
+#define PERIPH_NO_RESET         (1 << 9)
+#define PERIPH_NO_ENB           (1 << 10)
+#define PERIPH_EMC_ENB          (1 << 11)
+#define PERIPH_MANUAL_RESET     (1 << 12)
+#define PLL_ALT_MISC_REG        (1 << 13)
+#define PLLU                    (1 << 14)
 #define ENABLE_ON_INIT          (1 << 28)
 
 struct clk;
+struct regulator;
+
+struct dvfs_table {
+        unsigned long rate;
+        int millivolts;
+};
+
+struct dvfs_process_id_table {
+        int process_id;
+        struct dvfs_table *table;
+};
+
+
+struct dvfs {
+        struct regulator *reg;
+        struct dvfs_table *table;
+        int max_millivolts;
+
+        int process_id_table_length;
+        const char *reg_id;
+        bool cpu;
+        struct dvfs_process_id_table process_id_table[];
+};
 
 struct clk_mux_sel {
         struct clk      *input;
@@ -58,12 +83,9 @@ struct clk_ops {
         void            (*init)(struct clk *);
         int             (*enable)(struct clk *);
         void            (*disable)(struct clk *);
-        void            (*recalc)(struct clk *);
         int             (*set_parent)(struct clk *, struct clk *);
         int             (*set_rate)(struct clk *, unsigned long);
-        unsigned long   (*get_rate)(struct clk *);
         long            (*round_rate)(struct clk *, unsigned long);
-        unsigned long   (*recalculate_rate)(struct clk *);
 };
 
 enum clk_state {
@@ -85,6 +107,7 @@ struct clk {
         struct clk                      *parent;
         struct clk_lookup               lookup;
         unsigned long                   rate;
+        unsigned long                   max_rate;
         u32                             flags;
         u32                             refcnt;
         const char                      *name;
@@ -103,10 +126,6 @@ struct clk {
         unsigned long                   cf_max;
         unsigned long                   vco_min;
         unsigned long                   vco_max;
-        u32                             m;
-        u32                             n;
-        u32                             p;
-        u32                             cpcon;
         const struct clk_pll_table      *pll_table;
 
         /* DIV */
@@ -117,6 +136,12 @@ struct clk {
         const struct clk_mux_sel        *inputs;
         u32                             sel;
         u32                             reg_mask;
+
+        /* Virtual cpu clock */
+        struct clk                      *main;
+        struct clk                      *backup;
+
+        struct dvfs                     *dvfs;
 };
 
 
@@ -141,6 +166,7 @@ unsigned long clk_measure_input_freq(void);
 void clk_disable_locked(struct clk *c);
 int clk_enable_locked(struct clk *c);
 int clk_set_parent_locked(struct clk *c, struct clk *parent);
+int clk_set_rate_locked(struct clk *c, unsigned long rate);
 int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);