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author | Grant Likely <grant.likely@secretlab.ca> | 2012-02-27 16:04:40 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2012-02-27 16:04:40 -0500 |
commit | 29f141fed01a09050207c4d41fc5811520d81146 (patch) | |
tree | c55a51dca4a0e4da9fdc2b904eefbde37d2a5b03 /arch/arm/mach-tegra/board-paz00.c | |
parent | 2261cc627f5453004042b4f694612edae27e492e (diff) | |
parent | 14cd3c15cfc8118586262a79bfa3b3123f13e2c2 (diff) |
Merge branch 'fixes-for-grant' of git://sources.calxeda.com/kernel/linux into devicetree/merge
Diffstat (limited to 'arch/arm/mach-tegra/board-paz00.c')
-rw-r--r-- | arch/arm/mach-tegra/board-paz00.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index fcf4f377b1dc..330afdfa2475 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c | |||
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { | |||
60 | .uartclk = 216000000, | 60 | .uartclk = 216000000, |
61 | }, { | 61 | }, { |
62 | /* serial port on mini-pcie */ | 62 | /* serial port on mini-pcie */ |
63 | .membase = IO_ADDRESS(TEGRA_UARTD_BASE), | 63 | .membase = IO_ADDRESS(TEGRA_UARTC_BASE), |
64 | .mapbase = TEGRA_UARTD_BASE, | 64 | .mapbase = TEGRA_UARTC_BASE, |
65 | .irq = INT_UARTD, | 65 | .irq = INT_UARTC, |
66 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, | 66 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, |
67 | .type = PORT_TEGRA, | 67 | .type = PORT_TEGRA, |
68 | .iotype = UPIO_MEM, | 68 | .iotype = UPIO_MEM, |
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, | |||
174 | static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { | 174 | static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { |
175 | /* name parent rate enabled */ | 175 | /* name parent rate enabled */ |
176 | { "uarta", "pll_p", 216000000, true }, | 176 | { "uarta", "pll_p", 216000000, true }, |
177 | { "uartd", "pll_p", 216000000, true }, | 177 | { "uartc", "pll_p", 216000000, true }, |
178 | 178 | ||
179 | { "pll_p_out4", "pll_p", 24000000, true }, | 179 | { "pll_p_out4", "pll_p", 24000000, true }, |
180 | { "usbd", "clk_m", 12000000, false }, | 180 | { "usbd", "clk_m", 12000000, false }, |