diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-27 19:03:32 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-27 19:03:32 -0400 |
commit | d61b7a572b292e2be409e13b4b3adf475f18fb29 (patch) | |
tree | e9d30390860147136c05e66abf1edda1bc5b0562 /arch/arm/mach-tegra/Kconfig | |
parent | 18d9946bc7e2252fe3c0f2f609ac383c627edefd (diff) | |
parent | f4e2467bad53023589cbff18dd1ab6e0aa3f004c (diff) |
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: global cleanups" from Arnd Bergmann:
"Quite a bit of code gets removed, and some stuff moved around, mostly
the old samsung s3c24xx stuff. There should be no functional changes
in this series otherwise. Some cleanups have dependencies on other
arm-soc branches and will be sent in the second round.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>"
Fixed up trivial conflicts mainly due to #include's being changes on
both sides.
* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (121 commits)
ep93xx: Remove unnecessary includes of ep93xx-regs.h
ep93xx: Move EP93XX_SYSCON defines to SoC private header
ep93xx: Move crunch code to mach-ep93xx directory
ep93xx: Make syscon access functions private to SoC
ep93xx: Configure GPIO ports in core code
ep93xx: Move peripheral defines to local SoC header
ep93xx: Convert the watchdog driver into a platform device.
ep93xx: Use ioremap for backlight driver
ep93xx: Move GPIO defines to gpio-ep93xx.h
ep93xx: Don't use system controller defines in audio drivers
ep93xx: Move PHYS_BASE defines to local SoC header file
ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver
ARM: EXYNOS: add clock registers for exynos4x12-cpufreq
PM / devfreq: update the name of EXYNOS clock registers that were omitted
PM / devfreq: update the name of EXYNOS clock register
ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
ARM: EXYNOS: use static declaration on regarding clock
ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
ARM: OMAP2+: Fix build error after merge
ARM: S3C24XX: remove call to s3c24xx_setup_clocks
...
Diffstat (limited to 'arch/arm/mach-tegra/Kconfig')
-rw-r--r-- | arch/arm/mach-tegra/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 32b420a90c3d..16511199bad6 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
@@ -12,6 +12,14 @@ config ARCH_TEGRA_2x_SOC | |||
12 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 12 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
13 | select USB_ULPI if USB_SUPPORT | 13 | select USB_ULPI if USB_SUPPORT |
14 | select USB_ULPI_VIEWPORT if USB_SUPPORT | 14 | select USB_ULPI_VIEWPORT if USB_SUPPORT |
15 | select ARM_ERRATA_720789 | ||
16 | select ARM_ERRATA_742230 | ||
17 | select ARM_ERRATA_751472 | ||
18 | select ARM_ERRATA_754327 | ||
19 | select ARM_ERRATA_764369 | ||
20 | select PL310_ERRATA_727915 if CACHE_L2X0 | ||
21 | select PL310_ERRATA_769419 if CACHE_L2X0 | ||
22 | select CPU_FREQ_TABLE if CPU_FREQ | ||
15 | help | 23 | help |
16 | Support for NVIDIA Tegra AP20 and T20 processors, based on the | 24 | Support for NVIDIA Tegra AP20 and T20 processors, based on the |
17 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | 25 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
@@ -27,6 +35,12 @@ config ARCH_TEGRA_3x_SOC | |||
27 | select USB_ULPI if USB_SUPPORT | 35 | select USB_ULPI if USB_SUPPORT |
28 | select USB_ULPI_VIEWPORT if USB_SUPPORT | 36 | select USB_ULPI_VIEWPORT if USB_SUPPORT |
29 | select USE_OF | 37 | select USE_OF |
38 | select ARM_ERRATA_743622 | ||
39 | select ARM_ERRATA_751472 | ||
40 | select ARM_ERRATA_754322 | ||
41 | select ARM_ERRATA_764369 | ||
42 | select PL310_ERRATA_769419 if CACHE_L2X0 | ||
43 | select CPU_FREQ_TABLE if CPU_FREQ | ||
30 | help | 44 | help |
31 | Support for NVIDIA Tegra T30 processor family, based on the | 45 | Support for NVIDIA Tegra T30 processor family, based on the |
32 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | 46 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |