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authorOskar Schirmer <oskar@linutronix.de>2011-02-17 10:42:58 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-03-11 04:06:05 -0500
commit85922e54a3a14a6aee6c0b1fc67d81ef0c60fc9c (patch)
tree7ad5d37246e948424769c0456cd7d09f95f0192e /arch/arm/mach-tcc8k
parent30d913556b25db11f2537f4412487c6e81dc0374 (diff)
arm: tcc8k: Choose PLL settings conforming to board layout
The evaluation board is driven with 1.2V core voltage, so system clock must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose appropriate values and set DTCMWAIT accordingly. Adapt UART setting to avoid console log interruption and wait for the specified locking time of 300us to pass. Signed-off-by: Oskar Schirmer <oskar@linutronix.de> Cc: bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mach-tcc8k')
-rw-r--r--arch/arm/mach-tcc8k/board-tcc8000-sdk.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
index a3b66d405eb3..c25cf3f84566 100644
--- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -6,6 +6,7 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <linux/delay.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/kernel.h> 11#include <linux/kernel.h>
11#include <linux/platform_device.h> 12#include <linux/platform_device.h>
@@ -18,6 +19,7 @@
18 19
19#include <mach/clock.h> 20#include <mach/clock.h>
20#include <mach/tcc-nand.h> 21#include <mach/tcc-nand.h>
22#include <mach/tcc8k-regs.h>
21 23
22#include "common.h" 24#include "common.h"
23 25
@@ -52,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
52static void __init tcc8k_map_io(void) 54static void __init tcc8k_map_io(void)
53{ 55{
54 tcc8k_map_common_io(); 56 tcc8k_map_common_io();
57
58 /* set PLL0 clock to 96MHz, adapt UART0 divisor */
59 __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
60 __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
61
62 /* set PLL1 clock to 192MHz */
63 __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
64
65 /* set PLL2 clock to 48MHz */
66 __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
67
68 /* with CPU freq higher than 150 MHz, need extra DTCM wait */
69 __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
70
71 /* PLL locking time as specified */
72 udelay(300);
55} 73}
56 74
57MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") 75MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")