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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-05-06 22:44:21 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-05-23 04:37:44 -0400
commit553600502b84c79e7a7a13188350b0be4bdd2485 (patch)
tree6fdfa34fb053428c16c44c300122513cce78d2ac /arch/arm/mach-sunxi/sunxi.c
parent27a3cf055fcfe2dff9c59f424e9342f1a2d09023 (diff)
ARM: sunxi: Remove reset code from the platform
Now that reset is handled either by the watchdog driver for the sun4i, sun5i and sun7i, and by a driver of its own for sun6i, we can remove it from the platform code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-sunxi/sunxi.c')
-rw-r--r--arch/arm/mach-sunxi/sunxi.c98
1 files changed, 0 insertions, 98 deletions
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index df906e3a8f91..0c236c0be358 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,107 +12,12 @@
12 12
13#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
14#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h> 15#include <linux/of_platform.h>
21#include <linux/io.h>
22#include <linux/reboot.h>
23 16
24#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/system_misc.h>
27
28#define SUN4I_WATCHDOG_CTRL_REG 0x00
29#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
30#define SUN4I_WATCHDOG_MODE_REG 0x04
31#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
32#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
33
34#define SUN6I_WATCHDOG1_IRQ_REG 0x00
35#define SUN6I_WATCHDOG1_CTRL_REG 0x10
36#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
37#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
38#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
39#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
40#define SUN6I_WATCHDOG1_MODE_REG 0x18
41#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
42
43static void __iomem *wdt_base;
44
45static void sun4i_restart(enum reboot_mode mode, const char *cmd)
46{
47 if (!wdt_base)
48 return;
49
50 /* Enable timer and set reset bit in the watchdog */
51 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
52 wdt_base + SUN4I_WATCHDOG_MODE_REG);
53
54 /*
55 * Restart the watchdog. The default (and lowest) interval
56 * value for the watchdog is 0.5s.
57 */
58 writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
59
60 while (1) {
61 mdelay(5);
62 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
63 wdt_base + SUN4I_WATCHDOG_MODE_REG);
64 }
65}
66
67static void sun6i_restart(enum reboot_mode mode, const char *cmd)
68{
69 if (!wdt_base)
70 return;
71
72 /* Disable interrupts */
73 writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
74
75 /* We want to disable the IRQ and just reset the whole system */
76 writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
77 wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
78
79 /* Enable timer. The default and lowest interval value is 0.5s */
80 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
81 wdt_base + SUN6I_WATCHDOG1_MODE_REG);
82
83 /* Restart the watchdog. */
84 writel(SUN6I_WATCHDOG1_CTRL_RESTART,
85 wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
86
87 while (1) {
88 mdelay(5);
89 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
90 wdt_base + SUN6I_WATCHDOG1_MODE_REG);
91 }
92}
93
94static struct of_device_id sunxi_restart_ids[] = {
95 { .compatible = "allwinner,sun4i-a10-wdt" },
96 { .compatible = "allwinner,sun6i-a31-wdt" },
97 { /*sentinel*/ }
98};
99
100static void sunxi_setup_restart(void)
101{
102 struct device_node *np;
103
104 np = of_find_matching_node(NULL, sunxi_restart_ids);
105 if (WARN(!np, "unable to setup watchdog restart"))
106 return;
107
108 wdt_base = of_iomap(np, 0);
109 WARN(!wdt_base, "failed to map watchdog base address");
110}
111 18
112static void __init sunxi_dt_init(void) 19static void __init sunxi_dt_init(void)
113{ 20{
114 sunxi_setup_restart();
115
116 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 21 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
117} 22}
118 23
@@ -126,7 +31,6 @@ static const char * const sunxi_board_dt_compat[] = {
126DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") 31DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
127 .init_machine = sunxi_dt_init, 32 .init_machine = sunxi_dt_init,
128 .dt_compat = sunxi_board_dt_compat, 33 .dt_compat = sunxi_board_dt_compat,
129 .restart = sun4i_restart,
130MACHINE_END 34MACHINE_END
131 35
132static const char * const sun6i_board_dt_compat[] = { 36static const char * const sun6i_board_dt_compat[] = {
@@ -146,7 +50,6 @@ DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
146 .init_machine = sunxi_dt_init, 50 .init_machine = sunxi_dt_init,
147 .init_time = sun6i_timer_init, 51 .init_time = sun6i_timer_init,
148 .dt_compat = sun6i_board_dt_compat, 52 .dt_compat = sun6i_board_dt_compat,
149 .restart = sun6i_restart,
150MACHINE_END 53MACHINE_END
151 54
152static const char * const sun7i_board_dt_compat[] = { 55static const char * const sun7i_board_dt_compat[] = {
@@ -157,5 +60,4 @@ static const char * const sun7i_board_dt_compat[] = {
157DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") 60DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
158 .init_machine = sunxi_dt_init, 61 .init_machine = sunxi_dt_init,
159 .dt_compat = sun7i_board_dt_compat, 62 .dt_compat = sun7i_board_dt_compat,
160 .restart = sun4i_restart,
161MACHINE_END 63MACHINE_END