diff options
author | dmitry pervushin <dpervushin@embeddedalley.com> | 2009-05-31 08:31:14 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-05-31 08:55:49 -0400 |
commit | e0421bbe6479816ea16c6553b8f376c592e36a85 (patch) | |
tree | 2bb916f05f8d52272f3c8097ca94039c60bb9d1f /arch/arm/mach-stmp378x | |
parent | b4380b8e5888e5ef5872e43b610c9dac4bf253ac (diff) |
[ARM] 5530/1: Freescale STMP: get rid of HW_zzz macros [1/3]
Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls
Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-stmp378x')
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-apbh.h | 145 | ||||
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-apbx.h | 156 | ||||
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h | 320 | ||||
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-icoll.h | 214 | ||||
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h | 189 | ||||
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-power.h | 51 | ||||
-rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-timrot.h | 240 |
7 files changed, 421 insertions, 894 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h index db63b041e4f0..dbcf85b6ac2a 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h | |||
@@ -1,11 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * STMP APBH Register Definitions | 2 | * stmp378x: APBH register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
6 | * | 6 | * |
7 | * | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | 8 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or | 9 | * the Free Software Foundation; either version 2 of the License, or |
@@ -20,69 +18,84 @@ | |||
20 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
22 | */ | 20 | */ |
21 | #ifndef _MACH_REGS_APBH | ||
22 | #define _MACH_REGS_APBH | ||
23 | |||
24 | #define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) | ||
25 | #define REGS_APBH_PHYS 0x80004000 | ||
26 | #define REGS_APBH_SIZE 0x2000 | ||
27 | |||
28 | #define HW_APBH_CTRL0 0x0 | ||
29 | #define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 | ||
30 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
31 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
32 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
33 | |||
34 | #define HW_APBH_CTRL1 0x10 | ||
35 | #define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 | ||
36 | #define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 | ||
37 | |||
38 | #define HW_APBH_CTRL2 0x20 | ||
39 | |||
40 | #define HW_APBH_DEVSEL 0x30 | ||
41 | |||
42 | #define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) | ||
43 | #define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) | ||
44 | #define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) | ||
45 | #define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) | ||
46 | #define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) | ||
47 | #define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) | ||
48 | #define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) | ||
49 | #define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) | ||
50 | #define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) | ||
51 | #define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) | ||
52 | #define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) | ||
53 | #define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) | ||
54 | #define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) | ||
55 | #define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) | ||
56 | #define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) | ||
57 | #define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) | ||
58 | |||
59 | #define HW_APBH_CHn_NXTCMDAR 0x50 | ||
60 | |||
61 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 | ||
62 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 | ||
63 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 | ||
64 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 | ||
65 | #define BM_APBH_CHn_CMD_COMMAND 0x00000003 | ||
66 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
67 | #define BM_APBH_CHn_CMD_CHAIN 0x00000004 | ||
68 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 | ||
69 | #define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 | ||
70 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 | ||
71 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 | ||
72 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 | ||
73 | #define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 | ||
74 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
75 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 | ||
76 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
23 | 77 | ||
24 | #ifndef __ARCH_ARM___APBH_H | 78 | #define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) |
25 | #define __ARCH_ARM___APBH_H 1 | 79 | #define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) |
80 | #define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) | ||
81 | #define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) | ||
82 | #define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) | ||
83 | #define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) | ||
84 | #define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) | ||
85 | #define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) | ||
86 | #define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) | ||
87 | #define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) | ||
88 | #define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) | ||
89 | #define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) | ||
90 | #define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) | ||
91 | #define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) | ||
92 | #define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) | ||
93 | #define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) | ||
26 | 94 | ||
27 | #include <mach/stmp3xxx_regs.h> | 95 | #define HW_APBH_CHn_SEMA 0x80 |
96 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF | ||
97 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
98 | #define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 | ||
99 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
28 | 100 | ||
29 | #define REGS_APBH_BASE (REGS_BASE + 0x4000) | 101 | #endif |
30 | #define REGS_APBH_BASE_PHYS (0x80004000) | ||
31 | #define REGS_APBH_SIZE 0x00002000 | ||
32 | HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00000000) | ||
33 | #define HW_APBH_CTRL0_ADDR (REGS_APBH_BASE + 0x00000000) | ||
34 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
35 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
36 | #define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 | ||
37 | #define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000 | ||
38 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
39 | #define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 | ||
40 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) \ | ||
41 | (((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL) | ||
42 | HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x00000010) | ||
43 | #define HW_APBH_CTRL1_ADDR (REGS_APBH_BASE + 0x00000010) | ||
44 | HW_REGISTER(HW_APBH_CTRL2, REGS_APBH_BASE, 0x00000020) | ||
45 | HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x00000030) | ||
46 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x00000040, 0x70) | ||
47 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
48 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF | ||
49 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) | ||
50 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x00000050, 0x70) | ||
51 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x00000060, 0x70) | ||
52 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
53 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 | ||
54 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) \ | ||
55 | (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) | ||
56 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
57 | #define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 | ||
58 | #define BF_APBH_CHn_CMD_CMDWORDS(v) \ | ||
59 | (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) | ||
60 | #define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 | ||
61 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 | ||
62 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 | ||
63 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 | ||
64 | #define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 | ||
65 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 | ||
66 | #define BM_APBH_CHn_CMD_CHAIN 0x00000004 | ||
67 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
68 | #define BM_APBH_CHn_CMD_COMMAND 0x00000003 | ||
69 | #define BF_APBH_CHn_CMD_COMMAND(v) \ | ||
70 | (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) | ||
71 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
72 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
73 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
74 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
75 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x00000070, 0x70) | ||
76 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x00000080, 0x70) | ||
77 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
78 | #define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 | ||
79 | #define BF_APBH_CHn_SEMA_PHORE(v) \ | ||
80 | (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) | ||
81 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
82 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF | ||
83 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ | ||
84 | (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) | ||
85 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x00000090, 0x70) | ||
86 | HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0x000000a0, 0x70) | ||
87 | HW_REGISTER_0(HW_APBH_VERSION, REGS_APBH_BASE, 0x000003f0) | ||
88 | #endif /* __ARCH_ARM___APBH_H */ | ||
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h index d0e8e9fe1cce..3b934a4d27f0 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h | |||
@@ -1,10 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * STMP APBX Register Definitions | 2 | * stmp378x: APBX register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
6 | * | 6 | * |
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | 8 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or | 9 | * the Free Software Foundation; either version 2 of the License, or |
@@ -19,61 +18,102 @@ | |||
19 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
21 | */ | 20 | */ |
22 | #ifndef __ARCH_ARM___APBX_H | 21 | #ifndef _MACH_REGS_APBX |
23 | #define __ARCH_ARM___APBX_H 1 | 22 | #define _MACH_REGS_APBX |
23 | |||
24 | #define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) | ||
25 | #define REGS_APBX_PHYS 0x80024000 | ||
26 | #define REGS_APBX_SIZE 0x2000 | ||
27 | |||
28 | #define HW_APBX_CTRL0 0x0 | ||
29 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
30 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
31 | |||
32 | #define HW_APBX_CTRL1 0x10 | ||
33 | |||
34 | #define HW_APBX_CTRL2 0x20 | ||
35 | |||
36 | #define HW_APBX_CHANNEL_CTRL 0x30 | ||
37 | #define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 | ||
38 | #define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 | ||
39 | |||
40 | #define HW_APBX_DEVSEL 0x40 | ||
41 | |||
42 | #define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) | ||
43 | #define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) | ||
44 | #define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) | ||
45 | #define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) | ||
46 | #define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) | ||
47 | #define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) | ||
48 | #define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) | ||
49 | #define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) | ||
50 | #define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) | ||
51 | #define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) | ||
52 | #define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) | ||
53 | #define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) | ||
54 | #define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) | ||
55 | #define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) | ||
56 | #define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) | ||
57 | #define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) | ||
58 | |||
59 | #define HW_APBX_CHn_NXTCMDAR 0x110 | ||
60 | #define BM_APBX_CHn_CMD_COMMAND 0x00000003 | ||
61 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
62 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 | ||
63 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 | ||
64 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 | ||
65 | #define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 | ||
66 | #define BM_APBX_CHn_CMD_CHAIN 0x00000004 | ||
67 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 | ||
68 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 | ||
69 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 | ||
70 | #define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 | ||
71 | #define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 | ||
72 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
73 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 | ||
74 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
75 | |||
76 | #define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) | ||
77 | #define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) | ||
78 | #define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) | ||
79 | #define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) | ||
80 | #define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) | ||
81 | #define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) | ||
82 | #define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) | ||
83 | #define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) | ||
84 | #define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) | ||
85 | #define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) | ||
86 | #define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) | ||
87 | #define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) | ||
88 | #define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) | ||
89 | #define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) | ||
90 | #define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) | ||
91 | #define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) | ||
92 | |||
93 | #define HW_APBX_CHn_BAR 0x130 | ||
94 | |||
95 | #define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) | ||
96 | #define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) | ||
97 | #define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) | ||
98 | #define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) | ||
99 | #define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) | ||
100 | #define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) | ||
101 | #define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) | ||
102 | #define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) | ||
103 | #define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) | ||
104 | #define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) | ||
105 | #define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) | ||
106 | #define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) | ||
107 | #define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) | ||
108 | #define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) | ||
109 | #define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) | ||
110 | #define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) | ||
111 | |||
112 | #define HW_APBX_CHn_SEMA 0x140 | ||
113 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF | ||
114 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
115 | #define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 | ||
116 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
24 | 117 | ||
25 | #include <mach/stmp3xxx_regs.h> | 118 | #endif |
26 | 119 | ||
27 | #define REGS_APBX_BASE (REGS_BASE + 0x24000) | ||
28 | #define REGS_APBX_BASE_PHYS (0x80024000) | ||
29 | #define REGS_APBX_SIZE 0x00002000 | ||
30 | HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00000000) | ||
31 | #define HW_APBX_CTRL0_ADDR (REGS_APBX_BASE + 0x00000000) | ||
32 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
33 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
34 | HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x00000010) | ||
35 | HW_REGISTER(HW_APBX_CTRL2, REGS_APBX_BASE, 0x00000020) | ||
36 | HW_REGISTER(HW_APBX_CHANNEL_CTRL, REGS_APBX_BASE, 0x00000030) | ||
37 | #define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 | ||
38 | #define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 | ||
39 | #define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \ | ||
40 | (((v) << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL) & \ | ||
41 | BM_APBX_CHANNEL_CTRL_RESET_CHANNEL) | ||
42 | HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x00000040) | ||
43 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x00000100, 0x70) | ||
44 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x00000110, 0x70) | ||
45 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x00000120, 0x70) | ||
46 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
47 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 | ||
48 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) \ | ||
49 | (((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT) | ||
50 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
51 | #define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 | ||
52 | #define BF_APBX_CHn_CMD_CMDWORDS(v) \ | ||
53 | (((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS) | ||
54 | #define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 | ||
55 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 | ||
56 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 | ||
57 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 | ||
58 | #define BM_APBX_CHn_CMD_CHAIN 0x00000004 | ||
59 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
60 | #define BM_APBX_CHn_CMD_COMMAND 0x00000003 | ||
61 | #define BF_APBX_CHn_CMD_COMMAND(v) \ | ||
62 | (((v) << 0) & BM_APBX_CHn_CMD_COMMAND) | ||
63 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
64 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
65 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
66 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x00000130, 0x70) | ||
67 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x00000140, 0x70) | ||
68 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
69 | #define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 | ||
70 | #define BF_APBX_CHn_SEMA_PHORE(v) \ | ||
71 | (((v) << 16) & BM_APBX_CHn_SEMA_PHORE) | ||
72 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
73 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF | ||
74 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ | ||
75 | (((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA) | ||
76 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x00000150, 0x70) | ||
77 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0x00000160, 0x70) | ||
78 | HW_REGISTER_0(HW_APBX_VERSION, REGS_APBX_BASE, 0x00000800) | ||
79 | #endif /* __ARCH_ARM___APBX_H */ | ||
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h index a421d9e0cbff..7c546afd57a3 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * STMP CLKCTRL Register Definitions | 2 | * stmp378x: CLKCTRL register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
@@ -18,259 +18,71 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | #ifndef _MACH_REGS_CLKCTRL | ||
22 | #define _MACH_REGS_CLKCTRL | ||
21 | 23 | ||
22 | #ifndef __ARCH_ARM___CLKCTRL_H | 24 | #define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) |
23 | #define __ARCH_ARM___CLKCTRL_H 1 | 25 | #define REGS_CLKCTRL_PHYS 0x80040000 |
26 | #define REGS_CLKCTRL_SIZE 0x2000 | ||
24 | 27 | ||
25 | #include <mach/stmp3xxx_regs.h> | 28 | #define HW_CLKCTRL_PLLCTRL0 0x0 |
29 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 | ||
26 | 30 | ||
27 | #define REGS_CLKCTRL_BASE (REGS_BASE + 0x40000) | 31 | #define HW_CLKCTRL_CPU 0x20 |
28 | #define REGS_CLKCTRL_BASE_PHYS (0x80040000) | 32 | #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F |
29 | #define REGS_CLKCTRL_SIZE 0x00002000 | 33 | #define BP_CLKCTRL_CPU_DIV_CPU 0 |
30 | HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00000000) | 34 | |
31 | #define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00000000) | 35 | #define HW_CLKCTRL_HBUS 0x30 |
32 | #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 | 36 | #define BM_CLKCTRL_HBUS_DIV 0x0000001F |
33 | #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 | 37 | #define BP_CLKCTRL_HBUS_DIV 0 |
34 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ | 38 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 |
35 | (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) | 39 | |
36 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 | 40 | #define HW_CLKCTRL_XBUS 0x40 |
37 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 | 41 | |
38 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 | 42 | #define HW_CLKCTRL_XTAL 0x50 |
39 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 | 43 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 |
40 | #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 | 44 | |
41 | #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 | 45 | #define HW_CLKCTRL_PIX 0x60 |
42 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ | 46 | #define BM_CLKCTRL_PIX_DIV 0x00000FFF |
43 | (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) | 47 | #define BP_CLKCTRL_PIX_DIV 0 |
44 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 | 48 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 |
45 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 | 49 | |
46 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 | 50 | #define HW_CLKCTRL_SSP 0x70 |
47 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 | 51 | |
48 | #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 | 52 | #define HW_CLKCTRL_GPMI 0x80 |
49 | #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 | 53 | |
50 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ | 54 | #define HW_CLKCTRL_SPDIF 0x90 |
51 | (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) | 55 | |
52 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 | 56 | #define HW_CLKCTRL_EMI 0xA0 |
53 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 | 57 | #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F |
54 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 | 58 | #define BP_CLKCTRL_EMI_DIV_EMI 0 |
55 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 | 59 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 |
56 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 | 60 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 |
57 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 | 61 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 |
58 | HW_REGISTER_0(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x00000010) | 62 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 |
59 | #define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x00000010) | 63 | |
60 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | 64 | #define HW_CLKCTRL_IR 0xB0 |
61 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | 65 | |
62 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | 66 | #define HW_CLKCTRL_SAIF 0xC0 |
63 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF | 67 | |
64 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ | 68 | #define HW_CLKCTRL_TV 0xD0 |
65 | (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) | 69 | |
66 | HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x00000020) | 70 | #define HW_CLKCTRL_ETM 0xE0 |
67 | #define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x00000020) | 71 | |
68 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | 72 | #define HW_CLKCTRL_FRAC 0xF0 |
69 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | 73 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 |
70 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 | 74 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 |
71 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | 75 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 |
72 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 | 76 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 |
73 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ | 77 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 |
74 | (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) | 78 | |
75 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 | 79 | #define HW_CLKCTRL_FRAC1 0x100 |
76 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 | 80 | |
77 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | 81 | #define HW_CLKCTRL_CLKSEQ 0x110 |
78 | #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F | 82 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 |
79 | #define BF_CLKCTRL_CPU_DIV_CPU(v) \ | 83 | |
80 | (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) | 84 | #define HW_CLKCTRL_RESET 0x120 |
81 | HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x00000030) | 85 | #define BM_CLKCTRL_RESET_DIG 0x00000001 |
82 | #define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x00000030) | 86 | #define BP_CLKCTRL_RESET_DIG 0 |
83 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | 87 | |
84 | #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 | 88 | #endif |
85 | #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 | ||
86 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 | ||
87 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 | ||
88 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 | ||
89 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 | ||
90 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 | ||
91 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 | ||
92 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 | ||
93 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
94 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 | ||
95 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ | ||
96 | (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) | ||
97 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
98 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
99 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
100 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
101 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
102 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
103 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 | ||
104 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
105 | #define BM_CLKCTRL_HBUS_DIV 0x0000001F | ||
106 | #define BF_CLKCTRL_HBUS_DIV(v) \ | ||
107 | (((v) << 0) & BM_CLKCTRL_HBUS_DIV) | ||
108 | HW_REGISTER_0(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x00000040) | ||
109 | #define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x00000040) | ||
110 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
111 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 | ||
112 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
113 | #define BM_CLKCTRL_XBUS_DIV 0x000003FF | ||
114 | #define BF_CLKCTRL_XBUS_DIV(v) \ | ||
115 | (((v) << 0) & BM_CLKCTRL_XBUS_DIV) | ||
116 | HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x00000050) | ||
117 | #define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x00000050) | ||
118 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
119 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
120 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
121 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
122 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 | ||
123 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 | ||
124 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
125 | #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 | ||
126 | #define BF_CLKCTRL_XTAL_DIV_UART(v) \ | ||
127 | (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) | ||
128 | HW_REGISTER_0(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x00000060) | ||
129 | #define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x00000060) | ||
130 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 | ||
131 | #define BM_CLKCTRL_PIX_BUSY 0x20000000 | ||
132 | #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 | ||
133 | #define BP_CLKCTRL_PIX_DIV 0 | ||
134 | #define BM_CLKCTRL_PIX_DIV 0x00000FFF | ||
135 | #define BF_CLKCTRL_PIX_DIV(v) \ | ||
136 | (((v) << 0) & BM_CLKCTRL_PIX_DIV) | ||
137 | HW_REGISTER_0(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x00000070) | ||
138 | #define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x00000070) | ||
139 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
140 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
141 | #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 | ||
142 | #define BP_CLKCTRL_SSP_DIV 0 | ||
143 | #define BM_CLKCTRL_SSP_DIV 0x000001FF | ||
144 | #define BF_CLKCTRL_SSP_DIV(v) \ | ||
145 | (((v) << 0) & BM_CLKCTRL_SSP_DIV) | ||
146 | HW_REGISTER_0(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x00000080) | ||
147 | #define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x00000080) | ||
148 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
149 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
150 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 | ||
151 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
152 | #define BM_CLKCTRL_GPMI_DIV 0x000003FF | ||
153 | #define BF_CLKCTRL_GPMI_DIV(v) \ | ||
154 | (((v) << 0) & BM_CLKCTRL_GPMI_DIV) | ||
155 | HW_REGISTER_0(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x00000090) | ||
156 | #define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x00000090) | ||
157 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
158 | HW_REGISTER_0(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0x000000a0) | ||
159 | #define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0x000000a0) | ||
160 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
161 | #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 | ||
162 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
163 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
164 | #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 | ||
165 | #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 | ||
166 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 | ||
167 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 | ||
168 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
169 | #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 | ||
170 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ | ||
171 | (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) | ||
172 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
173 | #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F | ||
174 | #define BF_CLKCTRL_EMI_DIV_EMI(v) \ | ||
175 | (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) | ||
176 | HW_REGISTER_0(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0x000000b0) | ||
177 | #define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0x000000b0) | ||
178 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
179 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
180 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
181 | #define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 | ||
182 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
183 | #define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 | ||
184 | #define BF_CLKCTRL_IR_IROV_DIV(v) \ | ||
185 | (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) | ||
186 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
187 | #define BM_CLKCTRL_IR_IR_DIV 0x000003FF | ||
188 | #define BF_CLKCTRL_IR_IR_DIV(v) \ | ||
189 | (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) | ||
190 | HW_REGISTER_0(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0x000000c0) | ||
191 | #define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0x000000c0) | ||
192 | #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 | ||
193 | #define BM_CLKCTRL_SAIF_BUSY 0x20000000 | ||
194 | #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 | ||
195 | #define BP_CLKCTRL_SAIF_DIV 0 | ||
196 | #define BM_CLKCTRL_SAIF_DIV 0x0000FFFF | ||
197 | #define BF_CLKCTRL_SAIF_DIV(v) \ | ||
198 | (((v) << 0) & BM_CLKCTRL_SAIF_DIV) | ||
199 | HW_REGISTER_0(HW_CLKCTRL_TV, REGS_CLKCTRL_BASE, 0x000000d0) | ||
200 | #define HW_CLKCTRL_TV_ADDR (REGS_CLKCTRL_BASE + 0x000000d0) | ||
201 | #define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 | ||
202 | #define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 | ||
203 | HW_REGISTER_0(HW_CLKCTRL_ETM, REGS_CLKCTRL_BASE, 0x000000e0) | ||
204 | #define HW_CLKCTRL_ETM_ADDR (REGS_CLKCTRL_BASE + 0x000000e0) | ||
205 | #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 | ||
206 | #define BM_CLKCTRL_ETM_BUSY 0x20000000 | ||
207 | #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 | ||
208 | #define BP_CLKCTRL_ETM_DIV 0 | ||
209 | #define BM_CLKCTRL_ETM_DIV 0x0000003F | ||
210 | #define BF_CLKCTRL_ETM_DIV(v) \ | ||
211 | (((v) << 0) & BM_CLKCTRL_ETM_DIV) | ||
212 | HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0x000000f0) | ||
213 | #define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0x000000f0) | ||
214 | #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 | ||
215 | #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 | ||
216 | #define BP_CLKCTRL_FRAC_IOFRAC 24 | ||
217 | #define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 | ||
218 | #define BF_CLKCTRL_FRAC_IOFRAC(v) \ | ||
219 | (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) | ||
220 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 | ||
221 | #define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 | ||
222 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 | ||
223 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 | ||
224 | #define BF_CLKCTRL_FRAC_PIXFRAC(v) \ | ||
225 | (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) | ||
226 | #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 | ||
227 | #define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 | ||
228 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 | ||
229 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 | ||
230 | #define BF_CLKCTRL_FRAC_EMIFRAC(v) \ | ||
231 | (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) | ||
232 | #define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 | ||
233 | #define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 | ||
234 | #define BP_CLKCTRL_FRAC_CPUFRAC 0 | ||
235 | #define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F | ||
236 | #define BF_CLKCTRL_FRAC_CPUFRAC(v) \ | ||
237 | (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) | ||
238 | HW_REGISTER(HW_CLKCTRL_FRAC1, REGS_CLKCTRL_BASE, 0x00000100) | ||
239 | #define HW_CLKCTRL_FRAC1_ADDR (REGS_CLKCTRL_BASE + 0x00000100) | ||
240 | #define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 | ||
241 | #define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 | ||
242 | HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0x00000110) | ||
243 | #define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0x00000110) | ||
244 | #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 | ||
245 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 | ||
246 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 | ||
247 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 | ||
248 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 | ||
249 | #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 | ||
250 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 | ||
251 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 | ||
252 | HW_REGISTER_0(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0x00000120) | ||
253 | #define HW_CLKCTRL_RESET_ADDR (REGS_CLKCTRL_BASE + 0x00000120) | ||
254 | #define BM_CLKCTRL_RESET_CHIP 0x00000002 | ||
255 | #define BM_CLKCTRL_RESET_DIG 0x00000001 | ||
256 | HW_REGISTER_0(HW_CLKCTRL_STATUS, REGS_CLKCTRL_BASE, 0x00000130) | ||
257 | #define HW_CLKCTRL_STATUS_ADDR (REGS_CLKCTRL_BASE + 0x00000130) | ||
258 | #define BP_CLKCTRL_STATUS_CPU_LIMIT 30 | ||
259 | #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 | ||
260 | #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ | ||
261 | (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) | ||
262 | HW_REGISTER_0(HW_CLKCTRL_VERSION, REGS_CLKCTRL_BASE, 0x00000140) | ||
263 | #define HW_CLKCTRL_VERSION_ADDR (REGS_CLKCTRL_BASE + 0x00000140) | ||
264 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
265 | #define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 | ||
266 | #define BF_CLKCTRL_VERSION_MAJOR(v) \ | ||
267 | (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) | ||
268 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
269 | #define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 | ||
270 | #define BF_CLKCTRL_VERSION_MINOR(v) \ | ||
271 | (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) | ||
272 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
273 | #define BM_CLKCTRL_VERSION_STEP 0x0000FFFF | ||
274 | #define BF_CLKCTRL_VERSION_STEP(v) \ | ||
275 | (((v) << 0) & BM_CLKCTRL_VERSION_STEP) | ||
276 | #endif /* __ARCH_ARM___CLKCTRL_H */ | ||
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h index a5a530c6440d..f996e80f40e7 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * STMP ICOLL Register Definitions | 2 | * stmp378x: ICOLL register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
@@ -18,196 +18,28 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | #ifndef _MACH_REGS_ICOLL | ||
22 | #define _MACH_REGS_ICOLL | ||
21 | 23 | ||
22 | #ifndef __ARCH_ARM___ICOLL_H | 24 | #define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) |
23 | #define __ARCH_ARM___ICOLL_H 1 | 25 | #define REGS_ICOLL_PHYS 0x80000000 |
26 | #define REGS_ICOLL_SIZE 0x2000 | ||
24 | 27 | ||
25 | #include <mach/stmp3xxx_regs.h> | 28 | #define HW_ICOLL_VECTOR 0x0 |
26 | 29 | ||
27 | #define REGS_ICOLL_BASE (REGS_BASE + 0x0) | 30 | #define HW_ICOLL_LEVELACK 0x10 |
28 | #define REGS_ICOLL_BASE_PHYS (0x80000000) | 31 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F |
29 | #define REGS_ICOLL_SIZE 0x00002000 | 32 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 |
30 | HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00000000) | 33 | |
31 | #define HW_ICOLL_VECTOR_ADDR (REGS_ICOLL_BASE + 0x00000000) | 34 | #define HW_ICOLL_CTRL 0x20 |
32 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | 35 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 |
33 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC | 36 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 |
34 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) \ | 37 | |
35 | (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) | 38 | #define HW_ICOLL_STAT 0x70 |
36 | HW_REGISTER_0(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x00000010) | 39 | |
37 | #define HW_ICOLL_LEVELACK_ADDR (REGS_ICOLL_BASE + 0x00000010) | 40 | #define HW_ICOLL_INTERRUPTn 0x120 |
38 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | 41 | |
39 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F | 42 | #define HW_ICOLL_INTERRUPTn 0x120 |
40 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ | 43 | #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 |
41 | (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) | 44 | |
42 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | 45 | #endif |
43 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
44 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
45 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
46 | HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x00000020) | ||
47 | #define HW_ICOLL_CTRL_ADDR (REGS_ICOLL_BASE + 0x00000020) | ||
48 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
49 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
50 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
51 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
52 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
53 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
54 | #define BP_ICOLL_CTRL_VECTOR_PITCH 21 | ||
55 | #define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 | ||
56 | #define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ | ||
57 | (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) | ||
58 | #define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 | ||
59 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 | ||
60 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 | ||
61 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 | ||
62 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 | ||
63 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 | ||
64 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 | ||
65 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 | ||
66 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 | ||
67 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
68 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
69 | #define BM_ICOLL_CTRL_NO_NESTING 0x00080000 | ||
70 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
71 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
72 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 | ||
73 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 | ||
74 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
75 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
76 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 | ||
77 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
78 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
79 | HW_REGISTER(HW_ICOLL_VBASE, REGS_ICOLL_BASE, 0x00000040) | ||
80 | #define HW_ICOLL_VBASE_ADDR (REGS_ICOLL_BASE + 0x00000040) | ||
81 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
82 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC | ||
83 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ | ||
84 | (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) | ||
85 | HW_REGISTER_0(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x00000070) | ||
86 | #define HW_ICOLL_STAT_ADDR (REGS_ICOLL_BASE + 0x00000070) | ||
87 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
88 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F | ||
89 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ | ||
90 | (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) | ||
91 | /* | ||
92 | * multi-register-define name HW_ICOLL_RAWn | ||
93 | * base 0x000000A0 | ||
94 | * count 4 | ||
95 | * offset 0x10 | ||
96 | */ | ||
97 | HW_REGISTER_0_INDEXED(HW_ICOLL_RAWn, REGS_ICOLL_BASE, 0x000000a0, 0x10) | ||
98 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
99 | #define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF | ||
100 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (v) | ||
101 | /* | ||
102 | * multi-register-define name HW_ICOLL_INTERRUPTn | ||
103 | * base 0x00000120 | ||
104 | * count 128 | ||
105 | * offset 0x10 | ||
106 | */ | ||
107 | HW_REGISTER_INDEXED(HW_ICOLL_INTERRUPTn, REGS_ICOLL_BASE, 0x00000120, 0x10) | ||
108 | #define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 | ||
109 | #define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 | ||
110 | #define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 | ||
111 | #define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 | ||
112 | #define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 | ||
113 | #define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 | ||
114 | #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 | ||
115 | #define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 | ||
116 | #define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 | ||
117 | #define BP_ICOLL_INTERRUPTn_PRIORITY 0 | ||
118 | #define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 | ||
119 | #define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ | ||
120 | (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) | ||
121 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 | ||
122 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 | ||
123 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 | ||
124 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 | ||
125 | HW_REGISTER(HW_ICOLL_DEBUG, REGS_ICOLL_BASE, 0x00001120) | ||
126 | #define HW_ICOLL_DEBUG_ADDR (REGS_ICOLL_BASE + 0x00001120) | ||
127 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
128 | #define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 | ||
129 | #define BF_ICOLL_DEBUG_INSERVICE(v) \ | ||
130 | (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) | ||
131 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
132 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
133 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
134 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
135 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
136 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 | ||
137 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ | ||
138 | (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) | ||
139 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
140 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
141 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
142 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
143 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
144 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 | ||
145 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ | ||
146 | (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) | ||
147 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
148 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
149 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
150 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
151 | #define BM_ICOLL_DEBUG_FIQ 0x00020000 | ||
152 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
153 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
154 | #define BM_ICOLL_DEBUG_IRQ 0x00010000 | ||
155 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
156 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
157 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
158 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF | ||
159 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ | ||
160 | (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) | ||
161 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 | ||
162 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 | ||
163 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 | ||
164 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 | ||
165 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 | ||
166 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 | ||
167 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 | ||
168 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 | ||
169 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 | ||
170 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
171 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
172 | HW_REGISTER(HW_ICOLL_DBGREAD0, REGS_ICOLL_BASE, 0x00001130) | ||
173 | #define HW_ICOLL_DBGREAD0_ADDR (REGS_ICOLL_BASE + 0x00001130) | ||
174 | #define BP_ICOLL_DBGREAD0_VALUE 0 | ||
175 | #define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF | ||
176 | #define BF_ICOLL_DBGREAD0_VALUE(v) (v) | ||
177 | HW_REGISTER(HW_ICOLL_DBGREAD1, REGS_ICOLL_BASE, 0x00001140) | ||
178 | #define HW_ICOLL_DBGREAD1_ADDR (REGS_ICOLL_BASE + 0x00001140) | ||
179 | #define BP_ICOLL_DBGREAD1_VALUE 0 | ||
180 | #define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF | ||
181 | #define BF_ICOLL_DBGREAD1_VALUE(v) (v) | ||
182 | HW_REGISTER(HW_ICOLL_DBGFLAG, REGS_ICOLL_BASE, 0x00001150) | ||
183 | #define HW_ICOLL_DBGFLAG_ADDR (REGS_ICOLL_BASE + 0x00001150) | ||
184 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
185 | #define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF | ||
186 | #define BF_ICOLL_DBGFLAG_FLAG(v) \ | ||
187 | (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) | ||
188 | /* | ||
189 | * multi-register-define name HW_ICOLL_DBGREQUESTn | ||
190 | * base 0x00001160 | ||
191 | * count 4 | ||
192 | * offset 0x10 | ||
193 | */ | ||
194 | HW_REGISTER_0_INDEXED(HW_ICOLL_DBGREQUESTn, REGS_ICOLL_BASE, 0x00001160, | ||
195 | 0x10) | ||
196 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
197 | #define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF | ||
198 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (v) | ||
199 | HW_REGISTER_0(HW_ICOLL_VERSION, REGS_ICOLL_BASE, 0x000011e0) | ||
200 | #define HW_ICOLL_VERSION_ADDR (REGS_ICOLL_BASE + 0x000011e0) | ||
201 | #define BP_ICOLL_VERSION_MAJOR 24 | ||
202 | #define BM_ICOLL_VERSION_MAJOR 0xFF000000 | ||
203 | #define BF_ICOLL_VERSION_MAJOR(v) \ | ||
204 | (((v) << 24) & BM_ICOLL_VERSION_MAJOR) | ||
205 | #define BP_ICOLL_VERSION_MINOR 16 | ||
206 | #define BM_ICOLL_VERSION_MINOR 0x00FF0000 | ||
207 | #define BF_ICOLL_VERSION_MINOR(v) \ | ||
208 | (((v) << 16) & BM_ICOLL_VERSION_MINOR) | ||
209 | #define BP_ICOLL_VERSION_STEP 0 | ||
210 | #define BM_ICOLL_VERSION_STEP 0x0000FFFF | ||
211 | #define BF_ICOLL_VERSION_STEP(v) \ | ||
212 | (((v) << 0) & BM_ICOLL_VERSION_STEP) | ||
213 | #endif /* __ARCH_ARM___ICOLL_H */ | ||
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h index 6c42d2a47c19..50d90ea1b136 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * STMP PINCTRL Register Definitions | 2 | * stmp378x: PINCTRL register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
@@ -18,126 +18,73 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | #ifndef _MACH_REGS_PINCTRL | ||
22 | #define _MACH_REGS_PINCTRL | ||
21 | 23 | ||
22 | #ifndef __ARCH_ARM___PINCTRL_H | 24 | #define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) |
23 | #define __ARCH_ARM___PINCTRL_H 1 | 25 | #define REGS_PINCTRL_PHYS 0x80018000 |
26 | #define REGS_PINCTRL_SIZE 0x2000 | ||
24 | 27 | ||
25 | #include <mach/stmp3xxx_regs.h> | 28 | #define HW_PINCTRL_MUXSEL0 0x100 |
29 | #define HW_PINCTRL_MUXSEL1 0x110 | ||
30 | #define HW_PINCTRL_MUXSEL2 0x120 | ||
31 | #define HW_PINCTRL_MUXSEL3 0x130 | ||
32 | #define HW_PINCTRL_MUXSEL4 0x140 | ||
33 | #define HW_PINCTRL_MUXSEL5 0x150 | ||
34 | #define HW_PINCTRL_MUXSEL6 0x160 | ||
35 | #define HW_PINCTRL_MUXSEL7 0x170 | ||
26 | 36 | ||
27 | #define REGS_PINCTRL_BASE (REGS_BASE + 0x18000) | 37 | #define HW_PINCTRL_DRIVE0 0x200 |
28 | #define REGS_PINCTRL_BASE_PHYS (0x80018000) | 38 | #define HW_PINCTRL_DRIVE1 0x210 |
29 | #define REGS_PINCTRL_SIZE 0x00002000 | 39 | #define HW_PINCTRL_DRIVE2 0x220 |
30 | HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0x00000000) | 40 | #define HW_PINCTRL_DRIVE3 0x230 |
31 | #define HW_PINCTRL_CTRL_ADDR (REGS_PINCTRL_BASE + 0x00000000) | 41 | #define HW_PINCTRL_DRIVE4 0x240 |
32 | #define BM_PINCTRL_CTRL_SFTRST 0x80000000 | 42 | #define HW_PINCTRL_DRIVE5 0x250 |
33 | #define BM_PINCTRL_CTRL_CLKGATE 0x40000000 | 43 | #define HW_PINCTRL_DRIVE6 0x260 |
34 | #define BM_PINCTRL_CTRL_PRESENT3 0x08000000 | 44 | #define HW_PINCTRL_DRIVE7 0x270 |
35 | #define BM_PINCTRL_CTRL_PRESENT2 0x04000000 | 45 | #define HW_PINCTRL_DRIVE8 0x280 |
36 | #define BM_PINCTRL_CTRL_PRESENT1 0x02000000 | 46 | #define HW_PINCTRL_DRIVE9 0x290 |
37 | #define BM_PINCTRL_CTRL_PRESENT0 0x01000000 | 47 | #define HW_PINCTRL_DRIVE10 0x2A0 |
38 | #define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 | 48 | #define HW_PINCTRL_DRIVE11 0x2B0 |
39 | #define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 | 49 | #define HW_PINCTRL_DRIVE12 0x2C0 |
40 | #define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 | 50 | #define HW_PINCTRL_DRIVE13 0x2D0 |
41 | HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x00000100) | 51 | #define HW_PINCTRL_DRIVE14 0x2E0 |
42 | #define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x00000100) | 52 | |
43 | HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x00000110) | 53 | #define HW_PINCTRL_PULL0 0x400 |
44 | #define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x00000110) | 54 | #define HW_PINCTRL_PULL1 0x410 |
45 | HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x00000120) | 55 | #define HW_PINCTRL_PULL2 0x420 |
46 | #define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x00000120) | 56 | #define HW_PINCTRL_PULL3 0x430 |
47 | HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x00000130) | 57 | |
48 | #define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x00000130) | 58 | #define HW_PINCTRL_DOUT0 0x500 |
49 | HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x00000140) | 59 | #define HW_PINCTRL_DOUT1 0x510 |
50 | #define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x00000140) | 60 | #define HW_PINCTRL_DOUT2 0x520 |
51 | HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x00000150) | 61 | |
52 | #define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x00000150) | 62 | #define HW_PINCTRL_DIN0 0x600 |
53 | HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x00000160) | 63 | #define HW_PINCTRL_DIN1 0x610 |
54 | #define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x00000160) | 64 | #define HW_PINCTRL_DIN2 0x620 |
55 | HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x00000170) | 65 | |
56 | #define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x00000170) | 66 | #define HW_PINCTRL_DOE0 0x700 |
57 | HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x00000200) | 67 | #define HW_PINCTRL_DOE1 0x710 |
58 | #define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x00000200) | 68 | #define HW_PINCTRL_DOE2 0x720 |
59 | HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x00000210) | 69 | |
60 | #define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x00000210) | 70 | #define HW_PINCTRL_PIN2IRQ0 0x800 |
61 | HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x00000220) | 71 | #define HW_PINCTRL_PIN2IRQ1 0x810 |
62 | #define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x00000220) | 72 | #define HW_PINCTRL_PIN2IRQ2 0x820 |
63 | HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x00000230) | 73 | |
64 | #define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x00000230) | 74 | #define HW_PINCTRL_IRQEN0 0x900 |
65 | HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x00000240) | 75 | #define HW_PINCTRL_IRQEN1 0x910 |
66 | #define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x00000240) | 76 | #define HW_PINCTRL_IRQEN2 0x920 |
67 | HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x00000250) | 77 | |
68 | #define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x00000250) | 78 | #define HW_PINCTRL_IRQLEVEL0 0xA00 |
69 | HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x00000260) | 79 | #define HW_PINCTRL_IRQLEVEL1 0xA10 |
70 | #define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x00000260) | 80 | #define HW_PINCTRL_IRQLEVEL2 0xA20 |
71 | HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x00000270) | 81 | |
72 | #define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x00000270) | 82 | #define HW_PINCTRL_IRQPOL0 0xB00 |
73 | HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x00000280) | 83 | #define HW_PINCTRL_IRQPOL1 0xB10 |
74 | #define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x00000280) | 84 | #define HW_PINCTRL_IRQPOL2 0xB20 |
75 | HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x00000290) | 85 | |
76 | #define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x00000290) | 86 | #define HW_PINCTRL_IRQSTAT0 0xC00 |
77 | HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x000002a0) | 87 | #define HW_PINCTRL_IRQSTAT1 0xC10 |
78 | #define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x000002a0) | 88 | #define HW_PINCTRL_IRQSTAT2 0xC20 |
79 | HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x000002b0) | 89 | |
80 | #define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x000002b0) | 90 | #endif |
81 | HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x000002c0) | ||
82 | #define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x000002c0) | ||
83 | HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x000002d0) | ||
84 | #define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x000002d0) | ||
85 | HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x000002e0) | ||
86 | #define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x000002e0) | ||
87 | HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x00000400) | ||
88 | #define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x00000400) | ||
89 | HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x00000410) | ||
90 | #define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x00000410) | ||
91 | HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x00000420) | ||
92 | #define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x00000420) | ||
93 | HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x00000430) | ||
94 | #define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x00000430) | ||
95 | HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x00000500) | ||
96 | #define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x00000500) | ||
97 | HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x00000510) | ||
98 | #define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x00000510) | ||
99 | HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x00000520) | ||
100 | #define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x00000520) | ||
101 | HW_REGISTER(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x00000600) | ||
102 | #define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x00000600) | ||
103 | HW_REGISTER(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x00000610) | ||
104 | #define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x00000610) | ||
105 | HW_REGISTER(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x00000620) | ||
106 | #define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x00000620) | ||
107 | HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x00000700) | ||
108 | #define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x00000700) | ||
109 | HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x00000710) | ||
110 | #define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x00000710) | ||
111 | HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x00000720) | ||
112 | #define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x00000720) | ||
113 | HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x00000800) | ||
114 | #define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x00000800) | ||
115 | HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x00000810) | ||
116 | #define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x00000810) | ||
117 | HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x00000820) | ||
118 | #define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x00000820) | ||
119 | HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x00000900) | ||
120 | #define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x00000900) | ||
121 | HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x00000910) | ||
122 | #define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x00000910) | ||
123 | HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x00000920) | ||
124 | #define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x00000920) | ||
125 | HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x00000a00) | ||
126 | #define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x00000a00) | ||
127 | HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x00000a10) | ||
128 | #define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x00000a10) | ||
129 | HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x00000a20) | ||
130 | #define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x00000a20) | ||
131 | HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0x00000b00) | ||
132 | #define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0x00000b00) | ||
133 | HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0x00000b10) | ||
134 | #define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0x00000b10) | ||
135 | HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0x00000b20) | ||
136 | #define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0x00000b20) | ||
137 | HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0x00000c00) | ||
138 | #define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0x00000c00) | ||
139 | HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0x00000c10) | ||
140 | #define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0x00000c10) | ||
141 | HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0x00000c20) | ||
142 | #define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0x00000c20) | ||
143 | #endif /* __ARCH_ARM___PINCTRL_H */ | ||
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h index 1c81afeed531..e454c830f076 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-power.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-power.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * STMP POWER Register Definitions | 2 | * stmp378x: POWER register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
@@ -18,15 +18,46 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | #ifndef _MACH_REGS_POWER | ||
22 | #define _MACH_REGS_POWER | ||
21 | 23 | ||
22 | #ifndef __ARCH_ARM___POWER_H | 24 | #define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) |
23 | #define __ARCH_ARM___POWER_H 1 | 25 | #define REGS_POWER_PHYS 0x80044000 |
26 | #define REGS_POWER_SIZE 0x2000 | ||
24 | 27 | ||
25 | #include <mach/stmp3xxx_regs.h> | 28 | #define HW_POWER_CTRL 0x0 |
29 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 | ||
30 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
31 | #define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 | ||
32 | #define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 | ||
33 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
26 | 34 | ||
27 | #define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000) | 35 | #define HW_POWER_5VCTRL 0x10 |
28 | #define REGS_POWER_BASE_PHYS (0x80044000) | 36 | #define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 |
29 | #define REGS_POWER_SIZE 0x00002000 | 37 | |
30 | HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020) | 38 | #define HW_POWER_MINPWR 0x20 |
31 | HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030) | 39 | |
32 | #endif /* __ARCH_ARM___POWER_H */ | 40 | #define HW_POWER_CHARGE 0x30 |
41 | |||
42 | #define HW_POWER_VDDDCTRL 0x40 | ||
43 | |||
44 | #define HW_POWER_VDDACTRL 0x50 | ||
45 | |||
46 | #define HW_POWER_VDDIOCTRL 0x60 | ||
47 | #define BM_POWER_VDDIOCTRL_TRG 0x0000001F | ||
48 | #define BP_POWER_VDDIOCTRL_TRG 0 | ||
49 | |||
50 | #define HW_POWER_STS 0xC0 | ||
51 | #define BM_POWER_STS_VBUSVALID 0x00000002 | ||
52 | #define BM_POWER_STS_BVALID 0x00000004 | ||
53 | #define BM_POWER_STS_AVALID 0x00000008 | ||
54 | #define BM_POWER_STS_DC_OK 0x00000200 | ||
55 | |||
56 | #define HW_POWER_RESET 0x100 | ||
57 | |||
58 | #define HW_POWER_DEBUG 0x110 | ||
59 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 | ||
60 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 | ||
61 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 | ||
62 | |||
63 | #endif | ||
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h index bb6355acdfd1..b5527957c67f 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * STMP TIMROT Register Definitions | 2 | * stmp378x: TIMROT register definitions |
3 | * | 3 | * |
4 | * Copyright (c) 2008 Freescale Semiconductor | 4 | * Copyright (c) 2008 Freescale Semiconductor |
5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
@@ -18,199 +18,51 @@ | |||
18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
20 | */ | 20 | */ |
21 | #ifndef _MACH_REGS_TIMROT | ||
22 | #define _MACH_REGS_TIMROT | ||
21 | 23 | ||
22 | #ifndef __ARCH_ARM___TIMROT_H | 24 | #define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) |
23 | #define __ARCH_ARM___TIMROT_H 1 | 25 | #define REGS_TIMROT_PHYS 0x80068000 |
26 | #define REGS_TIMROT_SIZE 0x2000 | ||
24 | 27 | ||
25 | #include <mach/stmp3xxx_regs.h> | 28 | #define HW_TIMROT_ROTCTRL 0x0 |
29 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 | ||
30 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
31 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 | ||
32 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
33 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 | ||
34 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 | ||
35 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 | ||
36 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
37 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 | ||
38 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 | ||
39 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
40 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
41 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
42 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
26 | 43 | ||
27 | #define REGS_TIMROT_BASE (REGS_BASE + 0x68000) | 44 | #define HW_TIMROT_ROTCOUNT 0x10 |
28 | #define REGS_TIMROT_BASE_PHYS (0x80068000) | 45 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF |
29 | #define REGS_TIMROT_SIZE 0x00002000 | 46 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 |
30 | HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0x00000000) | 47 | |
31 | #define HW_TIMROT_ROTCTRL_ADDR (REGS_TIMROT_BASE + 0x00000000) | 48 | #define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) |
32 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | 49 | #define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) |
33 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | 50 | #define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) |
34 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | 51 | |
35 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | 52 | #define HW_TIMROT_TIMCTRLn 0x20 |
36 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 | 53 | #define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F |
37 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 | 54 | #define BP_TIMROT_TIMCTRLn_SELECT 0 |
38 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 | 55 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 |
39 | #define BP_TIMROT_ROTCTRL_STATE 22 | 56 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 |
40 | #define BM_TIMROT_ROTCTRL_STATE 0x01C00000 | 57 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 |
41 | #define BF_TIMROT_ROTCTRL_STATE(v) \ | 58 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 |
42 | (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) | 59 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 |
43 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | 60 | #define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 |
44 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 | 61 | |
45 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) \ | 62 | #define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) |
46 | (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) | 63 | #define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) |
47 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 | 64 | #define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) |
48 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | 65 | |
49 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 | 66 | #define HW_TIMROT_TIMCOUNTn 0x30 |
50 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ | 67 | |
51 | (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) | 68 | #endif |
52 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
53 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
54 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
55 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
56 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 | ||
57 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 | ||
58 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
59 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 | ||
60 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) \ | ||
61 | (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) | ||
62 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
63 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
64 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
65 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
66 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
67 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
68 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
69 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
70 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
71 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 | ||
72 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) \ | ||
73 | (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) | ||
74 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
75 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
76 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
77 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
78 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
79 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
80 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
81 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
82 | HW_REGISTER_0(HW_TIMROT_ROTCOUNT, REGS_TIMROT_BASE, 0x00000010) | ||
83 | #define HW_TIMROT_ROTCOUNT_ADDR (REGS_TIMROT_BASE + 0x00000010) | ||
84 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
85 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF | ||
86 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ | ||
87 | (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) | ||
88 | /* | ||
89 | * multi-register-define name HW_TIMROT_TIMCTRLn | ||
90 | * base 0x00000020 | ||
91 | * count 3 | ||
92 | * offset 0x20 | ||
93 | */ | ||
94 | HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x00000020, 0x20) | ||
95 | #define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 | ||
96 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 | ||
97 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 | ||
98 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 | ||
99 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 | ||
100 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
101 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 | ||
102 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ | ||
103 | (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) | ||
104 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
105 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
106 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
107 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
108 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
109 | #define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F | ||
110 | #define BF_TIMROT_TIMCTRLn_SELECT(v) \ | ||
111 | (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) | ||
112 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
113 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
114 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
115 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
116 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
117 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
118 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
119 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
120 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
121 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
122 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA | ||
123 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB | ||
124 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC | ||
125 | /* | ||
126 | * multi-register-define name HW_TIMROT_TIMCOUNTn | ||
127 | * base 0x00000030 | ||
128 | * count 3 | ||
129 | * offset 0x20 | ||
130 | */ | ||
131 | HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x00000030, | ||
132 | 0x20) | ||
133 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
134 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000 | ||
135 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \ | ||
136 | (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT) | ||
137 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
138 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF | ||
139 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \ | ||
140 | (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT) | ||
141 | HW_REGISTER(HW_TIMROT_TIMCTRL3, REGS_TIMROT_BASE, 0x00000080) | ||
142 | #define HW_TIMROT_TIMCTRL3_ADDR (REGS_TIMROT_BASE + 0x00000080) | ||
143 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
144 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 | ||
145 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ | ||
146 | (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) | ||
147 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
148 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
149 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
150 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
151 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
152 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
153 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
154 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
155 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
156 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
157 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA | ||
158 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB | ||
159 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC | ||
160 | #define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 | ||
161 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 | ||
162 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 | ||
163 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 | ||
164 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 | ||
165 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 | ||
166 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 | ||
167 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
168 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 | ||
169 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ | ||
170 | (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) | ||
171 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
172 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
173 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
174 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
175 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
176 | #define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F | ||
177 | #define BF_TIMROT_TIMCTRL3_SELECT(v) \ | ||
178 | (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) | ||
179 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
180 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
181 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
182 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
183 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
184 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
185 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
186 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
187 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
188 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
189 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA | ||
190 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB | ||
191 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC | ||
192 | HW_REGISTER_0(HW_TIMROT_TIMCOUNT3, REGS_TIMROT_BASE, 0x00000090) | ||
193 | #define HW_TIMROT_TIMCOUNT3_ADDR (REGS_TIMROT_BASE + 0x00000090) | ||
194 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
195 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000 | ||
196 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \ | ||
197 | (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT) | ||
198 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
199 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF | ||
200 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \ | ||
201 | (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT) | ||
202 | HW_REGISTER_0(HW_TIMROT_VERSION, REGS_TIMROT_BASE, 0x000000a0) | ||
203 | #define HW_TIMROT_VERSION_ADDR (REGS_TIMROT_BASE + 0x000000a0) | ||
204 | #define BP_TIMROT_VERSION_MAJOR 24 | ||
205 | #define BM_TIMROT_VERSION_MAJOR 0xFF000000 | ||
206 | #define BF_TIMROT_VERSION_MAJOR(v) \ | ||
207 | (((v) << 24) & BM_TIMROT_VERSION_MAJOR) | ||
208 | #define BP_TIMROT_VERSION_MINOR 16 | ||
209 | #define BM_TIMROT_VERSION_MINOR 0x00FF0000 | ||
210 | #define BF_TIMROT_VERSION_MINOR(v) \ | ||
211 | (((v) << 16) & BM_TIMROT_VERSION_MINOR) | ||
212 | #define BP_TIMROT_VERSION_STEP 0 | ||
213 | #define BM_TIMROT_VERSION_STEP 0x0000FFFF | ||
214 | #define BF_TIMROT_VERSION_STEP(v) \ | ||
215 | (((v) << 0) & BM_TIMROT_VERSION_STEP) | ||
216 | #endif /* __ARCH_ARM___TIMROT_H */ | ||