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authorArnd Bergmann <arnd@arndb.de>2012-05-14 09:59:18 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 11:35:50 -0400
commit090a80cba39f2763a488b6f7c65e38922d5aa17a (patch)
treeba3797eeca74c42be95bc592ed2db1be99e329d2 /arch/arm/mach-spear6xx
parent36be50515fe2aef61533b516fa2576a2c7fe7664 (diff)
parenteb3f995d7e73fd78b8fcdc55cfbf01a74a09a6e8 (diff)
Merge branch 'spear/13xx' into next/soc2
* spear/13xx: pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res SPEAr: Update MAINTAINERS and Documentation SPEAr13xx: Add defconfig SPEAr13xx: Add compilation support SPEAr13xx: Add dts and dtsi files pinctrl: Add SPEAr13xx pinctrl drivers pinctrl: SPEAr: Create macro for declaring GPIO PINS SPEAr13xx: Add common clock framework support SPEAr13xx: Add source files SPEAr13xx: Add header files Depends on clock, pinctrl and dt branches to go first. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-spear6xx')
-rw-r--r--arch/arm/mach-spear6xx/Makefile2
-rw-r--r--arch/arm/mach-spear6xx/Makefile.boot2
-rw-r--r--arch/arm/mach-spear6xx/clock.c683
-rw-r--r--arch/arm/mach-spear6xx/include/mach/generic.h29
-rw-r--r--arch/arm/mach-spear6xx/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-spear6xx/include/mach/irqs.h76
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h154
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h56
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear600.h21
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c422
10 files changed, 411 insertions, 1058 deletions
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += clock.o spear6xx.o 6obj-y += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index a86499a8a15f..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/clock.c
3 *
4 * SPEAr6xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <plat/clock.h>
18#include <mach/misc_regs.h>
19
20/* root clks */
21/* 32 KHz oscillator clock */
22static struct clk osc_32k_clk = {
23 .flags = ALWAYS_ENABLED,
24 .rate = 32000,
25};
26
27/* 30 MHz oscillator clock */
28static struct clk osc_30m_clk = {
29 .flags = ALWAYS_ENABLED,
30 .rate = 30000000,
31};
32
33/* clock derived from 32 KHz osc clk */
34/* rtc clock */
35static struct clk rtc_clk = {
36 .pclk = &osc_32k_clk,
37 .en_reg = PERIP1_CLK_ENB,
38 .en_reg_bit = RTC_CLK_ENB,
39 .recalc = &follow_parent,
40};
41
42/* clock derived from 30 MHz osc clk */
43/* pll masks structure */
44static struct pll_clk_masks pll1_masks = {
45 .mode_mask = PLL_MODE_MASK,
46 .mode_shift = PLL_MODE_SHIFT,
47 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
48 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
49 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
50 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
51 .div_p_mask = PLL_DIV_P_MASK,
52 .div_p_shift = PLL_DIV_P_SHIFT,
53 .div_n_mask = PLL_DIV_N_MASK,
54 .div_n_shift = PLL_DIV_N_SHIFT,
55};
56
57/* pll1 configuration structure */
58static struct pll_clk_config pll1_config = {
59 .mode_reg = PLL1_CTR,
60 .cfg_reg = PLL1_FRQ,
61 .masks = &pll1_masks,
62};
63
64/* pll rate configuration table, in ascending order of rates */
65struct pll_rate_tbl pll_rtbl[] = {
66 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
67 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
68};
69
70/* PLL1 clock */
71static struct clk pll1_clk = {
72 .flags = ENABLED_ON_INIT,
73 .pclk = &osc_30m_clk,
74 .en_reg = PLL1_CTR,
75 .en_reg_bit = PLL_ENABLE,
76 .calc_rate = &pll_calc_rate,
77 .recalc = &pll_clk_recalc,
78 .set_rate = &pll_clk_set_rate,
79 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
80 .private_data = &pll1_config,
81};
82
83/* PLL3 48 MHz clock */
84static struct clk pll3_48m_clk = {
85 .flags = ALWAYS_ENABLED,
86 .pclk = &osc_30m_clk,
87 .rate = 48000000,
88};
89
90/* watch dog timer clock */
91static struct clk wdt_clk = {
92 .flags = ALWAYS_ENABLED,
93 .pclk = &osc_30m_clk,
94 .recalc = &follow_parent,
95};
96
97/* clock derived from pll1 clk */
98/* cpu clock */
99static struct clk cpu_clk = {
100 .flags = ALWAYS_ENABLED,
101 .pclk = &pll1_clk,
102 .recalc = &follow_parent,
103};
104
105/* ahb masks structure */
106static struct bus_clk_masks ahb_masks = {
107 .mask = PLL_HCLK_RATIO_MASK,
108 .shift = PLL_HCLK_RATIO_SHIFT,
109};
110
111/* ahb configuration structure */
112static struct bus_clk_config ahb_config = {
113 .reg = CORE_CLK_CFG,
114 .masks = &ahb_masks,
115};
116
117/* ahb rate configuration table, in ascending order of rates */
118struct bus_rate_tbl bus_rtbl[] = {
119 {.div = 3}, /* == parent divided by 4 */
120 {.div = 2}, /* == parent divided by 3 */
121 {.div = 1}, /* == parent divided by 2 */
122 {.div = 0}, /* == parent divided by 1 */
123};
124
125/* ahb clock */
126static struct clk ahb_clk = {
127 .flags = ALWAYS_ENABLED,
128 .pclk = &pll1_clk,
129 .calc_rate = &bus_calc_rate,
130 .recalc = &bus_clk_recalc,
131 .set_rate = &bus_clk_set_rate,
132 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
133 .private_data = &ahb_config,
134};
135
136/* auxiliary synthesizers masks */
137static struct aux_clk_masks aux_masks = {
138 .eq_sel_mask = AUX_EQ_SEL_MASK,
139 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
140 .eq1_mask = AUX_EQ1_SEL,
141 .eq2_mask = AUX_EQ2_SEL,
142 .xscale_sel_mask = AUX_XSCALE_MASK,
143 .xscale_sel_shift = AUX_XSCALE_SHIFT,
144 .yscale_sel_mask = AUX_YSCALE_MASK,
145 .yscale_sel_shift = AUX_YSCALE_SHIFT,
146};
147
148/* uart configurations */
149static struct aux_clk_config uart_synth_config = {
150 .synth_reg = UART_CLK_SYNT,
151 .masks = &aux_masks,
152};
153
154/* aux rate configuration table, in ascending order of rates */
155struct aux_rate_tbl aux_rtbl[] = {
156 /* For PLL1 = 332 MHz */
157 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
158 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
159 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
160};
161
162/* uart synth clock */
163static struct clk uart_synth_clk = {
164 .en_reg = UART_CLK_SYNT,
165 .en_reg_bit = AUX_SYNT_ENB,
166 .pclk = &pll1_clk,
167 .calc_rate = &aux_calc_rate,
168 .recalc = &aux_clk_recalc,
169 .set_rate = &aux_clk_set_rate,
170 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
171 .private_data = &uart_synth_config,
172};
173
174/* uart parents */
175static struct pclk_info uart_pclk_info[] = {
176 {
177 .pclk = &uart_synth_clk,
178 .pclk_val = AUX_CLK_PLL1_VAL,
179 }, {
180 .pclk = &pll3_48m_clk,
181 .pclk_val = AUX_CLK_PLL3_VAL,
182 },
183};
184
185/* uart parent select structure */
186static struct pclk_sel uart_pclk_sel = {
187 .pclk_info = uart_pclk_info,
188 .pclk_count = ARRAY_SIZE(uart_pclk_info),
189 .pclk_sel_reg = PERIP_CLK_CFG,
190 .pclk_sel_mask = UART_CLK_MASK,
191};
192
193/* uart0 clock */
194static struct clk uart0_clk = {
195 .en_reg = PERIP1_CLK_ENB,
196 .en_reg_bit = UART0_CLK_ENB,
197 .pclk_sel = &uart_pclk_sel,
198 .pclk_sel_shift = UART_CLK_SHIFT,
199 .recalc = &follow_parent,
200};
201
202/* uart1 clock */
203static struct clk uart1_clk = {
204 .en_reg = PERIP1_CLK_ENB,
205 .en_reg_bit = UART1_CLK_ENB,
206 .pclk_sel = &uart_pclk_sel,
207 .pclk_sel_shift = UART_CLK_SHIFT,
208 .recalc = &follow_parent,
209};
210
211/* firda configurations */
212static struct aux_clk_config firda_synth_config = {
213 .synth_reg = FIRDA_CLK_SYNT,
214 .masks = &aux_masks,
215};
216
217/* firda synth clock */
218static struct clk firda_synth_clk = {
219 .en_reg = FIRDA_CLK_SYNT,
220 .en_reg_bit = AUX_SYNT_ENB,
221 .pclk = &pll1_clk,
222 .calc_rate = &aux_calc_rate,
223 .recalc = &aux_clk_recalc,
224 .set_rate = &aux_clk_set_rate,
225 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
226 .private_data = &firda_synth_config,
227};
228
229/* firda parents */
230static struct pclk_info firda_pclk_info[] = {
231 {
232 .pclk = &firda_synth_clk,
233 .pclk_val = AUX_CLK_PLL1_VAL,
234 }, {
235 .pclk = &pll3_48m_clk,
236 .pclk_val = AUX_CLK_PLL3_VAL,
237 },
238};
239
240/* firda parent select structure */
241static struct pclk_sel firda_pclk_sel = {
242 .pclk_info = firda_pclk_info,
243 .pclk_count = ARRAY_SIZE(firda_pclk_info),
244 .pclk_sel_reg = PERIP_CLK_CFG,
245 .pclk_sel_mask = FIRDA_CLK_MASK,
246};
247
248/* firda clock */
249static struct clk firda_clk = {
250 .en_reg = PERIP1_CLK_ENB,
251 .en_reg_bit = FIRDA_CLK_ENB,
252 .pclk_sel = &firda_pclk_sel,
253 .pclk_sel_shift = FIRDA_CLK_SHIFT,
254 .recalc = &follow_parent,
255};
256
257/* clcd configurations */
258static struct aux_clk_config clcd_synth_config = {
259 .synth_reg = CLCD_CLK_SYNT,
260 .masks = &aux_masks,
261};
262
263/* firda synth clock */
264static struct clk clcd_synth_clk = {
265 .en_reg = CLCD_CLK_SYNT,
266 .en_reg_bit = AUX_SYNT_ENB,
267 .pclk = &pll1_clk,
268 .calc_rate = &aux_calc_rate,
269 .recalc = &aux_clk_recalc,
270 .set_rate = &aux_clk_set_rate,
271 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
272 .private_data = &clcd_synth_config,
273};
274
275/* clcd parents */
276static struct pclk_info clcd_pclk_info[] = {
277 {
278 .pclk = &clcd_synth_clk,
279 .pclk_val = AUX_CLK_PLL1_VAL,
280 }, {
281 .pclk = &pll3_48m_clk,
282 .pclk_val = AUX_CLK_PLL3_VAL,
283 },
284};
285
286/* clcd parent select structure */
287static struct pclk_sel clcd_pclk_sel = {
288 .pclk_info = clcd_pclk_info,
289 .pclk_count = ARRAY_SIZE(clcd_pclk_info),
290 .pclk_sel_reg = PERIP_CLK_CFG,
291 .pclk_sel_mask = CLCD_CLK_MASK,
292};
293
294/* clcd clock */
295static struct clk clcd_clk = {
296 .en_reg = PERIP1_CLK_ENB,
297 .en_reg_bit = CLCD_CLK_ENB,
298 .pclk_sel = &clcd_pclk_sel,
299 .pclk_sel_shift = CLCD_CLK_SHIFT,
300 .recalc = &follow_parent,
301};
302
303/* gpt synthesizer masks */
304static struct gpt_clk_masks gpt_masks = {
305 .mscale_sel_mask = GPT_MSCALE_MASK,
306 .mscale_sel_shift = GPT_MSCALE_SHIFT,
307 .nscale_sel_mask = GPT_NSCALE_MASK,
308 .nscale_sel_shift = GPT_NSCALE_SHIFT,
309};
310
311/* gpt rate configuration table, in ascending order of rates */
312struct gpt_rate_tbl gpt_rtbl[] = {
313 /* For pll1 = 332 MHz */
314 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
315 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
316 {.mscale = 1, .nscale = 0}, /* 83 MHz */
317};
318
319/* gpt0 synth clk config*/
320static struct gpt_clk_config gpt0_synth_config = {
321 .synth_reg = PRSC1_CLK_CFG,
322 .masks = &gpt_masks,
323};
324
325/* gpt synth clock */
326static struct clk gpt0_synth_clk = {
327 .flags = ALWAYS_ENABLED,
328 .pclk = &pll1_clk,
329 .calc_rate = &gpt_calc_rate,
330 .recalc = &gpt_clk_recalc,
331 .set_rate = &gpt_clk_set_rate,
332 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
333 .private_data = &gpt0_synth_config,
334};
335
336/* gpt parents */
337static struct pclk_info gpt0_pclk_info[] = {
338 {
339 .pclk = &gpt0_synth_clk,
340 .pclk_val = AUX_CLK_PLL1_VAL,
341 }, {
342 .pclk = &pll3_48m_clk,
343 .pclk_val = AUX_CLK_PLL3_VAL,
344 },
345};
346
347/* gpt parent select structure */
348static struct pclk_sel gpt0_pclk_sel = {
349 .pclk_info = gpt0_pclk_info,
350 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
351 .pclk_sel_reg = PERIP_CLK_CFG,
352 .pclk_sel_mask = GPT_CLK_MASK,
353};
354
355/* gpt0 ARM1 subsystem timer clock */
356static struct clk gpt0_clk = {
357 .flags = ALWAYS_ENABLED,
358 .pclk_sel = &gpt0_pclk_sel,
359 .pclk_sel_shift = GPT0_CLK_SHIFT,
360 .recalc = &follow_parent,
361};
362
363
364/* Note: gpt0 and gpt1 share same parent clocks */
365/* gpt parent select structure */
366static struct pclk_sel gpt1_pclk_sel = {
367 .pclk_info = gpt0_pclk_info,
368 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
369 .pclk_sel_reg = PERIP_CLK_CFG,
370 .pclk_sel_mask = GPT_CLK_MASK,
371};
372
373/* gpt1 timer clock */
374static struct clk gpt1_clk = {
375 .flags = ALWAYS_ENABLED,
376 .pclk_sel = &gpt1_pclk_sel,
377 .pclk_sel_shift = GPT1_CLK_SHIFT,
378 .recalc = &follow_parent,
379};
380
381/* gpt2 synth clk config*/
382static struct gpt_clk_config gpt2_synth_config = {
383 .synth_reg = PRSC2_CLK_CFG,
384 .masks = &gpt_masks,
385};
386
387/* gpt synth clock */
388static struct clk gpt2_synth_clk = {
389 .flags = ALWAYS_ENABLED,
390 .pclk = &pll1_clk,
391 .calc_rate = &gpt_calc_rate,
392 .recalc = &gpt_clk_recalc,
393 .set_rate = &gpt_clk_set_rate,
394 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
395 .private_data = &gpt2_synth_config,
396};
397
398/* gpt parents */
399static struct pclk_info gpt2_pclk_info[] = {
400 {
401 .pclk = &gpt2_synth_clk,
402 .pclk_val = AUX_CLK_PLL1_VAL,
403 }, {
404 .pclk = &pll3_48m_clk,
405 .pclk_val = AUX_CLK_PLL3_VAL,
406 },
407};
408
409/* gpt parent select structure */
410static struct pclk_sel gpt2_pclk_sel = {
411 .pclk_info = gpt2_pclk_info,
412 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
413 .pclk_sel_reg = PERIP_CLK_CFG,
414 .pclk_sel_mask = GPT_CLK_MASK,
415};
416
417/* gpt2 timer clock */
418static struct clk gpt2_clk = {
419 .flags = ALWAYS_ENABLED,
420 .pclk_sel = &gpt2_pclk_sel,
421 .pclk_sel_shift = GPT2_CLK_SHIFT,
422 .recalc = &follow_parent,
423};
424
425/* gpt3 synth clk config*/
426static struct gpt_clk_config gpt3_synth_config = {
427 .synth_reg = PRSC3_CLK_CFG,
428 .masks = &gpt_masks,
429};
430
431/* gpt synth clock */
432static struct clk gpt3_synth_clk = {
433 .flags = ALWAYS_ENABLED,
434 .pclk = &pll1_clk,
435 .calc_rate = &gpt_calc_rate,
436 .recalc = &gpt_clk_recalc,
437 .set_rate = &gpt_clk_set_rate,
438 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
439 .private_data = &gpt3_synth_config,
440};
441
442/* gpt parents */
443static struct pclk_info gpt3_pclk_info[] = {
444 {
445 .pclk = &gpt3_synth_clk,
446 .pclk_val = AUX_CLK_PLL1_VAL,
447 }, {
448 .pclk = &pll3_48m_clk,
449 .pclk_val = AUX_CLK_PLL3_VAL,
450 },
451};
452
453/* gpt parent select structure */
454static struct pclk_sel gpt3_pclk_sel = {
455 .pclk_info = gpt3_pclk_info,
456 .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
457 .pclk_sel_reg = PERIP_CLK_CFG,
458 .pclk_sel_mask = GPT_CLK_MASK,
459};
460
461/* gpt3 timer clock */
462static struct clk gpt3_clk = {
463 .flags = ALWAYS_ENABLED,
464 .pclk_sel = &gpt3_pclk_sel,
465 .pclk_sel_shift = GPT3_CLK_SHIFT,
466 .recalc = &follow_parent,
467};
468
469/* clock derived from pll3 clk */
470/* usbh0 clock */
471static struct clk usbh0_clk = {
472 .pclk = &pll3_48m_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = USBH0_CLK_ENB,
475 .recalc = &follow_parent,
476};
477
478/* usbh1 clock */
479static struct clk usbh1_clk = {
480 .pclk = &pll3_48m_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = USBH1_CLK_ENB,
483 .recalc = &follow_parent,
484};
485
486/* usbd clock */
487static struct clk usbd_clk = {
488 .pclk = &pll3_48m_clk,
489 .en_reg = PERIP1_CLK_ENB,
490 .en_reg_bit = USBD_CLK_ENB,
491 .recalc = &follow_parent,
492};
493
494/* clock derived from ahb clk */
495/* apb masks structure */
496static struct bus_clk_masks apb_masks = {
497 .mask = HCLK_PCLK_RATIO_MASK,
498 .shift = HCLK_PCLK_RATIO_SHIFT,
499};
500
501/* apb configuration structure */
502static struct bus_clk_config apb_config = {
503 .reg = CORE_CLK_CFG,
504 .masks = &apb_masks,
505};
506
507/* apb clock */
508static struct clk apb_clk = {
509 .flags = ALWAYS_ENABLED,
510 .pclk = &ahb_clk,
511 .calc_rate = &bus_calc_rate,
512 .recalc = &bus_clk_recalc,
513 .set_rate = &bus_clk_set_rate,
514 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
515 .private_data = &apb_config,
516};
517
518/* i2c clock */
519static struct clk i2c_clk = {
520 .pclk = &ahb_clk,
521 .en_reg = PERIP1_CLK_ENB,
522 .en_reg_bit = I2C_CLK_ENB,
523 .recalc = &follow_parent,
524};
525
526/* dma clock */
527static struct clk dma_clk = {
528 .pclk = &ahb_clk,
529 .en_reg = PERIP1_CLK_ENB,
530 .en_reg_bit = DMA_CLK_ENB,
531 .recalc = &follow_parent,
532};
533
534/* jpeg clock */
535static struct clk jpeg_clk = {
536 .pclk = &ahb_clk,
537 .en_reg = PERIP1_CLK_ENB,
538 .en_reg_bit = JPEG_CLK_ENB,
539 .recalc = &follow_parent,
540};
541
542/* gmac clock */
543static struct clk gmac_clk = {
544 .pclk = &ahb_clk,
545 .en_reg = PERIP1_CLK_ENB,
546 .en_reg_bit = GMAC_CLK_ENB,
547 .recalc = &follow_parent,
548};
549
550/* smi clock */
551static struct clk smi_clk = {
552 .pclk = &ahb_clk,
553 .en_reg = PERIP1_CLK_ENB,
554 .en_reg_bit = SMI_CLK_ENB,
555 .recalc = &follow_parent,
556};
557
558/* fsmc clock */
559static struct clk fsmc_clk = {
560 .pclk = &ahb_clk,
561 .en_reg = PERIP1_CLK_ENB,
562 .en_reg_bit = FSMC_CLK_ENB,
563 .recalc = &follow_parent,
564};
565
566/* clock derived from apb clk */
567/* adc clock */
568static struct clk adc_clk = {
569 .pclk = &apb_clk,
570 .en_reg = PERIP1_CLK_ENB,
571 .en_reg_bit = ADC_CLK_ENB,
572 .recalc = &follow_parent,
573};
574
575/* ssp0 clock */
576static struct clk ssp0_clk = {
577 .pclk = &apb_clk,
578 .en_reg = PERIP1_CLK_ENB,
579 .en_reg_bit = SSP0_CLK_ENB,
580 .recalc = &follow_parent,
581};
582
583/* ssp1 clock */
584static struct clk ssp1_clk = {
585 .pclk = &apb_clk,
586 .en_reg = PERIP1_CLK_ENB,
587 .en_reg_bit = SSP1_CLK_ENB,
588 .recalc = &follow_parent,
589};
590
591/* ssp2 clock */
592static struct clk ssp2_clk = {
593 .pclk = &apb_clk,
594 .en_reg = PERIP1_CLK_ENB,
595 .en_reg_bit = SSP2_CLK_ENB,
596 .recalc = &follow_parent,
597};
598
599/* gpio0 ARM subsystem clock */
600static struct clk gpio0_clk = {
601 .flags = ALWAYS_ENABLED,
602 .pclk = &apb_clk,
603 .recalc = &follow_parent,
604};
605
606/* gpio1 clock */
607static struct clk gpio1_clk = {
608 .pclk = &apb_clk,
609 .en_reg = PERIP1_CLK_ENB,
610 .en_reg_bit = GPIO1_CLK_ENB,
611 .recalc = &follow_parent,
612};
613
614/* gpio2 clock */
615static struct clk gpio2_clk = {
616 .pclk = &apb_clk,
617 .en_reg = PERIP1_CLK_ENB,
618 .en_reg_bit = GPIO2_CLK_ENB,
619 .recalc = &follow_parent,
620};
621
622static struct clk dummy_apb_pclk;
623
624/* array of all spear 6xx clock lookups */
625static struct clk_lookup spear_clk_lookups[] = {
626 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
627 /* root clks */
628 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
629 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
630 /* clock derived from 32 KHz os clk */
631 { .dev_id = "rtc-spear", .clk = &rtc_clk},
632 /* clock derived from 30 MHz os clk */
633 { .con_id = "pll1_clk", .clk = &pll1_clk},
634 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
635 { .dev_id = "wdt", .clk = &wdt_clk},
636 /* clock derived from pll1 clk */
637 { .con_id = "cpu_clk", .clk = &cpu_clk},
638 { .con_id = "ahb_clk", .clk = &ahb_clk},
639 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
640 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
641 { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
642 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
643 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
644 { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
645 { .dev_id = "d0000000.serial", .clk = &uart0_clk},
646 { .dev_id = "d0080000.serial", .clk = &uart1_clk},
647 { .dev_id = "firda", .clk = &firda_clk},
648 { .dev_id = "clcd", .clk = &clcd_clk},
649 { .dev_id = "gpt0", .clk = &gpt0_clk},
650 { .dev_id = "gpt1", .clk = &gpt1_clk},
651 { .dev_id = "gpt2", .clk = &gpt2_clk},
652 { .dev_id = "gpt3", .clk = &gpt3_clk},
653 /* clock derived from pll3 clk */
654 { .dev_id = "designware_udc", .clk = &usbd_clk},
655 { .con_id = "usbh.0_clk", .clk = &usbh0_clk},
656 { .con_id = "usbh.1_clk", .clk = &usbh1_clk},
657 /* clock derived from ahb clk */
658 { .con_id = "apb_clk", .clk = &apb_clk},
659 { .dev_id = "d0200000.i2c", .clk = &i2c_clk},
660 { .dev_id = "dma", .clk = &dma_clk},
661 { .dev_id = "jpeg", .clk = &jpeg_clk},
662 { .dev_id = "gmac", .clk = &gmac_clk},
663 { .dev_id = "smi", .clk = &smi_clk},
664 { .dev_id = "fsmc-nand", .clk = &fsmc_clk},
665 /* clock derived from apb clk */
666 { .dev_id = "adc", .clk = &adc_clk},
667 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
668 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
669 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
670 { .dev_id = "f0100000.gpio", .clk = &gpio0_clk},
671 { .dev_id = "fc980000.gpio", .clk = &gpio1_clk},
672 { .dev_id = "d8100000.gpio", .clk = &gpio2_clk},
673};
674
675void __init spear6xx_clk_init(void)
676{
677 int i;
678
679 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
680 clk_register(&spear_clk_lookups[i]);
681
682 clk_init();
683}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/amba/bus.h>
20#include <asm/mach/time.h>
21#include <asm/mach/map.h>
22
23/*
24 * Each GPT has 2 timer channels
25 * Following GPT channels will be used as clock source and clockevent
26 */
27#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
28#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
29#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
30
31/* Add spear6xx family device structure declarations here */
32extern struct amba_device gpio_device[];
33extern struct amba_device uart_device[];
34extern struct sys_timer spear6xx_timer;
35
36/* Add spear6xx family function declarations here */
37void __init spear_setup_timer(void);
38void __init spear6xx_map_io(void);
39void __init spear6xx_init_irq(void);
40void __init spear6xx_init(void);
41void __init spear600_init(void);
42void __init spear6xx_clk_init(void);
43 18
19void __init spear_setup_of_timer(void);
44void spear_restart(char, const char *); 20void spear_restart(char, const char *);
45 21void __init spear6xx_clk_init(void);
46/* Add spear600 machine device structure declarations here */
47 22
48#endif /* __MACH_GENERIC_H */ 23#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear6xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr6xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
16 16
17/* IRQ definitions */ 17/* IRQ definitions */
18/* VIC 1 */ 18/* VIC 1 */
19#define IRQ_INTRCOMM_SW_IRQ 0
20#define IRQ_INTRCOMM_CPU_1 1
21#define IRQ_INTRCOMM_CPU_2 2
22#define IRQ_INTRCOMM_RAS2A11_1 3
23#define IRQ_INTRCOMM_RAS2A11_2 4
24#define IRQ_INTRCOMM_RAS2A12_1 5
25#define IRQ_INTRCOMM_RAS2A12_2 6
26#define IRQ_GEN_RAS_0 7
27#define IRQ_GEN_RAS_1 8
28#define IRQ_GEN_RAS_2 9
29#define IRQ_GEN_RAS_3 10
30#define IRQ_GEN_RAS_4 11
31#define IRQ_GEN_RAS_5 12
32#define IRQ_GEN_RAS_6 13
33#define IRQ_GEN_RAS_7 14
34#define IRQ_GEN_RAS_8 15
35#define IRQ_CPU_GPT1_1 16
36#define IRQ_CPU_GPT1_2 17
37#define IRQ_LOCAL_GPIO 18
38#define IRQ_PLL_UNLOCK 19
39#define IRQ_JPEG 20
40#define IRQ_FSMC 21
41#define IRQ_IRDA 22
42#define IRQ_RESERVED 23
43#define IRQ_UART_0 24
44#define IRQ_UART_1 25
45#define IRQ_SSP_1 26
46#define IRQ_SSP_2 27
47#define IRQ_I2C 28
48#define IRQ_GEN_RAS_9 29
49#define IRQ_GEN_RAS_10 30
50#define IRQ_GEN_RAS_11 31
51
52/* VIC 2 */
53#define IRQ_APPL_GPT1_1 32
54#define IRQ_APPL_GPT1_2 33
55#define IRQ_APPL_GPT2_1 34
56#define IRQ_APPL_GPT2_2 35
57#define IRQ_APPL_GPIO 36
58#define IRQ_APPL_SSP 37
59#define IRQ_APPL_ADC 38
60#define IRQ_APPL_RESERVED 39
61#define IRQ_AHB_EXP_MASTER 40
62#define IRQ_DDR_CONTROLLER 41
63#define IRQ_BASIC_DMA 42
64#define IRQ_BASIC_RESERVED1 43
65#define IRQ_BASIC_SMI 44
66#define IRQ_BASIC_CLCD 45
67#define IRQ_EXP_AHB_1 46
68#define IRQ_EXP_AHB_2 47
69#define IRQ_BASIC_GPT1_1 48
70#define IRQ_BASIC_GPT1_2 49
71#define IRQ_BASIC_RTC 50
72#define IRQ_BASIC_GPIO 51
73#define IRQ_BASIC_WDT 52
74#define IRQ_BASIC_RESERVED 53
75#define IRQ_AHB_EXP_SLAVE 54
76#define IRQ_GMAC_1 55
77#define IRQ_GMAC_2 56
78#define IRQ_USB_DEV 57
79#define IRQ_USB_H_OHCI_0 58
80#define IRQ_USB_H_EHCI_0 59
81#define IRQ_USB_H_OHCI_1 60
82#define IRQ_USB_H_EHCI_1 61
83#define IRQ_EXP_AHB_3 62
84#define IRQ_EXP_AHB_4 63
85
86#define IRQ_VIC_END 64 19#define IRQ_VIC_END 64
87 20
88/* GPIO pins virtual irqs */ 21/* GPIO pins virtual irqs */
89#define SPEAR_GPIO_INT_BASE IRQ_VIC_END 22#define VIRTUAL_IRQS 24
90#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE 23#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
91#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
92#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
93#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
94#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
95#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
96 24
97#endif /* __MACH_IRQS_H */ 25#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,9 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h> 17#include <mach/spear.h>
18 18
19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
20
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define CLCD_CLK_SHIFT 2
59#define CLCD_CLK_MASK 0x3
60#define UART_CLK_SHIFT 4
61#define UART_CLK_MASK 0x1
62#define FIRDA_CLK_SHIFT 5
63#define FIRDA_CLK_MASK 0x3
64#define GPT0_CLK_SHIFT 8
65#define GPT1_CLK_SHIFT 10
66#define GPT2_CLK_SHIFT 11
67#define GPT3_CLK_SHIFT 12
68#define GPT_CLK_MASK 0x1
69#define AUX_CLK_PLL3_VAL 0
70#define AUX_CLK_PLL1_VAL 1
71
72#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
73/* PERIP1_CLK_ENB register masks */
74#define UART0_CLK_ENB 3
75#define UART1_CLK_ENB 4
76#define SSP0_CLK_ENB 5
77#define SSP1_CLK_ENB 6
78#define I2C_CLK_ENB 7
79#define JPEG_CLK_ENB 8
80#define FSMC_CLK_ENB 9
81#define FIRDA_CLK_ENB 10
82#define GPT2_CLK_ENB 11
83#define GPT3_CLK_ENB 12
84#define GPIO2_CLK_ENB 13
85#define SSP2_CLK_ENB 14
86#define ADC_CLK_ENB 15
87#define GPT1_CLK_ENB 11
88#define RTC_CLK_ENB 17
89#define GPIO1_CLK_ENB 18
90#define DMA_CLK_ENB 19
91#define SMI_CLK_ENB 21
92#define CLCD_CLK_ENB 22
93#define GMAC_CLK_ENB 23
94#define USBD_CLK_ENB 24
95#define USBH0_CLK_ENB 25
96#define USBH1_CLK_ENB 26
97
98#define SOC_CORE_ID (MISC_BASE + 0x030)
99#define RAS_CLK_ENB (MISC_BASE + 0x034)
100#define PERIP1_SOF_RST (MISC_BASE + 0x038)
101/* PERIP1_SOF_RST register masks */
102#define JPEG_SOF_RST 8
103
104#define SOC_USER_ID (MISC_BASE + 0x03C)
105#define RAS_SOF_RST (MISC_BASE + 0x040)
106#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
107#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
108#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
109/* gpt synthesizer register masks */
110#define GPT_MSCALE_SHIFT 0
111#define GPT_MSCALE_MASK 0xFFF
112#define GPT_NSCALE_SHIFT 12
113#define GPT_NSCALE_MASK 0xF
114
115#define AMEM_CLK_CFG (MISC_BASE + 0x050)
116#define EXPI_CLK_CFG (MISC_BASE + 0x054)
117#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
118#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
119#define UART_CLK_SYNT (MISC_BASE + 0x064)
120#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
121#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
122#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
123#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
124#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
125/* aux clk synthesiser register masks for irda to ras4 */
126#define AUX_SYNT_ENB 31
127#define AUX_EQ_SEL_SHIFT 30
128#define AUX_EQ_SEL_MASK 1
129#define AUX_EQ1_SEL 0
130#define AUX_EQ2_SEL 1
131#define AUX_XSCALE_SHIFT 16
132#define AUX_XSCALE_MASK 0xFFF
133#define AUX_YSCALE_SHIFT 0
134#define AUX_YSCALE_MASK 0xFFF
135
136#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
137#define ICM2_ARB_CFG (MISC_BASE + 0x080)
138#define ICM3_ARB_CFG (MISC_BASE + 0x084)
139#define ICM4_ARB_CFG (MISC_BASE + 0x088)
140#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
141#define ICM6_ARB_CFG (MISC_BASE + 0x090)
142#define ICM7_ARB_CFG (MISC_BASE + 0x094)
143#define ICM8_ARB_CFG (MISC_BASE + 0x098)
144#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
145#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
146#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
147#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
148#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
149#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
150#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
151#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
152#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
153#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
154#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
155#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
156#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
157#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
158#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
159#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
160#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
161#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
162#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
163#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
164#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
165#define BIST4_CFG_CTR (MISC_BASE + 0x100)
166#define BIST5_CFG_CTR (MISC_BASE + 0x104)
167#define BIST1_STS_RES (MISC_BASE + 0x108)
168#define BIST2_STS_RES (MISC_BASE + 0x10C)
169#define BIST3_STS_RES (MISC_BASE + 0x110)
170#define BIST4_STS_RES (MISC_BASE + 0x114)
171#define BIST5_STS_RES (MISC_BASE + 0x118)
172#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
173 21
174#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
15#define __MACH_SPEAR6XX_H 15#define __MACH_SPEAR6XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear600.h>
19 18
20#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
21/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
22#define SPEAR6XX_ICM1_BASE UL(0xD0000000) 20#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
23 21#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
24#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) 22#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
25#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) 23#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
26
27#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
28#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
29#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
30#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
31#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
32#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
33#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
34#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
35#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
36
37/* ICM2 - Application Subsystem */
38#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
39#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
40#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
41#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
42#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
43#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
44 24
45/* ML-1, 2 - Multi Layer CPU Subsystem */ 25/* ML-1, 2 - Multi Layer CPU Subsystem */
46#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 26#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
47#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) 27#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
48#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
49#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
50#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
51#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
52#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
53 28
54/* ICM3 - Basic Subsystem */ 29/* ICM3 - Basic Subsystem */
55#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
56#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
57#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 30#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
58#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) 31#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
59#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) 32#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
60#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
61#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
62#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
63#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
64#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
65#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 33#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
66#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) 34#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
67#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 35#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
68#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) 36#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
69
70/* ICM4 - High Speed Connection */
71#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
72#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
73#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
74#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
75#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
76#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
77#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
78#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
79#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
80#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
81 37
82/* Debug uart for linux, will be used for debug and uncompress messages */ 38/* Debug uart for linux, will be used for debug and uncompress messages */
83#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE 39#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-spear66xx/include/mach/spear600.h
3 *
4 * SPEAr600 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR600
15
16#ifndef __MACH_SPEAR600_H
17#define __MACH_SPEAR600_H
18
19#endif /* __MACH_SPEAR600_H */
20
21#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h>
17#include <linux/clk.h>
18#include <linux/err.h>
16#include <linux/of.h> 19#include <linux/of.h>
17#include <linux/of_address.h> 20#include <linux/of_address.h>
18#include <linux/of_irq.h> 21#include <linux/of_irq.h>
19#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <asm/hardware/pl080.h>
20#include <asm/hardware/vic.h> 24#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28#include <plat/pl080.h>
22#include <mach/generic.h> 29#include <mach/generic.h>
23#include <mach/hardware.h> 30#include <mach/spear.h>
24 31
25/* Following will create static virtual/physical mappings */ 32/* dmac device registration */
26static struct map_desc spear6xx_io_desc[] __initdata = { 33static struct pl08x_channel_data spear600_dma_info[] = {
27 { 34 {
28 .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, 35 .bus_id = "ssp1_rx",
29 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), 36 .min_signal = 0,
30 .length = SZ_4K, 37 .max_signal = 0,
31 .type = MT_DEVICE 38 .muxval = 0,
39 .cctl = 0,
40 .periph_buses = PL08X_AHB1,
32 }, { 41 }, {
33 .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, 42 .bus_id = "ssp1_tx",
34 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), 43 .min_signal = 1,
35 .length = SZ_4K, 44 .max_signal = 1,
36 .type = MT_DEVICE 45 .muxval = 0,
46 .cctl = 0,
47 .periph_buses = PL08X_AHB1,
37 }, { 48 }, {
38 .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, 49 .bus_id = "uart0_rx",
39 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), 50 .min_signal = 2,
40 .length = SZ_4K, 51 .max_signal = 2,
41 .type = MT_DEVICE 52 .muxval = 0,
53 .cctl = 0,
54 .periph_buses = PL08X_AHB1,
55 }, {
56 .bus_id = "uart0_tx",
57 .min_signal = 3,
58 .max_signal = 3,
59 .muxval = 0,
60 .cctl = 0,
61 .periph_buses = PL08X_AHB1,
62 }, {
63 .bus_id = "uart1_rx",
64 .min_signal = 4,
65 .max_signal = 4,
66 .muxval = 0,
67 .cctl = 0,
68 .periph_buses = PL08X_AHB1,
69 }, {
70 .bus_id = "uart1_tx",
71 .min_signal = 5,
72 .max_signal = 5,
73 .muxval = 0,
74 .cctl = 0,
75 .periph_buses = PL08X_AHB1,
76 }, {
77 .bus_id = "ssp2_rx",
78 .min_signal = 6,
79 .max_signal = 6,
80 .muxval = 0,
81 .cctl = 0,
82 .periph_buses = PL08X_AHB2,
83 }, {
84 .bus_id = "ssp2_tx",
85 .min_signal = 7,
86 .max_signal = 7,
87 .muxval = 0,
88 .cctl = 0,
89 .periph_buses = PL08X_AHB2,
90 }, {
91 .bus_id = "ssp0_rx",
92 .min_signal = 8,
93 .max_signal = 8,
94 .muxval = 0,
95 .cctl = 0,
96 .periph_buses = PL08X_AHB1,
97 }, {
98 .bus_id = "ssp0_tx",
99 .min_signal = 9,
100 .max_signal = 9,
101 .muxval = 0,
102 .cctl = 0,
103 .periph_buses = PL08X_AHB1,
104 }, {
105 .bus_id = "i2c_rx",
106 .min_signal = 10,
107 .max_signal = 10,
108 .muxval = 0,
109 .cctl = 0,
110 .periph_buses = PL08X_AHB1,
111 }, {
112 .bus_id = "i2c_tx",
113 .min_signal = 11,
114 .max_signal = 11,
115 .muxval = 0,
116 .cctl = 0,
117 .periph_buses = PL08X_AHB1,
118 }, {
119 .bus_id = "irda",
120 .min_signal = 12,
121 .max_signal = 12,
122 .muxval = 0,
123 .cctl = 0,
124 .periph_buses = PL08X_AHB1,
125 }, {
126 .bus_id = "adc",
127 .min_signal = 13,
128 .max_signal = 13,
129 .muxval = 0,
130 .cctl = 0,
131 .periph_buses = PL08X_AHB2,
132 }, {
133 .bus_id = "to_jpeg",
134 .min_signal = 14,
135 .max_signal = 14,
136 .muxval = 0,
137 .cctl = 0,
138 .periph_buses = PL08X_AHB1,
139 }, {
140 .bus_id = "from_jpeg",
141 .min_signal = 15,
142 .max_signal = 15,
143 .muxval = 0,
144 .cctl = 0,
145 .periph_buses = PL08X_AHB1,
146 }, {
147 .bus_id = "ras0_rx",
148 .min_signal = 0,
149 .max_signal = 0,
150 .muxval = 1,
151 .cctl = 0,
152 .periph_buses = PL08X_AHB1,
153 }, {
154 .bus_id = "ras0_tx",
155 .min_signal = 1,
156 .max_signal = 1,
157 .muxval = 1,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "ras1_rx",
162 .min_signal = 2,
163 .max_signal = 2,
164 .muxval = 1,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "ras1_tx",
169 .min_signal = 3,
170 .max_signal = 3,
171 .muxval = 1,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "ras2_rx",
176 .min_signal = 4,
177 .max_signal = 4,
178 .muxval = 1,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "ras2_tx",
183 .min_signal = 5,
184 .max_signal = 5,
185 .muxval = 1,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "ras3_rx",
190 .min_signal = 6,
191 .max_signal = 6,
192 .muxval = 1,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "ras3_tx",
197 .min_signal = 7,
198 .max_signal = 7,
199 .muxval = 1,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "ras4_rx",
204 .min_signal = 8,
205 .max_signal = 8,
206 .muxval = 1,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "ras4_tx",
211 .min_signal = 9,
212 .max_signal = 9,
213 .muxval = 1,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "ras5_rx",
218 .min_signal = 10,
219 .max_signal = 10,
220 .muxval = 1,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ras5_tx",
225 .min_signal = 11,
226 .max_signal = 11,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB1,
230 }, {
231 .bus_id = "ras6_rx",
232 .min_signal = 12,
233 .max_signal = 12,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB1,
237 }, {
238 .bus_id = "ras6_tx",
239 .min_signal = 13,
240 .max_signal = 13,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB1,
244 }, {
245 .bus_id = "ras7_rx",
246 .min_signal = 14,
247 .max_signal = 14,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB1,
251 }, {
252 .bus_id = "ras7_tx",
253 .min_signal = 15,
254 .max_signal = 15,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB1,
42 }, { 258 }, {
43 .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, 259 .bus_id = "ext0_rx",
44 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), 260 .min_signal = 0,
45 .length = SZ_4K, 261 .max_signal = 0,
262 .muxval = 2,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB2,
265 }, {
266 .bus_id = "ext0_tx",
267 .min_signal = 1,
268 .max_signal = 1,
269 .muxval = 2,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB2,
272 }, {
273 .bus_id = "ext1_rx",
274 .min_signal = 2,
275 .max_signal = 2,
276 .muxval = 2,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB2,
279 }, {
280 .bus_id = "ext1_tx",
281 .min_signal = 3,
282 .max_signal = 3,
283 .muxval = 2,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB2,
286 }, {
287 .bus_id = "ext2_rx",
288 .min_signal = 4,
289 .max_signal = 4,
290 .muxval = 2,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB2,
293 }, {
294 .bus_id = "ext2_tx",
295 .min_signal = 5,
296 .max_signal = 5,
297 .muxval = 2,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB2,
300 }, {
301 .bus_id = "ext3_rx",
302 .min_signal = 6,
303 .max_signal = 6,
304 .muxval = 2,
305 .cctl = 0,
306 .periph_buses = PL08X_AHB2,
307 }, {
308 .bus_id = "ext3_tx",
309 .min_signal = 7,
310 .max_signal = 7,
311 .muxval = 2,
312 .cctl = 0,
313 .periph_buses = PL08X_AHB2,
314 }, {
315 .bus_id = "ext4_rx",
316 .min_signal = 8,
317 .max_signal = 8,
318 .muxval = 2,
319 .cctl = 0,
320 .periph_buses = PL08X_AHB2,
321 }, {
322 .bus_id = "ext4_tx",
323 .min_signal = 9,
324 .max_signal = 9,
325 .muxval = 2,
326 .cctl = 0,
327 .periph_buses = PL08X_AHB2,
328 }, {
329 .bus_id = "ext5_rx",
330 .min_signal = 10,
331 .max_signal = 10,
332 .muxval = 2,
333 .cctl = 0,
334 .periph_buses = PL08X_AHB2,
335 }, {
336 .bus_id = "ext5_tx",
337 .min_signal = 11,
338 .max_signal = 11,
339 .muxval = 2,
340 .cctl = 0,
341 .periph_buses = PL08X_AHB2,
342 }, {
343 .bus_id = "ext6_rx",
344 .min_signal = 12,
345 .max_signal = 12,
346 .muxval = 2,
347 .cctl = 0,
348 .periph_buses = PL08X_AHB2,
349 }, {
350 .bus_id = "ext6_tx",
351 .min_signal = 13,
352 .max_signal = 13,
353 .muxval = 2,
354 .cctl = 0,
355 .periph_buses = PL08X_AHB2,
356 }, {
357 .bus_id = "ext7_rx",
358 .min_signal = 14,
359 .max_signal = 14,
360 .muxval = 2,
361 .cctl = 0,
362 .periph_buses = PL08X_AHB2,
363 }, {
364 .bus_id = "ext7_tx",
365 .min_signal = 15,
366 .max_signal = 15,
367 .muxval = 2,
368 .cctl = 0,
369 .periph_buses = PL08X_AHB2,
370 },
371};
372
373struct pl08x_platform_data pl080_plat_data = {
374 .memcpy_channel = {
375 .bus_id = "memcpy",
376 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
377 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
378 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
379 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
380 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
381 PL080_CONTROL_PROT_SYS),
382 },
383 .lli_buses = PL08X_AHB1,
384 .mem_buses = PL08X_AHB1,
385 .get_signal = pl080_get_signal,
386 .put_signal = pl080_put_signal,
387 .slave_channels = spear600_dma_info,
388 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
389};
390
391/*
392 * Following will create 16MB static virtual/physical mappings
393 * PHYSICAL VIRTUAL
394 * 0xF0000000 0xF0000000
395 * 0xF1000000 0xF1000000
396 * 0xD0000000 0xFD000000
397 * 0xFC000000 0xFC000000
398 */
399struct map_desc spear6xx_io_desc[] __initdata = {
400 {
401 .virtual = VA_SPEAR6XX_ML_CPU_BASE,
402 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
403 .length = 2 * SZ_16M,
404 .type = MT_DEVICE
405 }, {
406 .virtual = VA_SPEAR6XX_ICM1_BASE,
407 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
408 .length = SZ_16M,
46 .type = MT_DEVICE 409 .type = MT_DEVICE
47 }, { 410 }, {
48 .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, 411 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
49 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), 412 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
50 .length = SZ_4K, 413 .length = SZ_16M,
51 .type = MT_DEVICE 414 .type = MT_DEVICE
52 }, 415 },
53}; 416};
@@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
56void __init spear6xx_map_io(void) 419void __init spear6xx_map_io(void)
57{ 420{
58 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
59
60 /* This will initialize clock framework */
61 spear6xx_clk_init();
62} 422}
63 423
64static void __init spear6xx_timer_init(void) 424static void __init spear6xx_timer_init(void)
@@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void)
66 char pclk_name[] = "pll3_48m_clk"; 426 char pclk_name[] = "pll3_48m_clk";
67 struct clk *gpt_clk, *pclk; 427 struct clk *gpt_clk, *pclk;
68 428
429 spear6xx_clk_init();
430
69 /* get the system timer clock */ 431 /* get the system timer clock */
70 gpt_clk = clk_get_sys("gpt0", NULL); 432 gpt_clk = clk_get_sys("gpt0", NULL);
71 if (IS_ERR(gpt_clk)) { 433 if (IS_ERR(gpt_clk)) {
@@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void)
85 clk_put(gpt_clk); 447 clk_put(gpt_clk);
86 clk_put(pclk); 448 clk_put(pclk);
87 449
88 spear_setup_timer(); 450 spear_setup_of_timer();
89} 451}
90 452
91struct sys_timer spear6xx_timer = { 453struct sys_timer spear6xx_timer = {
92 .init = spear6xx_timer_init, 454 .init = spear6xx_timer_init,
93}; 455};
94 456
457/* Add auxdata to pass platform data */
458struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
459 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
460 &pl080_plat_data),
461 {}
462};
463
95static void __init spear600_dt_init(void) 464static void __init spear600_dt_init(void)
96{ 465{
97 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 466 of_platform_populate(NULL, of_default_bus_match_table,
467 spear6xx_auxdata_lookup, NULL);
98} 468}
99 469
100static const char *spear600_dt_board_compat[] = { 470static const char *spear600_dt_board_compat[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 03:40:17 -0500