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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-26 15:42:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-26 15:42:29 -0400
commit27953437059c64d14086196eb96f43c78caa9db3 (patch)
tree0cfd5fb21262a6db3de0c64462847b4c0c43e9df /arch/arm/mach-spear6xx
parent2c757fd5d1a92086f225a75a8fac7cab242d11b0 (diff)
parent3c0dec5f58b3c7b3627715126d1bf9b030a076f0 (diff)
Merge tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc clock driver changes from Olof Johansson: "The new clock subsystem was merged in linux-3.4 without any users, this now moves the first three platforms over to it: imx, mxs and spear. The series also contains the changes for the clock subsystem itself, since Mike preferred to have it together with the platforms that require these changes, in order to avoid interdependencies and conflicts." Fix up trivial conflicts in arch/arm/mach-kirkwood/common.c (code removed in one branch, added OF support in another) and drivers/dma/imx-sdma.c (independent changes next to each other). * tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate(). clk: Provide dummy clk_unregister() SPEAr: Update defconfigs SPEAr: Add SMI NOR partition info in dts files SPEAr: Switch to common clock framework SPEAr: Call clk_prepare() before calling clk_enable SPEAr: clk: Add General Purpose Timer Synthesizer clock SPEAr: clk: Add Fractional Synthesizer clock SPEAr: clk: Add Auxiliary Synthesizer clock SPEAr: clk: Add VCO-PLL Synthesizer clock SPEAr: Add DT bindings for SPEAr's timer ARM i.MX: remove now unused clock files ARM: i.MX6: implement clocks using common clock framework ARM i.MX35: implement clocks using common clock framework ARM i.MX5: implement clocks using common clock framework ARM: Kirkwood: Replace clock gating ARM: Orion: Audio: Add clk/clkdev support ARM: Orion: PCIE: Add support for clk ARM: Orion: XOR: Add support for clk ARM: Orion: CESA: Add support for clk ...
Diffstat (limited to 'arch/arm/mach-spear6xx')
-rw-r--r--arch/arm/mach-spear6xx/Makefile2
-rw-r--r--arch/arm/mach-spear6xx/clock.c789
-rw-r--r--arch/arm/mach-spear6xx/include/mach/generic.h2
-rw-r--r--arch/arm/mach-spear6xx/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h1
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c7
7 files changed, 7 insertions, 799 deletions
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += clock.o spear6xx.o 6obj-y += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index bef77d43db87..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,789 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/clock.c
3 *
4 * SPEAr6xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <plat/clock.h>
18#include <mach/misc_regs.h>
19#include <mach/spear.h>
20
21#define PLL1_CTR (MISC_BASE + 0x008)
22#define PLL1_FRQ (MISC_BASE + 0x00C)
23#define PLL1_MOD (MISC_BASE + 0x010)
24#define PLL2_CTR (MISC_BASE + 0x014)
25/* PLL_CTR register masks */
26#define PLL_ENABLE 2
27#define PLL_MODE_SHIFT 4
28#define PLL_MODE_MASK 0x3
29#define PLL_MODE_NORMAL 0
30#define PLL_MODE_FRACTION 1
31#define PLL_MODE_DITH_DSB 2
32#define PLL_MODE_DITH_SSB 3
33
34#define PLL2_FRQ (MISC_BASE + 0x018)
35/* PLL FRQ register masks */
36#define PLL_DIV_N_SHIFT 0
37#define PLL_DIV_N_MASK 0xFF
38#define PLL_DIV_P_SHIFT 8
39#define PLL_DIV_P_MASK 0x7
40#define PLL_NORM_FDBK_M_SHIFT 24
41#define PLL_NORM_FDBK_M_MASK 0xFF
42#define PLL_DITH_FDBK_M_SHIFT 16
43#define PLL_DITH_FDBK_M_MASK 0xFFFF
44
45#define PLL2_MOD (MISC_BASE + 0x01C)
46#define PLL_CLK_CFG (MISC_BASE + 0x020)
47#define CORE_CLK_CFG (MISC_BASE + 0x024)
48/* CORE CLK CFG register masks */
49#define PLL_HCLK_RATIO_SHIFT 10
50#define PLL_HCLK_RATIO_MASK 0x3
51#define HCLK_PCLK_RATIO_SHIFT 8
52#define HCLK_PCLK_RATIO_MASK 0x3
53
54#define PERIP_CLK_CFG (MISC_BASE + 0x028)
55/* PERIP_CLK_CFG register masks */
56#define CLCD_CLK_SHIFT 2
57#define CLCD_CLK_MASK 0x3
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 10
64#define GPT2_CLK_SHIFT 11
65#define GPT3_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART0_CLK_ENB 3
73#define UART1_CLK_ENB 4
74#define SSP0_CLK_ENB 5
75#define SSP1_CLK_ENB 6
76#define I2C_CLK_ENB 7
77#define JPEG_CLK_ENB 8
78#define FSMC_CLK_ENB 9
79#define FIRDA_CLK_ENB 10
80#define GPT2_CLK_ENB 11
81#define GPT3_CLK_ENB 12
82#define GPIO2_CLK_ENB 13
83#define SSP2_CLK_ENB 14
84#define ADC_CLK_ENB 15
85#define GPT1_CLK_ENB 11
86#define RTC_CLK_ENB 17
87#define GPIO1_CLK_ENB 18
88#define DMA_CLK_ENB 19
89#define SMI_CLK_ENB 21
90#define CLCD_CLK_ENB 22
91#define GMAC_CLK_ENB 23
92#define USBD_CLK_ENB 24
93#define USBH0_CLK_ENB 25
94#define USBH1_CLK_ENB 26
95
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126/* root clks */
127/* 32 KHz oscillator clock */
128static struct clk osc_32k_clk = {
129 .flags = ALWAYS_ENABLED,
130 .rate = 32000,
131};
132
133/* 30 MHz oscillator clock */
134static struct clk osc_30m_clk = {
135 .flags = ALWAYS_ENABLED,
136 .rate = 30000000,
137};
138
139/* clock derived from 32 KHz osc clk */
140/* rtc clock */
141static struct clk rtc_clk = {
142 .pclk = &osc_32k_clk,
143 .en_reg = PERIP1_CLK_ENB,
144 .en_reg_bit = RTC_CLK_ENB,
145 .recalc = &follow_parent,
146};
147
148/* clock derived from 30 MHz osc clk */
149/* pll masks structure */
150static struct pll_clk_masks pll1_masks = {
151 .mode_mask = PLL_MODE_MASK,
152 .mode_shift = PLL_MODE_SHIFT,
153 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
154 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
155 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
156 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
157 .div_p_mask = PLL_DIV_P_MASK,
158 .div_p_shift = PLL_DIV_P_SHIFT,
159 .div_n_mask = PLL_DIV_N_MASK,
160 .div_n_shift = PLL_DIV_N_SHIFT,
161};
162
163/* pll1 configuration structure */
164static struct pll_clk_config pll1_config = {
165 .mode_reg = PLL1_CTR,
166 .cfg_reg = PLL1_FRQ,
167 .masks = &pll1_masks,
168};
169
170/* pll rate configuration table, in ascending order of rates */
171struct pll_rate_tbl pll_rtbl[] = {
172 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
173 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
174};
175
176/* PLL1 clock */
177static struct clk pll1_clk = {
178 .flags = ENABLED_ON_INIT,
179 .pclk = &osc_30m_clk,
180 .en_reg = PLL1_CTR,
181 .en_reg_bit = PLL_ENABLE,
182 .calc_rate = &pll_calc_rate,
183 .recalc = &pll_clk_recalc,
184 .set_rate = &pll_clk_set_rate,
185 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
186 .private_data = &pll1_config,
187};
188
189/* PLL3 48 MHz clock */
190static struct clk pll3_48m_clk = {
191 .flags = ALWAYS_ENABLED,
192 .pclk = &osc_30m_clk,
193 .rate = 48000000,
194};
195
196/* watch dog timer clock */
197static struct clk wdt_clk = {
198 .flags = ALWAYS_ENABLED,
199 .pclk = &osc_30m_clk,
200 .recalc = &follow_parent,
201};
202
203/* clock derived from pll1 clk */
204/* cpu clock */
205static struct clk cpu_clk = {
206 .flags = ALWAYS_ENABLED,
207 .pclk = &pll1_clk,
208 .recalc = &follow_parent,
209};
210
211/* ahb masks structure */
212static struct bus_clk_masks ahb_masks = {
213 .mask = PLL_HCLK_RATIO_MASK,
214 .shift = PLL_HCLK_RATIO_SHIFT,
215};
216
217/* ahb configuration structure */
218static struct bus_clk_config ahb_config = {
219 .reg = CORE_CLK_CFG,
220 .masks = &ahb_masks,
221};
222
223/* ahb rate configuration table, in ascending order of rates */
224struct bus_rate_tbl bus_rtbl[] = {
225 {.div = 3}, /* == parent divided by 4 */
226 {.div = 2}, /* == parent divided by 3 */
227 {.div = 1}, /* == parent divided by 2 */
228 {.div = 0}, /* == parent divided by 1 */
229};
230
231/* ahb clock */
232static struct clk ahb_clk = {
233 .flags = ALWAYS_ENABLED,
234 .pclk = &pll1_clk,
235 .calc_rate = &bus_calc_rate,
236 .recalc = &bus_clk_recalc,
237 .set_rate = &bus_clk_set_rate,
238 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
239 .private_data = &ahb_config,
240};
241
242/* auxiliary synthesizers masks */
243static struct aux_clk_masks aux_masks = {
244 .eq_sel_mask = AUX_EQ_SEL_MASK,
245 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
246 .eq1_mask = AUX_EQ1_SEL,
247 .eq2_mask = AUX_EQ2_SEL,
248 .xscale_sel_mask = AUX_XSCALE_MASK,
249 .xscale_sel_shift = AUX_XSCALE_SHIFT,
250 .yscale_sel_mask = AUX_YSCALE_MASK,
251 .yscale_sel_shift = AUX_YSCALE_SHIFT,
252};
253
254/* uart configurations */
255static struct aux_clk_config uart_synth_config = {
256 .synth_reg = UART_CLK_SYNT,
257 .masks = &aux_masks,
258};
259
260/* aux rate configuration table, in ascending order of rates */
261struct aux_rate_tbl aux_rtbl[] = {
262 /* For PLL1 = 332 MHz */
263 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
264 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
265 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
266};
267
268/* uart synth clock */
269static struct clk uart_synth_clk = {
270 .en_reg = UART_CLK_SYNT,
271 .en_reg_bit = AUX_SYNT_ENB,
272 .pclk = &pll1_clk,
273 .calc_rate = &aux_calc_rate,
274 .recalc = &aux_clk_recalc,
275 .set_rate = &aux_clk_set_rate,
276 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
277 .private_data = &uart_synth_config,
278};
279
280/* uart parents */
281static struct pclk_info uart_pclk_info[] = {
282 {
283 .pclk = &uart_synth_clk,
284 .pclk_val = AUX_CLK_PLL1_VAL,
285 }, {
286 .pclk = &pll3_48m_clk,
287 .pclk_val = AUX_CLK_PLL3_VAL,
288 },
289};
290
291/* uart parent select structure */
292static struct pclk_sel uart_pclk_sel = {
293 .pclk_info = uart_pclk_info,
294 .pclk_count = ARRAY_SIZE(uart_pclk_info),
295 .pclk_sel_reg = PERIP_CLK_CFG,
296 .pclk_sel_mask = UART_CLK_MASK,
297};
298
299/* uart0 clock */
300static struct clk uart0_clk = {
301 .en_reg = PERIP1_CLK_ENB,
302 .en_reg_bit = UART0_CLK_ENB,
303 .pclk_sel = &uart_pclk_sel,
304 .pclk_sel_shift = UART_CLK_SHIFT,
305 .recalc = &follow_parent,
306};
307
308/* uart1 clock */
309static struct clk uart1_clk = {
310 .en_reg = PERIP1_CLK_ENB,
311 .en_reg_bit = UART1_CLK_ENB,
312 .pclk_sel = &uart_pclk_sel,
313 .pclk_sel_shift = UART_CLK_SHIFT,
314 .recalc = &follow_parent,
315};
316
317/* firda configurations */
318static struct aux_clk_config firda_synth_config = {
319 .synth_reg = FIRDA_CLK_SYNT,
320 .masks = &aux_masks,
321};
322
323/* firda synth clock */
324static struct clk firda_synth_clk = {
325 .en_reg = FIRDA_CLK_SYNT,
326 .en_reg_bit = AUX_SYNT_ENB,
327 .pclk = &pll1_clk,
328 .calc_rate = &aux_calc_rate,
329 .recalc = &aux_clk_recalc,
330 .set_rate = &aux_clk_set_rate,
331 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
332 .private_data = &firda_synth_config,
333};
334
335/* firda parents */
336static struct pclk_info firda_pclk_info[] = {
337 {
338 .pclk = &firda_synth_clk,
339 .pclk_val = AUX_CLK_PLL1_VAL,
340 }, {
341 .pclk = &pll3_48m_clk,
342 .pclk_val = AUX_CLK_PLL3_VAL,
343 },
344};
345
346/* firda parent select structure */
347static struct pclk_sel firda_pclk_sel = {
348 .pclk_info = firda_pclk_info,
349 .pclk_count = ARRAY_SIZE(firda_pclk_info),
350 .pclk_sel_reg = PERIP_CLK_CFG,
351 .pclk_sel_mask = FIRDA_CLK_MASK,
352};
353
354/* firda clock */
355static struct clk firda_clk = {
356 .en_reg = PERIP1_CLK_ENB,
357 .en_reg_bit = FIRDA_CLK_ENB,
358 .pclk_sel = &firda_pclk_sel,
359 .pclk_sel_shift = FIRDA_CLK_SHIFT,
360 .recalc = &follow_parent,
361};
362
363/* clcd configurations */
364static struct aux_clk_config clcd_synth_config = {
365 .synth_reg = CLCD_CLK_SYNT,
366 .masks = &aux_masks,
367};
368
369/* firda synth clock */
370static struct clk clcd_synth_clk = {
371 .en_reg = CLCD_CLK_SYNT,
372 .en_reg_bit = AUX_SYNT_ENB,
373 .pclk = &pll1_clk,
374 .calc_rate = &aux_calc_rate,
375 .recalc = &aux_clk_recalc,
376 .set_rate = &aux_clk_set_rate,
377 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
378 .private_data = &clcd_synth_config,
379};
380
381/* clcd parents */
382static struct pclk_info clcd_pclk_info[] = {
383 {
384 .pclk = &clcd_synth_clk,
385 .pclk_val = AUX_CLK_PLL1_VAL,
386 }, {
387 .pclk = &pll3_48m_clk,
388 .pclk_val = AUX_CLK_PLL3_VAL,
389 },
390};
391
392/* clcd parent select structure */
393static struct pclk_sel clcd_pclk_sel = {
394 .pclk_info = clcd_pclk_info,
395 .pclk_count = ARRAY_SIZE(clcd_pclk_info),
396 .pclk_sel_reg = PERIP_CLK_CFG,
397 .pclk_sel_mask = CLCD_CLK_MASK,
398};
399
400/* clcd clock */
401static struct clk clcd_clk = {
402 .en_reg = PERIP1_CLK_ENB,
403 .en_reg_bit = CLCD_CLK_ENB,
404 .pclk_sel = &clcd_pclk_sel,
405 .pclk_sel_shift = CLCD_CLK_SHIFT,
406 .recalc = &follow_parent,
407};
408
409/* gpt synthesizer masks */
410static struct gpt_clk_masks gpt_masks = {
411 .mscale_sel_mask = GPT_MSCALE_MASK,
412 .mscale_sel_shift = GPT_MSCALE_SHIFT,
413 .nscale_sel_mask = GPT_NSCALE_MASK,
414 .nscale_sel_shift = GPT_NSCALE_SHIFT,
415};
416
417/* gpt rate configuration table, in ascending order of rates */
418struct gpt_rate_tbl gpt_rtbl[] = {
419 /* For pll1 = 332 MHz */
420 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
421 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
422 {.mscale = 1, .nscale = 0}, /* 83 MHz */
423};
424
425/* gpt0 synth clk config*/
426static struct gpt_clk_config gpt0_synth_config = {
427 .synth_reg = PRSC1_CLK_CFG,
428 .masks = &gpt_masks,
429};
430
431/* gpt synth clock */
432static struct clk gpt0_synth_clk = {
433 .flags = ALWAYS_ENABLED,
434 .pclk = &pll1_clk,
435 .calc_rate = &gpt_calc_rate,
436 .recalc = &gpt_clk_recalc,
437 .set_rate = &gpt_clk_set_rate,
438 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
439 .private_data = &gpt0_synth_config,
440};
441
442/* gpt parents */
443static struct pclk_info gpt0_pclk_info[] = {
444 {
445 .pclk = &gpt0_synth_clk,
446 .pclk_val = AUX_CLK_PLL1_VAL,
447 }, {
448 .pclk = &pll3_48m_clk,
449 .pclk_val = AUX_CLK_PLL3_VAL,
450 },
451};
452
453/* gpt parent select structure */
454static struct pclk_sel gpt0_pclk_sel = {
455 .pclk_info = gpt0_pclk_info,
456 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
457 .pclk_sel_reg = PERIP_CLK_CFG,
458 .pclk_sel_mask = GPT_CLK_MASK,
459};
460
461/* gpt0 ARM1 subsystem timer clock */
462static struct clk gpt0_clk = {
463 .flags = ALWAYS_ENABLED,
464 .pclk_sel = &gpt0_pclk_sel,
465 .pclk_sel_shift = GPT0_CLK_SHIFT,
466 .recalc = &follow_parent,
467};
468
469
470/* Note: gpt0 and gpt1 share same parent clocks */
471/* gpt parent select structure */
472static struct pclk_sel gpt1_pclk_sel = {
473 .pclk_info = gpt0_pclk_info,
474 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
475 .pclk_sel_reg = PERIP_CLK_CFG,
476 .pclk_sel_mask = GPT_CLK_MASK,
477};
478
479/* gpt1 timer clock */
480static struct clk gpt1_clk = {
481 .flags = ALWAYS_ENABLED,
482 .pclk_sel = &gpt1_pclk_sel,
483 .pclk_sel_shift = GPT1_CLK_SHIFT,
484 .recalc = &follow_parent,
485};
486
487/* gpt2 synth clk config*/
488static struct gpt_clk_config gpt2_synth_config = {
489 .synth_reg = PRSC2_CLK_CFG,
490 .masks = &gpt_masks,
491};
492
493/* gpt synth clock */
494static struct clk gpt2_synth_clk = {
495 .flags = ALWAYS_ENABLED,
496 .pclk = &pll1_clk,
497 .calc_rate = &gpt_calc_rate,
498 .recalc = &gpt_clk_recalc,
499 .set_rate = &gpt_clk_set_rate,
500 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
501 .private_data = &gpt2_synth_config,
502};
503
504/* gpt parents */
505static struct pclk_info gpt2_pclk_info[] = {
506 {
507 .pclk = &gpt2_synth_clk,
508 .pclk_val = AUX_CLK_PLL1_VAL,
509 }, {
510 .pclk = &pll3_48m_clk,
511 .pclk_val = AUX_CLK_PLL3_VAL,
512 },
513};
514
515/* gpt parent select structure */
516static struct pclk_sel gpt2_pclk_sel = {
517 .pclk_info = gpt2_pclk_info,
518 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
519 .pclk_sel_reg = PERIP_CLK_CFG,
520 .pclk_sel_mask = GPT_CLK_MASK,
521};
522
523/* gpt2 timer clock */
524static struct clk gpt2_clk = {
525 .flags = ALWAYS_ENABLED,
526 .pclk_sel = &gpt2_pclk_sel,
527 .pclk_sel_shift = GPT2_CLK_SHIFT,
528 .recalc = &follow_parent,
529};
530
531/* gpt3 synth clk config*/
532static struct gpt_clk_config gpt3_synth_config = {
533 .synth_reg = PRSC3_CLK_CFG,
534 .masks = &gpt_masks,
535};
536
537/* gpt synth clock */
538static struct clk gpt3_synth_clk = {
539 .flags = ALWAYS_ENABLED,
540 .pclk = &pll1_clk,
541 .calc_rate = &gpt_calc_rate,
542 .recalc = &gpt_clk_recalc,
543 .set_rate = &gpt_clk_set_rate,
544 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
545 .private_data = &gpt3_synth_config,
546};
547
548/* gpt parents */
549static struct pclk_info gpt3_pclk_info[] = {
550 {
551 .pclk = &gpt3_synth_clk,
552 .pclk_val = AUX_CLK_PLL1_VAL,
553 }, {
554 .pclk = &pll3_48m_clk,
555 .pclk_val = AUX_CLK_PLL3_VAL,
556 },
557};
558
559/* gpt parent select structure */
560static struct pclk_sel gpt3_pclk_sel = {
561 .pclk_info = gpt3_pclk_info,
562 .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
563 .pclk_sel_reg = PERIP_CLK_CFG,
564 .pclk_sel_mask = GPT_CLK_MASK,
565};
566
567/* gpt3 timer clock */
568static struct clk gpt3_clk = {
569 .flags = ALWAYS_ENABLED,
570 .pclk_sel = &gpt3_pclk_sel,
571 .pclk_sel_shift = GPT3_CLK_SHIFT,
572 .recalc = &follow_parent,
573};
574
575/* clock derived from pll3 clk */
576/* usbh0 clock */
577static struct clk usbh0_clk = {
578 .pclk = &pll3_48m_clk,
579 .en_reg = PERIP1_CLK_ENB,
580 .en_reg_bit = USBH0_CLK_ENB,
581 .recalc = &follow_parent,
582};
583
584/* usbh1 clock */
585static struct clk usbh1_clk = {
586 .pclk = &pll3_48m_clk,
587 .en_reg = PERIP1_CLK_ENB,
588 .en_reg_bit = USBH1_CLK_ENB,
589 .recalc = &follow_parent,
590};
591
592/* usbd clock */
593static struct clk usbd_clk = {
594 .pclk = &pll3_48m_clk,
595 .en_reg = PERIP1_CLK_ENB,
596 .en_reg_bit = USBD_CLK_ENB,
597 .recalc = &follow_parent,
598};
599
600/* clock derived from ahb clk */
601/* apb masks structure */
602static struct bus_clk_masks apb_masks = {
603 .mask = HCLK_PCLK_RATIO_MASK,
604 .shift = HCLK_PCLK_RATIO_SHIFT,
605};
606
607/* apb configuration structure */
608static struct bus_clk_config apb_config = {
609 .reg = CORE_CLK_CFG,
610 .masks = &apb_masks,
611};
612
613/* apb clock */
614static struct clk apb_clk = {
615 .flags = ALWAYS_ENABLED,
616 .pclk = &ahb_clk,
617 .calc_rate = &bus_calc_rate,
618 .recalc = &bus_clk_recalc,
619 .set_rate = &bus_clk_set_rate,
620 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
621 .private_data = &apb_config,
622};
623
624/* i2c clock */
625static struct clk i2c_clk = {
626 .pclk = &ahb_clk,
627 .en_reg = PERIP1_CLK_ENB,
628 .en_reg_bit = I2C_CLK_ENB,
629 .recalc = &follow_parent,
630};
631
632/* dma clock */
633static struct clk dma_clk = {
634 .pclk = &ahb_clk,
635 .en_reg = PERIP1_CLK_ENB,
636 .en_reg_bit = DMA_CLK_ENB,
637 .recalc = &follow_parent,
638};
639
640/* jpeg clock */
641static struct clk jpeg_clk = {
642 .pclk = &ahb_clk,
643 .en_reg = PERIP1_CLK_ENB,
644 .en_reg_bit = JPEG_CLK_ENB,
645 .recalc = &follow_parent,
646};
647
648/* gmac clock */
649static struct clk gmac_clk = {
650 .pclk = &ahb_clk,
651 .en_reg = PERIP1_CLK_ENB,
652 .en_reg_bit = GMAC_CLK_ENB,
653 .recalc = &follow_parent,
654};
655
656/* smi clock */
657static struct clk smi_clk = {
658 .pclk = &ahb_clk,
659 .en_reg = PERIP1_CLK_ENB,
660 .en_reg_bit = SMI_CLK_ENB,
661 .recalc = &follow_parent,
662};
663
664/* fsmc clock */
665static struct clk fsmc_clk = {
666 .pclk = &ahb_clk,
667 .en_reg = PERIP1_CLK_ENB,
668 .en_reg_bit = FSMC_CLK_ENB,
669 .recalc = &follow_parent,
670};
671
672/* clock derived from apb clk */
673/* adc clock */
674static struct clk adc_clk = {
675 .pclk = &apb_clk,
676 .en_reg = PERIP1_CLK_ENB,
677 .en_reg_bit = ADC_CLK_ENB,
678 .recalc = &follow_parent,
679};
680
681/* ssp0 clock */
682static struct clk ssp0_clk = {
683 .pclk = &apb_clk,
684 .en_reg = PERIP1_CLK_ENB,
685 .en_reg_bit = SSP0_CLK_ENB,
686 .recalc = &follow_parent,
687};
688
689/* ssp1 clock */
690static struct clk ssp1_clk = {
691 .pclk = &apb_clk,
692 .en_reg = PERIP1_CLK_ENB,
693 .en_reg_bit = SSP1_CLK_ENB,
694 .recalc = &follow_parent,
695};
696
697/* ssp2 clock */
698static struct clk ssp2_clk = {
699 .pclk = &apb_clk,
700 .en_reg = PERIP1_CLK_ENB,
701 .en_reg_bit = SSP2_CLK_ENB,
702 .recalc = &follow_parent,
703};
704
705/* gpio0 ARM subsystem clock */
706static struct clk gpio0_clk = {
707 .flags = ALWAYS_ENABLED,
708 .pclk = &apb_clk,
709 .recalc = &follow_parent,
710};
711
712/* gpio1 clock */
713static struct clk gpio1_clk = {
714 .pclk = &apb_clk,
715 .en_reg = PERIP1_CLK_ENB,
716 .en_reg_bit = GPIO1_CLK_ENB,
717 .recalc = &follow_parent,
718};
719
720/* gpio2 clock */
721static struct clk gpio2_clk = {
722 .pclk = &apb_clk,
723 .en_reg = PERIP1_CLK_ENB,
724 .en_reg_bit = GPIO2_CLK_ENB,
725 .recalc = &follow_parent,
726};
727
728static struct clk dummy_apb_pclk;
729
730/* array of all spear 6xx clock lookups */
731static struct clk_lookup spear_clk_lookups[] = {
732 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
733 /* root clks */
734 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
735 CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
736 /* clock derived from 32 KHz os clk */
737 CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
738 /* clock derived from 30 MHz os clk */
739 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
740 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
741 CLKDEV_INIT("wdt", NULL, &wdt_clk),
742 /* clock derived from pll1 clk */
743 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
744 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
745 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
746 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
747 CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
748 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
749 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
750 CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
751 CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
752 CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
753 CLKDEV_INIT("firda", NULL, &firda_clk),
754 CLKDEV_INIT("clcd", NULL, &clcd_clk),
755 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
756 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
757 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
758 CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
759 /* clock derived from pll3 clk */
760 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
761 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
762 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
763 /* clock derived from ahb clk */
764 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
765 CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
766 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
767 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
768 CLKDEV_INIT("gmac", NULL, &gmac_clk),
769 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
770 CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
771 /* clock derived from apb clk */
772 CLKDEV_INIT("adc", NULL, &adc_clk),
773 CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
774 CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
775 CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
776 CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
777 CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
778 CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
779};
780
781void __init spear6xx_clk_init(void)
782{
783 int i;
784
785 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
786 clk_register(&spear_clk_lookups[i]);
787
788 clk_init();
789}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 7167fd331d86..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -16,7 +16,7 @@
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18 18
19void __init spear_setup_timer(resource_size_t base, int irq); 19void __init spear_setup_of_timer(void);
20void spear_restart(char, const char *); 20void spear_restart(char, const char *);
21void __init spear6xx_clk_init(void); 21void __init spear6xx_clk_init(void);
22 22
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 2b735389e74b..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,9 +16,6 @@
16 16
17/* IRQ definitions */ 17/* IRQ definitions */
18/* VIC 1 */ 18/* VIC 1 */
19/* FIXME: probe this from DT */
20#define IRQ_CPU_GPT1_1 16
21
22#define IRQ_VIC_END 64 19#define IRQ_VIC_END 64
23 20
24/* GPIO pins virtual irqs */ 21/* GPIO pins virtual irqs */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 2b9aaa6cdd11..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,6 +14,8 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/spear.h>
18
17#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
18#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
19 21
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index d278ed047a53..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -25,7 +25,6 @@
25/* ML-1, 2 - Multi Layer CPU Subsystem */ 25/* ML-1, 2 - Multi Layer CPU Subsystem */
26#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 26#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
27#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 27#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
28#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
29 28
30/* ICM3 - Basic Subsystem */ 29/* ICM3 - Basic Subsystem */
31#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 30#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index de194dbb8371..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -419,9 +419,6 @@ struct map_desc spear6xx_io_desc[] __initdata = {
419void __init spear6xx_map_io(void) 419void __init spear6xx_map_io(void)
420{ 420{
421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
422
423 /* This will initialize clock framework */
424 spear6xx_clk_init();
425} 422}
426 423
427static void __init spear6xx_timer_init(void) 424static void __init spear6xx_timer_init(void)
@@ -429,6 +426,8 @@ static void __init spear6xx_timer_init(void)
429 char pclk_name[] = "pll3_48m_clk"; 426 char pclk_name[] = "pll3_48m_clk";
430 struct clk *gpt_clk, *pclk; 427 struct clk *gpt_clk, *pclk;
431 428
429 spear6xx_clk_init();
430
432 /* get the system timer clock */ 431 /* get the system timer clock */
433 gpt_clk = clk_get_sys("gpt0", NULL); 432 gpt_clk = clk_get_sys("gpt0", NULL);
434 if (IS_ERR(gpt_clk)) { 433 if (IS_ERR(gpt_clk)) {
@@ -448,7 +447,7 @@ static void __init spear6xx_timer_init(void)
448 clk_put(gpt_clk); 447 clk_put(gpt_clk);
449 clk_put(pclk); 448 clk_put(pclk);
450 449
451 spear_setup_timer(SPEAR6XX_CPU_TMR_BASE, IRQ_CPU_GPT1_1); 450 spear_setup_of_timer();
452} 451}
453 452
454struct sys_timer spear6xx_timer = { 453struct sys_timer spear6xx_timer = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 03:48:38 -0500