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authorArnd Bergmann <arnd@arndb.de>2012-05-14 09:33:42 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 09:33:42 -0400
commitd2819f80d465672b09c2f4cb52303b7f951c4d0f (patch)
treeaa0262703e86b97ad1460c722e78d7233e24e3bb /arch/arm/mach-spear3xx
parent5df33a62c4a028d6fc7f2dcc159827d09b7334b8 (diff)
parent366695ff706669d40459174b1cbb78fca42f4e06 (diff)
Merge branch 'spear/pinctrl' into spear/clock
Conflicts: arch/arm/mach-spear3xx/Makefile arch/arm/mach-spear3xx/clock.c arch/arm/mach-spear3xx/include/mach/generic.h arch/arm/mach-spear6xx/clock.c arch/arm/plat-spear/Makefile drivers/pinctrl/core.c This resolves some annoying merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r--arch/arm/mach-spear3xx/Kconfig37
-rw-r--r--arch/arm/mach-spear3xx/Makefile13
-rw-r--r--arch/arm/mach-spear3xx/Makefile.boot4
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h163
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h9
-rw-r--r--arch/arm/mach-spear3xx/spear300.c613
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c75
-rw-r--r--arch/arm/mach-spear3xx/spear310.c416
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c81
-rw-r--r--arch/arm/mach-spear3xx/spear320.c663
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c79
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c541
13 files changed, 861 insertions, 1836 deletions
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
5if ARCH_SPEAR3XX 5if ARCH_SPEAR3XX
6 6
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config BOARD_SPEAR300_EVB
9 bool "SPEAr300 Evaluation Board"
10 select MACH_SPEAR300
11 help
12 Supports ST SPEAr300 Evaluation Board
13
14config BOARD_SPEAR310_EVB
15 bool "SPEAr310 Evaluation Board"
16 select MACH_SPEAR310
17 help
18 Supports ST SPEAr310 Evaluation Board
19
20config BOARD_SPEAR320_EVB
21 bool "SPEAr320 Evaluation Board"
22 select MACH_SPEAR320
23 help
24 Supports ST SPEAr320 Evaluation Board
25
26endmenu
27
28config MACH_SPEAR300 8config MACH_SPEAR300
29 bool "SPEAr300" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
30 help 11 help
31 Supports ST SPEAr300 Machine 12 Supports ST SPEAr300 machine configured via the device-tree
32 13
33config MACH_SPEAR310 14config MACH_SPEAR310
34 bool "SPEAr310" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
35 help 17 help
36 Supports ST SPEAr310 Machine 18 Supports ST SPEAr310 machine configured via the device-tree
37 19
38config MACH_SPEAR320 20config MACH_SPEAR320
39 bool "SPEAr320" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
40 help 23 help
41 Supports ST SPEAr320 Machine 24 Supports ST SPEAr320 machine configured via the device-tree
42 25endmenu
43endif #ARCH_SPEAR3XX 26endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index 5b30d0d10892..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += spear3xx.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
10 10
11# spear300 boards files
12obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
13
14
15# spear310 specific files 11# spear310 specific files
16obj-$(CONFIG_MACH_SPEAR310) += spear310.o 12obj-$(CONFIG_MACH_SPEAR310) += spear310.o
17 13
18# spear310 boards files
19obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
20
21
22# spear320 specific files 14# spear320 specific files
23obj-$(CONFIG_MACH_SPEAR320) += spear320.o 15obj-$(CONFIG_MACH_SPEAR320) += spear320.o
24
25# spear320 boards files
26obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
6dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
7dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 15c107aad202..c10eac6c10cb 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,12 +14,12 @@
14#ifndef __MACH_GENERIC_H 14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/amba/pl08x.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
20#include <asm/mach/time.h> 21#include <asm/mach/time.h>
21#include <asm/mach/map.h> 22#include <asm/mach/map.h>
22#include <plat/padmux.h>
23 23
24/* spear3xx declarations */ 24/* spear3xx declarations */
25/* 25/*
@@ -31,171 +31,16 @@
31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 32
33/* Add spear3xx family device structure declarations here */ 33/* Add spear3xx family device structure declarations here */
34extern struct amba_device spear3xx_gpio_device;
35extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 34extern struct sys_timer spear3xx_timer;
35extern struct pl022_ssp_controller pl022_plat_data;
36extern struct pl08x_platform_data pl080_plat_data;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init spear_setup_timer(void); 39void __init spear_setup_timer(void);
40void __init spear3xx_clk_init(void); 40void __init spear3xx_clk_init(void);
41void __init spear3xx_map_io(void); 41void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 42void __init spear3xx_dt_init_irq(void);
43void __init spear3xx_init(void);
44 43
45void spear_restart(char, const char *); 44void spear_restart(char, const char *);
46 45
47/* pad mux declarations */
48#define PMX_FIRDA_MASK (1 << 14)
49#define PMX_I2C_MASK (1 << 13)
50#define PMX_SSP_CS_MASK (1 << 12)
51#define PMX_SSP_MASK (1 << 11)
52#define PMX_MII_MASK (1 << 10)
53#define PMX_GPIO_PIN0_MASK (1 << 9)
54#define PMX_GPIO_PIN1_MASK (1 << 8)
55#define PMX_GPIO_PIN2_MASK (1 << 7)
56#define PMX_GPIO_PIN3_MASK (1 << 6)
57#define PMX_GPIO_PIN4_MASK (1 << 5)
58#define PMX_GPIO_PIN5_MASK (1 << 4)
59#define PMX_UART0_MODEM_MASK (1 << 3)
60#define PMX_UART0_MASK (1 << 2)
61#define PMX_TIMER_3_4_MASK (1 << 1)
62#define PMX_TIMER_1_2_MASK (1 << 0)
63
64/* pad mux devices */
65extern struct pmx_dev spear3xx_pmx_firda;
66extern struct pmx_dev spear3xx_pmx_i2c;
67extern struct pmx_dev spear3xx_pmx_ssp_cs;
68extern struct pmx_dev spear3xx_pmx_ssp;
69extern struct pmx_dev spear3xx_pmx_mii;
70extern struct pmx_dev spear3xx_pmx_gpio_pin0;
71extern struct pmx_dev spear3xx_pmx_gpio_pin1;
72extern struct pmx_dev spear3xx_pmx_gpio_pin2;
73extern struct pmx_dev spear3xx_pmx_gpio_pin3;
74extern struct pmx_dev spear3xx_pmx_gpio_pin4;
75extern struct pmx_dev spear3xx_pmx_gpio_pin5;
76extern struct pmx_dev spear3xx_pmx_uart0_modem;
77extern struct pmx_dev spear3xx_pmx_uart0;
78extern struct pmx_dev spear3xx_pmx_timer_3_4;
79extern struct pmx_dev spear3xx_pmx_timer_1_2;
80
81#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
82/* padmux plgpio devices */
83extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
84extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
85extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
86extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
87extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
88extern struct pmx_dev spear3xx_pmx_plgpio_28;
89extern struct pmx_dev spear3xx_pmx_plgpio_29;
90extern struct pmx_dev spear3xx_pmx_plgpio_30;
91extern struct pmx_dev spear3xx_pmx_plgpio_31;
92extern struct pmx_dev spear3xx_pmx_plgpio_32;
93extern struct pmx_dev spear3xx_pmx_plgpio_33;
94extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
95extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
96extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
97extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
98#endif
99
100/* spear300 declarations */
101#ifdef CONFIG_MACH_SPEAR300
102/* Add spear300 machine device structure declarations here */
103extern struct amba_device spear300_gpio1_device;
104
105/* pad mux modes */
106extern struct pmx_mode spear300_nand_mode;
107extern struct pmx_mode spear300_nor_mode;
108extern struct pmx_mode spear300_photo_frame_mode;
109extern struct pmx_mode spear300_lend_ip_phone_mode;
110extern struct pmx_mode spear300_hend_ip_phone_mode;
111extern struct pmx_mode spear300_lend_wifi_phone_mode;
112extern struct pmx_mode spear300_hend_wifi_phone_mode;
113extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115extern struct pmx_mode spear300_caml_lcdw_mode;
116extern struct pmx_mode spear300_camu_lcd_mode;
117extern struct pmx_mode spear300_camu_wlcd_mode;
118extern struct pmx_mode spear300_caml_lcd_mode;
119
120/* pad mux devices */
121extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123extern struct pmx_dev spear300_pmx_keyboard;
124extern struct pmx_dev spear300_pmx_clcd;
125extern struct pmx_dev spear300_pmx_telecom_gpio;
126extern struct pmx_dev spear300_pmx_telecom_tdm;
127extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128extern struct pmx_dev spear300_pmx_telecom_camera;
129extern struct pmx_dev spear300_pmx_telecom_dac;
130extern struct pmx_dev spear300_pmx_telecom_i2s;
131extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134extern struct pmx_dev spear300_pmx_gpio1;
135
136/* Add spear300 machine function declarations here */
137void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
138 u8 pmx_dev_count);
139
140#endif /* CONFIG_MACH_SPEAR300 */
141
142/* spear310 declarations */
143#ifdef CONFIG_MACH_SPEAR310
144/* Add spear310 machine device structure declarations here */
145
146/* pad mux devices */
147extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
148extern struct pmx_dev spear310_pmx_emi_cs_2_3;
149extern struct pmx_dev spear310_pmx_uart1;
150extern struct pmx_dev spear310_pmx_uart2;
151extern struct pmx_dev spear310_pmx_uart3_4_5;
152extern struct pmx_dev spear310_pmx_fsmc;
153extern struct pmx_dev spear310_pmx_rs485_0_1;
154extern struct pmx_dev spear310_pmx_tdm0;
155
156/* Add spear310 machine function declarations here */
157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158 u8 pmx_dev_count);
159#endif /* CONFIG_MACH_SPEAR310 */
160
161/* spear320 declarations */
162#ifdef CONFIG_MACH_SPEAR320
163/* Add spear320 machine device structure declarations here */
164
165/* pad mux modes */
166extern struct pmx_mode spear320_auto_net_smii_mode;
167extern struct pmx_mode spear320_auto_net_mii_mode;
168extern struct pmx_mode spear320_auto_exp_mode;
169extern struct pmx_mode spear320_small_printers_mode;
170
171/* pad mux devices */
172extern struct pmx_dev spear320_pmx_clcd;
173extern struct pmx_dev spear320_pmx_emi;
174extern struct pmx_dev spear320_pmx_fsmc;
175extern struct pmx_dev spear320_pmx_spp;
176extern struct pmx_dev spear320_pmx_sdhci;
177extern struct pmx_dev spear320_pmx_i2s;
178extern struct pmx_dev spear320_pmx_uart1;
179extern struct pmx_dev spear320_pmx_uart1_modem;
180extern struct pmx_dev spear320_pmx_uart2;
181extern struct pmx_dev spear320_pmx_touchscreen;
182extern struct pmx_dev spear320_pmx_can;
183extern struct pmx_dev spear320_pmx_sdhci_led;
184extern struct pmx_dev spear320_pmx_pwm0;
185extern struct pmx_dev spear320_pmx_pwm1;
186extern struct pmx_dev spear320_pmx_pwm2;
187extern struct pmx_dev spear320_pmx_pwm3;
188extern struct pmx_dev spear320_pmx_ssp1;
189extern struct pmx_dev spear320_pmx_ssp2;
190extern struct pmx_dev spear320_pmx_mii1;
191extern struct pmx_dev spear320_pmx_smii0;
192extern struct pmx_dev spear320_pmx_smii1;
193extern struct pmx_dev spear320_pmx_i2c1;
194
195/* Add spear320 machine function declarations here */
196void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
197 u8 pmx_dev_count);
198
199#endif /* CONFIG_MACH_SPEAR320 */
200
201#endif /* __MACH_GENERIC_H */ 46#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..defa374f5bee 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -17,7 +17,4 @@
17#include <plat/hardware.h> 17#include <plat/hardware.h>
18#include <mach/spear.h> 18#include <mach/spear.h>
19 19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */ 20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 881109522060..e7bc8bab83fe 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -25,8 +25,9 @@
25 25
26/* ICM1 - Low speed connection */ 26/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
28#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
29#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) 30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
30#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) 31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
31#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
32#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) 33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
@@ -53,11 +54,11 @@
53#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
54#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) 56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
56#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
57 57
58/* ICM3 - Basic Subsystem */ 58/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) 59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
62#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) 63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
63#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) 64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
@@ -65,9 +66,9 @@
65#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) 66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
66#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) 67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
67#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
68#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) 69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
69#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
70#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) 71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
71#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) 72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
72 73
73/* Debug uart for linux, will be used for debug and uncompress messages */ 74/* Debug uart for linux, will be used for debug and uncompress messages */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..2db0bd14e481 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,373 +3,24 @@
3 * 3 *
4 * SPEAr300 machine source file 4 * SPEAr300 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr300: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl08x.h>
17#include <asm/irq.h> 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h>
18#include <plat/shirq.h> 20#include <plat/shirq.h>
19#include <mach/generic.h> 21#include <mach/generic.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21 23
22/* pad multiplexing support */
23/* muxing registers */
24#define PAD_MUX_CONFIG_REG 0x00
25#define MODE_CONFIG_REG 0x04
26
27/* modes */
28#define NAND_MODE (1 << 0)
29#define NOR_MODE (1 << 1)
30#define PHOTO_FRAME_MODE (1 << 2)
31#define LEND_IP_PHONE_MODE (1 << 3)
32#define HEND_IP_PHONE_MODE (1 << 4)
33#define LEND_WIFI_PHONE_MODE (1 << 5)
34#define HEND_WIFI_PHONE_MODE (1 << 6)
35#define ATA_PABX_WI2S_MODE (1 << 7)
36#define ATA_PABX_I2S_MODE (1 << 8)
37#define CAML_LCDW_MODE (1 << 9)
38#define CAMU_LCD_MODE (1 << 10)
39#define CAMU_WLCD_MODE (1 << 11)
40#define CAML_LCD_MODE (1 << 12)
41#define ALL_MODES 0x1FFF
42
43struct pmx_mode spear300_nand_mode = {
44 .id = NAND_MODE,
45 .name = "nand mode",
46 .mask = 0x00,
47};
48
49struct pmx_mode spear300_nor_mode = {
50 .id = NOR_MODE,
51 .name = "nor mode",
52 .mask = 0x01,
53};
54
55struct pmx_mode spear300_photo_frame_mode = {
56 .id = PHOTO_FRAME_MODE,
57 .name = "photo frame mode",
58 .mask = 0x02,
59};
60
61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode",
64 .mask = 0x03,
65};
66
67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode",
70 .mask = 0x04,
71};
72
73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode",
76 .mask = 0x05,
77};
78
79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode",
82 .mask = 0x06,
83};
84
85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode",
88 .mask = 0x07,
89};
90
91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode",
94 .mask = 0x08,
95};
96
97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode",
100 .mask = 0x0C,
101};
102
103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode",
106 .mask = 0x0D,
107};
108
109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode",
112 .mask = 0x0E,
113};
114
115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode",
118 .mask = 0x0F,
119};
120
121/* devices */
122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
126 .mask = PMX_FIRDA_MASK,
127 },
128};
129
130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
141 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
142 },
143};
144
145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1,
150};
151
152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
156 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
157 CAML_LCD_MODE,
158 .mask = 0x0,
159 },
160};
161
162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard",
164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1,
167};
168
169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 {
171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
173 }, {
174 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
175 CAMU_LCD_MODE | CAML_LCD_MODE,
176 .mask = PMX_TIMER_3_4_MASK,
177 },
178};
179
180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd",
182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1,
185};
186
187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK,
191 }, {
192 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
193 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
194 }, {
195 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
196 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
197 }, {
198 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
199 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
200 }, {
201 .ids = ATA_PABX_WI2S_MODE,
202 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
203 | PMX_UART0_MODEM_MASK,
204 },
205};
206
207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1,
212};
213
214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
218 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
219 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
220 | CAMU_WLCD_MODE | CAML_LCD_MODE,
221 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
236 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
237 CAML_LCDW_MODE | CAML_LCD_MODE,
238 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
239 },
240};
241
242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK,
253 }, {
254 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
255 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
270 .mask = PMX_TIMER_1_2_MASK,
271 },
272};
273
274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1,
279};
280
281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
285 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
286 | CAMU_WLCD_MODE | CAML_LCD_MODE,
287 .mask = PMX_UART0_MODEM_MASK,
288 },
289};
290
291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 {
300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
302 PMX_TIMER_3_4_MASK,
303 },
304};
305
306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1,
311};
312
313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
317 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
318 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
319 ATA_PABX_I2S_MODE,
320 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
321 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
322 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
323 },
324};
325
326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1,
331};
332
333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
337 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
338 CAMU_WLCD_MODE | CAML_LCD_MODE,
339 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
340 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
341 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
342 },
343};
344
345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 {
354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
356 PMX_TIMER_3_4_MASK,
357 },
358};
359
360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
364 .enb_on_reset = 1,
365};
366
367/* pmx driver structure */
368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371};
372
373/* spear3xx shared irq */ 24/* spear3xx shared irq */
374static struct shirq_dev_config shirq_ras1_config[] = { 25static struct shirq_dev_config shirq_ras1_config[] = {
375 { 26 {
@@ -423,45 +74,239 @@ static struct spear_shirq shirq_ras1 = {
423 }, 74 },
424}; 75};
425 76
426/* Add spear300 specific devices here */ 77/* DMAC platform data's slave info */
427/* arm gpio1 device registration */ 78struct pl08x_channel_data spear300_dma_info[] = {
428static struct pl061_platform_data gpio1_plat_data = { 79 {
429 .gpio_base = 8, 80 .bus_id = "uart0_rx",
430 .irq_base = SPEAR300_GPIO1_INT_BASE, 81 .min_signal = 2,
82 .max_signal = 2,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB1,
86 }, {
87 .bus_id = "uart0_tx",
88 .min_signal = 3,
89 .max_signal = 3,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_rx",
95 .min_signal = 8,
96 .max_signal = 8,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "ssp0_tx",
102 .min_signal = 9,
103 .max_signal = 9,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_rx",
109 .min_signal = 10,
110 .max_signal = 10,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "i2c_tx",
116 .min_signal = 11,
117 .max_signal = 11,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "irda",
123 .min_signal = 12,
124 .max_signal = 12,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB1,
128 }, {
129 .bus_id = "adc",
130 .min_signal = 13,
131 .max_signal = 13,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "to_jpeg",
137 .min_signal = 14,
138 .max_signal = 14,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "from_jpeg",
144 .min_signal = 15,
145 .max_signal = 15,
146 .muxval = 0,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_rx",
151 .min_signal = 0,
152 .max_signal = 0,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras0_tx",
158 .min_signal = 1,
159 .max_signal = 1,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_rx",
165 .min_signal = 2,
166 .max_signal = 2,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras1_tx",
172 .min_signal = 3,
173 .max_signal = 3,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_rx",
179 .min_signal = 4,
180 .max_signal = 4,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras2_tx",
186 .min_signal = 5,
187 .max_signal = 5,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_rx",
193 .min_signal = 6,
194 .max_signal = 6,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras3_tx",
200 .min_signal = 7,
201 .max_signal = 7,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_rx",
207 .min_signal = 8,
208 .max_signal = 8,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras4_tx",
214 .min_signal = 9,
215 .max_signal = 9,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_rx",
221 .min_signal = 10,
222 .max_signal = 10,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras5_tx",
228 .min_signal = 11,
229 .max_signal = 11,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_rx",
235 .min_signal = 12,
236 .max_signal = 12,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras6_tx",
242 .min_signal = 13,
243 .max_signal = 13,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_rx",
249 .min_signal = 14,
250 .max_signal = 14,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ras7_tx",
256 .min_signal = 15,
257 .max_signal = 15,
258 .muxval = 1,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB1,
261 },
431}; 262};
432 263
433AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, 264/* Add SPEAr300 auxdata to pass platform data */
434 {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); 265static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
266 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
267 &pl022_plat_data),
268 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
269 &pl080_plat_data),
270 {}
271};
435 272
436/* spear300 routines */ 273static void __init spear300_dt_init(void)
437void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
438 u8 pmx_dev_count)
439{ 274{
440 int ret = 0; 275 int ret;
276
277 pl080_plat_data.slave_channels = spear300_dma_info;
278 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
441 279
442 /* call spear3xx family common init function */ 280 of_platform_populate(NULL, of_default_bus_match_table,
443 spear3xx_init(); 281 spear300_auxdata_lookup, NULL);
444 282
445 /* shared irq registration */ 283 /* shared irq registration */
446 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); 284 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
447 if (shirq_ras1.regs.base) { 285 if (shirq_ras1.regs.base) {
448 ret = spear_shirq_register(&shirq_ras1); 286 ret = spear_shirq_register(&shirq_ras1);
449 if (ret) 287 if (ret)
450 printk(KERN_ERR "Error registering Shared IRQ\n"); 288 pr_err("Error registering Shared IRQ\n");
451 } 289 }
290}
452 291
453 /* pmx initialization */ 292static const char * const spear300_dt_board_compat[] = {
454 pmx_driver.mode = pmx_mode; 293 "st,spear300",
455 pmx_driver.devs = pmx_devs; 294 "st,spear300-evb",
456 pmx_driver.devs_count = pmx_dev_count; 295 NULL,
296};
457 297
458 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 298static void __init spear300_map_io(void)
459 if (pmx_driver.base) { 299{
460 ret = pmx_register(&pmx_driver); 300 spear3xx_map_io();
461 if (ret) 301 spear300_clk_init();
462 printk(KERN_ERR "padmux: registration failed. err no"
463 ": %d\n", ret);
464 /* Free Mapping, device selection already done */
465 iounmap(pmx_driver.base);
466 }
467} 302}
303
304DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
305 .map_io = spear300_map_io,
306 .init_irq = spear3xx_dt_init_irq,
307 .handle_irq = vic_handle_irq,
308 .timer = &spear3xx_timer,
309 .init_machine = spear300_dt_init,
310 .restart = spear_restart,
311 .dt_compat = spear300_dt_board_compat,
312MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear300_evb.c
3 *
4 * SPEAr300 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp_cs,
25 &spear3xx_pmx_ssp,
26 &spear3xx_pmx_mii,
27 &spear3xx_pmx_uart0,
28
29 /* spear300 specific devices */
30 &spear300_pmx_fsmc_2_chips,
31 &spear300_pmx_clcd,
32 &spear300_pmx_telecom_sdhci_4bit,
33 &spear300_pmx_gpio1,
34};
35
36static struct amba_device *amba_devs[] __initdata = {
37 /* spear3xx specific devices */
38 &spear3xx_gpio_device,
39 &spear3xx_uart_device,
40
41 /* spear300 specific devices */
42 &spear300_gpio1_device,
43};
44
45static struct platform_device *plat_devs[] __initdata = {
46 /* spear3xx specific devices */
47
48 /* spear300 specific devices */
49};
50
51static void __init spear300_evb_init(void)
52{
53 unsigned int i;
54
55 /* call spear300 machine init function */
56 spear300_init(&spear300_photo_frame_mode, pmx_devs,
57 ARRAY_SIZE(pmx_devs));
58
59 /* Add Platform Devices */
60 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
61
62 /* Add Amba Devices */
63 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
64 amba_device_register(amba_devs[i], &iomem_resource);
65}
66
67MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
68 .atag_offset = 0x100,
69 .map_io = spear3xx_map_io,
70 .init_irq = spear3xx_init_irq,
71 .handle_irq = vic_handle_irq,
72 .timer = &spear3xx_timer,
73 .init_machine = spear300_evb_init,
74 .restart = spear_restart,
75MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..aec07c951205 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,142 +3,25 @@
3 * 3 *
4 * SPEAr310 machine source file 4 * SPEAr310 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr310: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl08x.h>
17#include <linux/amba/serial.h>
18#include <linux/of_platform.h>
19#include <asm/hardware/vic.h>
20#include <asm/mach/arch.h>
16#include <plat/shirq.h> 21#include <plat/shirq.h>
17#include <mach/generic.h> 22#include <mach/generic.h>
18#include <mach/hardware.h> 23#include <mach/hardware.h>
19 24
20/* pad multiplexing support */
21/* muxing registers */
22#define PAD_MUX_CONFIG_REG 0x08
23
24/* devices */
25static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
26 {
27 .ids = 0x00,
28 .mask = PMX_TIMER_3_4_MASK,
29 },
30};
31
32struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
33 .name = "emi_cs_0_1_4_5",
34 .modes = pmx_emi_cs_0_1_4_5_modes,
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
36 .enb_on_reset = 1,
37};
38
39static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
40 {
41 .ids = 0x00,
42 .mask = PMX_TIMER_1_2_MASK,
43 },
44};
45
46struct pmx_dev spear310_pmx_emi_cs_2_3 = {
47 .name = "emi_cs_2_3",
48 .modes = pmx_emi_cs_2_3_modes,
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
50 .enb_on_reset = 1,
51};
52
53static struct pmx_dev_mode pmx_uart1_modes[] = {
54 {
55 .ids = 0x00,
56 .mask = PMX_FIRDA_MASK,
57 },
58};
59
60struct pmx_dev spear310_pmx_uart1 = {
61 .name = "uart1",
62 .modes = pmx_uart1_modes,
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
64 .enb_on_reset = 1,
65};
66
67static struct pmx_dev_mode pmx_uart2_modes[] = {
68 {
69 .ids = 0x00,
70 .mask = PMX_TIMER_1_2_MASK,
71 },
72};
73
74struct pmx_dev spear310_pmx_uart2 = {
75 .name = "uart2",
76 .modes = pmx_uart2_modes,
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
78 .enb_on_reset = 1,
79};
80
81static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82 {
83 .ids = 0x00,
84 .mask = PMX_UART0_MODEM_MASK,
85 },
86};
87
88struct pmx_dev spear310_pmx_uart3_4_5 = {
89 .name = "uart3_4_5",
90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92 .enb_on_reset = 1,
93};
94
95static struct pmx_dev_mode pmx_fsmc_modes[] = {
96 {
97 .ids = 0x00,
98 .mask = PMX_SSP_CS_MASK,
99 },
100};
101
102struct pmx_dev spear310_pmx_fsmc = {
103 .name = "fsmc",
104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106 .enb_on_reset = 1,
107};
108
109static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110 {
111 .ids = 0x00,
112 .mask = PMX_MII_MASK,
113 },
114};
115
116struct pmx_dev spear310_pmx_rs485_0_1 = {
117 .name = "rs485_0_1",
118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120 .enb_on_reset = 1,
121};
122
123static struct pmx_dev_mode pmx_tdm0_modes[] = {
124 {
125 .ids = 0x00,
126 .mask = PMX_MII_MASK,
127 },
128};
129
130struct pmx_dev spear310_pmx_tdm0 = {
131 .name = "tdm0",
132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
134 .enb_on_reset = 1,
135};
136
137/* pmx driver structure */
138static struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140};
141
142/* spear3xx shared irq */ 25/* spear3xx shared irq */
143static struct shirq_dev_config shirq_ras1_config[] = { 26static struct shirq_dev_config shirq_ras1_config[] = {
144 { 27 {
@@ -255,17 +138,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
255 }, 138 },
256}; 139};
257 140
258/* Add spear310 specific devices here */ 141/* DMAC platform data's slave info */
142struct pl08x_channel_data spear310_dma_info[] = {
143 {
144 .bus_id = "uart0_rx",
145 .min_signal = 2,
146 .max_signal = 2,
147 .muxval = 0,
148 .cctl = 0,
149 .periph_buses = PL08X_AHB1,
150 }, {
151 .bus_id = "uart0_tx",
152 .min_signal = 3,
153 .max_signal = 3,
154 .muxval = 0,
155 .cctl = 0,
156 .periph_buses = PL08X_AHB1,
157 }, {
158 .bus_id = "ssp0_rx",
159 .min_signal = 8,
160 .max_signal = 8,
161 .muxval = 0,
162 .cctl = 0,
163 .periph_buses = PL08X_AHB1,
164 }, {
165 .bus_id = "ssp0_tx",
166 .min_signal = 9,
167 .max_signal = 9,
168 .muxval = 0,
169 .cctl = 0,
170 .periph_buses = PL08X_AHB1,
171 }, {
172 .bus_id = "i2c_rx",
173 .min_signal = 10,
174 .max_signal = 10,
175 .muxval = 0,
176 .cctl = 0,
177 .periph_buses = PL08X_AHB1,
178 }, {
179 .bus_id = "i2c_tx",
180 .min_signal = 11,
181 .max_signal = 11,
182 .muxval = 0,
183 .cctl = 0,
184 .periph_buses = PL08X_AHB1,
185 }, {
186 .bus_id = "irda",
187 .min_signal = 12,
188 .max_signal = 12,
189 .muxval = 0,
190 .cctl = 0,
191 .periph_buses = PL08X_AHB1,
192 }, {
193 .bus_id = "adc",
194 .min_signal = 13,
195 .max_signal = 13,
196 .muxval = 0,
197 .cctl = 0,
198 .periph_buses = PL08X_AHB1,
199 }, {
200 .bus_id = "to_jpeg",
201 .min_signal = 14,
202 .max_signal = 14,
203 .muxval = 0,
204 .cctl = 0,
205 .periph_buses = PL08X_AHB1,
206 }, {
207 .bus_id = "from_jpeg",
208 .min_signal = 15,
209 .max_signal = 15,
210 .muxval = 0,
211 .cctl = 0,
212 .periph_buses = PL08X_AHB1,
213 }, {
214 .bus_id = "uart1_rx",
215 .min_signal = 0,
216 .max_signal = 0,
217 .muxval = 1,
218 .cctl = 0,
219 .periph_buses = PL08X_AHB1,
220 }, {
221 .bus_id = "uart1_tx",
222 .min_signal = 1,
223 .max_signal = 1,
224 .muxval = 1,
225 .cctl = 0,
226 .periph_buses = PL08X_AHB1,
227 }, {
228 .bus_id = "uart2_rx",
229 .min_signal = 2,
230 .max_signal = 2,
231 .muxval = 1,
232 .cctl = 0,
233 .periph_buses = PL08X_AHB1,
234 }, {
235 .bus_id = "uart2_tx",
236 .min_signal = 3,
237 .max_signal = 3,
238 .muxval = 1,
239 .cctl = 0,
240 .periph_buses = PL08X_AHB1,
241 }, {
242 .bus_id = "uart3_rx",
243 .min_signal = 4,
244 .max_signal = 4,
245 .muxval = 1,
246 .cctl = 0,
247 .periph_buses = PL08X_AHB1,
248 }, {
249 .bus_id = "uart3_tx",
250 .min_signal = 5,
251 .max_signal = 5,
252 .muxval = 1,
253 .cctl = 0,
254 .periph_buses = PL08X_AHB1,
255 }, {
256 .bus_id = "uart4_rx",
257 .min_signal = 6,
258 .max_signal = 6,
259 .muxval = 1,
260 .cctl = 0,
261 .periph_buses = PL08X_AHB1,
262 }, {
263 .bus_id = "uart4_tx",
264 .min_signal = 7,
265 .max_signal = 7,
266 .muxval = 1,
267 .cctl = 0,
268 .periph_buses = PL08X_AHB1,
269 }, {
270 .bus_id = "uart5_rx",
271 .min_signal = 8,
272 .max_signal = 8,
273 .muxval = 1,
274 .cctl = 0,
275 .periph_buses = PL08X_AHB1,
276 }, {
277 .bus_id = "uart5_tx",
278 .min_signal = 9,
279 .max_signal = 9,
280 .muxval = 1,
281 .cctl = 0,
282 .periph_buses = PL08X_AHB1,
283 }, {
284 .bus_id = "ras5_rx",
285 .min_signal = 10,
286 .max_signal = 10,
287 .muxval = 1,
288 .cctl = 0,
289 .periph_buses = PL08X_AHB1,
290 }, {
291 .bus_id = "ras5_tx",
292 .min_signal = 11,
293 .max_signal = 11,
294 .muxval = 1,
295 .cctl = 0,
296 .periph_buses = PL08X_AHB1,
297 }, {
298 .bus_id = "ras6_rx",
299 .min_signal = 12,
300 .max_signal = 12,
301 .muxval = 1,
302 .cctl = 0,
303 .periph_buses = PL08X_AHB1,
304 }, {
305 .bus_id = "ras6_tx",
306 .min_signal = 13,
307 .max_signal = 13,
308 .muxval = 1,
309 .cctl = 0,
310 .periph_buses = PL08X_AHB1,
311 }, {
312 .bus_id = "ras7_rx",
313 .min_signal = 14,
314 .max_signal = 14,
315 .muxval = 1,
316 .cctl = 0,
317 .periph_buses = PL08X_AHB1,
318 }, {
319 .bus_id = "ras7_tx",
320 .min_signal = 15,
321 .max_signal = 15,
322 .muxval = 1,
323 .cctl = 0,
324 .periph_buses = PL08X_AHB1,
325 },
326};
259 327
260/* spear310 routines */ 328/* uart devices plat data */
261void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 329static struct amba_pl011_data spear310_uart_data[] = {
262 u8 pmx_dev_count) 330 {
331 .dma_filter = pl08x_filter_id,
332 .dma_tx_param = "uart1_tx",
333 .dma_rx_param = "uart1_rx",
334 }, {
335 .dma_filter = pl08x_filter_id,
336 .dma_tx_param = "uart2_tx",
337 .dma_rx_param = "uart2_rx",
338 }, {
339 .dma_filter = pl08x_filter_id,
340 .dma_tx_param = "uart3_tx",
341 .dma_rx_param = "uart3_rx",
342 }, {
343 .dma_filter = pl08x_filter_id,
344 .dma_tx_param = "uart4_tx",
345 .dma_rx_param = "uart4_rx",
346 }, {
347 .dma_filter = pl08x_filter_id,
348 .dma_tx_param = "uart5_tx",
349 .dma_rx_param = "uart5_rx",
350 },
351};
352
353/* Add SPEAr310 auxdata to pass platform data */
354static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
355 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
356 &pl022_plat_data),
357 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
358 &pl080_plat_data),
359 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
360 &spear310_uart_data[0]),
361 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
362 &spear310_uart_data[1]),
363 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
364 &spear310_uart_data[2]),
365 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
366 &spear310_uart_data[3]),
367 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
368 &spear310_uart_data[4]),
369 {}
370};
371
372static void __init spear310_dt_init(void)
263{ 373{
264 void __iomem *base; 374 void __iomem *base;
265 int ret = 0; 375 int ret;
266 376
267 /* call spear3xx family common init function */ 377 pl080_plat_data.slave_channels = spear310_dma_info;
268 spear3xx_init(); 378 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
379
380 of_platform_populate(NULL, of_default_bus_match_table,
381 spear310_auxdata_lookup, NULL);
269 382
270 /* shared irq registration */ 383 /* shared irq registration */
271 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); 384 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +387,46 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
274 shirq_ras1.regs.base = base; 387 shirq_ras1.regs.base = base;
275 ret = spear_shirq_register(&shirq_ras1); 388 ret = spear_shirq_register(&shirq_ras1);
276 if (ret) 389 if (ret)
277 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 390 pr_err("Error registering Shared IRQ 1\n");
278 391
279 /* shirq 2 */ 392 /* shirq 2 */
280 shirq_ras2.regs.base = base; 393 shirq_ras2.regs.base = base;
281 ret = spear_shirq_register(&shirq_ras2); 394 ret = spear_shirq_register(&shirq_ras2);
282 if (ret) 395 if (ret)
283 printk(KERN_ERR "Error registering Shared IRQ 2\n"); 396 pr_err("Error registering Shared IRQ 2\n");
284 397
285 /* shirq 3 */ 398 /* shirq 3 */
286 shirq_ras3.regs.base = base; 399 shirq_ras3.regs.base = base;
287 ret = spear_shirq_register(&shirq_ras3); 400 ret = spear_shirq_register(&shirq_ras3);
288 if (ret) 401 if (ret)
289 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 402 pr_err("Error registering Shared IRQ 3\n");
290 403
291 /* shirq 4 */ 404 /* shirq 4 */
292 shirq_intrcomm_ras.regs.base = base; 405 shirq_intrcomm_ras.regs.base = base;
293 ret = spear_shirq_register(&shirq_intrcomm_ras); 406 ret = spear_shirq_register(&shirq_intrcomm_ras);
294 if (ret) 407 if (ret)
295 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 408 pr_err("Error registering Shared IRQ 4\n");
296 } 409 }
410}
297 411
298 /* pmx initialization */ 412static const char * const spear310_dt_board_compat[] = {
299 pmx_driver.base = base; 413 "st,spear310",
300 pmx_driver.mode = pmx_mode; 414 "st,spear310-evb",
301 pmx_driver.devs = pmx_devs; 415 NULL,
302 pmx_driver.devs_count = pmx_dev_count; 416};
303 417
304 ret = pmx_register(&pmx_driver); 418static void __init spear310_map_io(void)
305 if (ret) 419{
306 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 420 spear3xx_map_io();
307 ret); 421 spear310_clk_init();
308} 422}
423
424DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
425 .map_io = spear310_map_io,
426 .init_irq = spear3xx_dt_init_irq,
427 .handle_irq = vic_handle_irq,
428 .timer = &spear3xx_timer,
429 .init_machine = spear310_dt_init,
430 .restart = spear_restart,
431 .dt_compat = spear310_dt_board_compat,
432MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear310_evb.c
3 *
4 * SPEAr310 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_gpio_pin0,
26 &spear3xx_pmx_gpio_pin1,
27 &spear3xx_pmx_gpio_pin2,
28 &spear3xx_pmx_gpio_pin3,
29 &spear3xx_pmx_gpio_pin4,
30 &spear3xx_pmx_gpio_pin5,
31 &spear3xx_pmx_uart0,
32
33 /* spear310 specific devices */
34 &spear310_pmx_emi_cs_0_1_4_5,
35 &spear310_pmx_emi_cs_2_3,
36 &spear310_pmx_uart1,
37 &spear310_pmx_uart2,
38 &spear310_pmx_uart3_4_5,
39 &spear310_pmx_fsmc,
40 &spear310_pmx_rs485_0_1,
41 &spear310_pmx_tdm0,
42};
43
44static struct amba_device *amba_devs[] __initdata = {
45 /* spear3xx specific devices */
46 &spear3xx_gpio_device,
47 &spear3xx_uart_device,
48
49 /* spear310 specific devices */
50};
51
52static struct platform_device *plat_devs[] __initdata = {
53 /* spear3xx specific devices */
54
55 /* spear310 specific devices */
56};
57
58static void __init spear310_evb_init(void)
59{
60 unsigned int i;
61
62 /* call spear310 machine init function */
63 spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
64
65 /* Add Platform Devices */
66 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
67
68 /* Add Amba Devices */
69 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
70 amba_device_register(amba_devs[i], &iomem_resource);
71}
72
73MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
74 .atag_offset = 0x100,
75 .map_io = spear3xx_map_io,
76 .init_irq = spear3xx_init_irq,
77 .handle_irq = vic_handle_irq,
78 .timer = &spear3xx_timer,
79 .init_machine = spear310_evb_init,
80 .restart = spear_restart,
81MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index bfdad554319c..fb28c189688e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,388 +3,27 @@
3 * 3 *
4 * SPEAr320 machine source file 4 * SPEAr320 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr320: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h>
16#include <plat/shirq.h> 22#include <plat/shirq.h>
17#include <mach/generic.h> 23#include <mach/generic.h>
18#include <mach/hardware.h> 24#include <mach/hardware.h>
19#include <mach/spear.h> 25#include <mach/spear.h>
20 26
21/* pad multiplexing support */
22/* muxing registers */
23#define PAD_MUX_CONFIG_REG 0x0C
24#define MODE_CONFIG_REG 0x10
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define ALL_MODES 0xF
32
33struct pmx_mode spear320_auto_net_smii_mode = {
34 .id = AUTO_NET_SMII_MODE,
35 .name = "Automation Networking SMII Mode",
36 .mask = 0x00,
37};
38
39struct pmx_mode spear320_auto_net_mii_mode = {
40 .id = AUTO_NET_MII_MODE,
41 .name = "Automation Networking MII Mode",
42 .mask = 0x01,
43};
44
45struct pmx_mode spear320_auto_exp_mode = {
46 .id = AUTO_EXP_MODE,
47 .name = "Automation Expanded Mode",
48 .mask = 0x02,
49};
50
51struct pmx_mode spear320_small_printers_mode = {
52 .id = SMALL_PRINTERS_MODE,
53 .name = "Small Printers Mode",
54 .mask = 0x03,
55};
56
57/* devices */
58static struct pmx_dev_mode pmx_clcd_modes[] = {
59 {
60 .ids = AUTO_NET_SMII_MODE,
61 .mask = 0x0,
62 },
63};
64
65struct pmx_dev spear320_pmx_clcd = {
66 .name = "clcd",
67 .modes = pmx_clcd_modes,
68 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
69 .enb_on_reset = 1,
70};
71
72static struct pmx_dev_mode pmx_emi_modes[] = {
73 {
74 .ids = AUTO_EXP_MODE,
75 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
76 },
77};
78
79struct pmx_dev spear320_pmx_emi = {
80 .name = "emi",
81 .modes = pmx_emi_modes,
82 .mode_count = ARRAY_SIZE(pmx_emi_modes),
83 .enb_on_reset = 1,
84};
85
86static struct pmx_dev_mode pmx_fsmc_modes[] = {
87 {
88 .ids = ALL_MODES,
89 .mask = 0x0,
90 },
91};
92
93struct pmx_dev spear320_pmx_fsmc = {
94 .name = "fsmc",
95 .modes = pmx_fsmc_modes,
96 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
97 .enb_on_reset = 1,
98};
99
100static struct pmx_dev_mode pmx_spp_modes[] = {
101 {
102 .ids = SMALL_PRINTERS_MODE,
103 .mask = 0x0,
104 },
105};
106
107struct pmx_dev spear320_pmx_spp = {
108 .name = "spp",
109 .modes = pmx_spp_modes,
110 .mode_count = ARRAY_SIZE(pmx_spp_modes),
111 .enb_on_reset = 1,
112};
113
114static struct pmx_dev_mode pmx_sdhci_modes[] = {
115 {
116 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
117 SMALL_PRINTERS_MODE,
118 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
119 },
120};
121
122struct pmx_dev spear320_pmx_sdhci = {
123 .name = "sdhci",
124 .modes = pmx_sdhci_modes,
125 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
126 .enb_on_reset = 1,
127};
128
129static struct pmx_dev_mode pmx_i2s_modes[] = {
130 {
131 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
132 .mask = PMX_UART0_MODEM_MASK,
133 },
134};
135
136struct pmx_dev spear320_pmx_i2s = {
137 .name = "i2s",
138 .modes = pmx_i2s_modes,
139 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
140 .enb_on_reset = 1,
141};
142
143static struct pmx_dev_mode pmx_uart1_modes[] = {
144 {
145 .ids = ALL_MODES,
146 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
147 },
148};
149
150struct pmx_dev spear320_pmx_uart1 = {
151 .name = "uart1",
152 .modes = pmx_uart1_modes,
153 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
154 .enb_on_reset = 1,
155};
156
157static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
158 {
159 .ids = AUTO_EXP_MODE,
160 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
161 PMX_SSP_CS_MASK,
162 }, {
163 .ids = SMALL_PRINTERS_MODE,
164 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
165 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
166 },
167};
168
169struct pmx_dev spear320_pmx_uart1_modem = {
170 .name = "uart1_modem",
171 .modes = pmx_uart1_modem_modes,
172 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
173 .enb_on_reset = 1,
174};
175
176static struct pmx_dev_mode pmx_uart2_modes[] = {
177 {
178 .ids = ALL_MODES,
179 .mask = PMX_FIRDA_MASK,
180 },
181};
182
183struct pmx_dev spear320_pmx_uart2 = {
184 .name = "uart2",
185 .modes = pmx_uart2_modes,
186 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
187 .enb_on_reset = 1,
188};
189
190static struct pmx_dev_mode pmx_touchscreen_modes[] = {
191 {
192 .ids = AUTO_NET_SMII_MODE,
193 .mask = PMX_SSP_CS_MASK,
194 },
195};
196
197struct pmx_dev spear320_pmx_touchscreen = {
198 .name = "touchscreen",
199 .modes = pmx_touchscreen_modes,
200 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
201 .enb_on_reset = 1,
202};
203
204static struct pmx_dev_mode pmx_can_modes[] = {
205 {
206 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
207 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
208 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
209 },
210};
211
212struct pmx_dev spear320_pmx_can = {
213 .name = "can",
214 .modes = pmx_can_modes,
215 .mode_count = ARRAY_SIZE(pmx_can_modes),
216 .enb_on_reset = 1,
217};
218
219static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
220 {
221 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
222 .mask = PMX_SSP_CS_MASK,
223 },
224};
225
226struct pmx_dev spear320_pmx_sdhci_led = {
227 .name = "sdhci_led",
228 .modes = pmx_sdhci_led_modes,
229 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
230 .enb_on_reset = 1,
231};
232
233static struct pmx_dev_mode pmx_pwm0_modes[] = {
234 {
235 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
236 .mask = PMX_UART0_MODEM_MASK,
237 }, {
238 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
239 .mask = PMX_MII_MASK,
240 },
241};
242
243struct pmx_dev spear320_pmx_pwm0 = {
244 .name = "pwm0",
245 .modes = pmx_pwm0_modes,
246 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
247 .enb_on_reset = 1,
248};
249
250static struct pmx_dev_mode pmx_pwm1_modes[] = {
251 {
252 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
253 .mask = PMX_UART0_MODEM_MASK,
254 }, {
255 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
256 .mask = PMX_MII_MASK,
257 },
258};
259
260struct pmx_dev spear320_pmx_pwm1 = {
261 .name = "pwm1",
262 .modes = pmx_pwm1_modes,
263 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
264 .enb_on_reset = 1,
265};
266
267static struct pmx_dev_mode pmx_pwm2_modes[] = {
268 {
269 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
270 .mask = PMX_SSP_CS_MASK,
271 }, {
272 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
273 .mask = PMX_MII_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_pwm2 = {
278 .name = "pwm2",
279 .modes = pmx_pwm2_modes,
280 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_pwm3_modes[] = {
285 {
286 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
287 .mask = PMX_MII_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_pwm3 = {
292 .name = "pwm3",
293 .modes = pmx_pwm3_modes,
294 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_ssp1_modes[] = {
299 {
300 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
301 .mask = PMX_MII_MASK,
302 },
303};
304
305struct pmx_dev spear320_pmx_ssp1 = {
306 .name = "ssp1",
307 .modes = pmx_ssp1_modes,
308 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_ssp2_modes[] = {
313 {
314 .ids = AUTO_NET_SMII_MODE,
315 .mask = PMX_MII_MASK,
316 },
317};
318
319struct pmx_dev spear320_pmx_ssp2 = {
320 .name = "ssp2",
321 .modes = pmx_ssp2_modes,
322 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_mii1_modes[] = {
327 {
328 .ids = AUTO_NET_MII_MODE,
329 .mask = 0x0,
330 },
331};
332
333struct pmx_dev spear320_pmx_mii1 = {
334 .name = "mii1",
335 .modes = pmx_mii1_modes,
336 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_smii0_modes[] = {
341 {
342 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
343 .mask = PMX_MII_MASK,
344 },
345};
346
347struct pmx_dev spear320_pmx_smii0 = {
348 .name = "smii0",
349 .modes = pmx_smii0_modes,
350 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_smii1_modes[] = {
355 {
356 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear320_pmx_smii1 = {
362 .name = "smii1",
363 .modes = pmx_smii1_modes,
364 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_i2c1_modes[] = {
369 {
370 .ids = AUTO_EXP_MODE,
371 .mask = 0x0,
372 },
373};
374
375struct pmx_dev spear320_pmx_i2c1 = {
376 .name = "i2c1",
377 .modes = pmx_i2c1_modes,
378 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
379 .enb_on_reset = 1,
380};
381
382/* pmx driver structure */
383static struct pmx_driver pmx_driver = {
384 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
385 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
386};
387
388/* spear3xx shared irq */ 27/* spear3xx shared irq */
389static struct shirq_dev_config shirq_ras1_config[] = { 28static struct shirq_dev_config shirq_ras1_config[] = {
390 { 29 {
@@ -509,17 +148,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
509 }, 148 },
510}; 149};
511 150
512/* Add spear320 specific devices here */ 151/* DMAC platform data's slave info */
152struct pl08x_channel_data spear320_dma_info[] = {
153 {
154 .bus_id = "uart0_rx",
155 .min_signal = 2,
156 .max_signal = 2,
157 .muxval = 0,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "uart0_tx",
162 .min_signal = 3,
163 .max_signal = 3,
164 .muxval = 0,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "ssp0_rx",
169 .min_signal = 8,
170 .max_signal = 8,
171 .muxval = 0,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "ssp0_tx",
176 .min_signal = 9,
177 .max_signal = 9,
178 .muxval = 0,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "i2c0_rx",
183 .min_signal = 10,
184 .max_signal = 10,
185 .muxval = 0,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "i2c0_tx",
190 .min_signal = 11,
191 .max_signal = 11,
192 .muxval = 0,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "irda",
197 .min_signal = 12,
198 .max_signal = 12,
199 .muxval = 0,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "adc",
204 .min_signal = 13,
205 .max_signal = 13,
206 .muxval = 0,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "to_jpeg",
211 .min_signal = 14,
212 .max_signal = 14,
213 .muxval = 0,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "from_jpeg",
218 .min_signal = 15,
219 .max_signal = 15,
220 .muxval = 0,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ssp1_rx",
225 .min_signal = 0,
226 .max_signal = 0,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB2,
230 }, {
231 .bus_id = "ssp1_tx",
232 .min_signal = 1,
233 .max_signal = 1,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB2,
237 }, {
238 .bus_id = "ssp2_rx",
239 .min_signal = 2,
240 .max_signal = 2,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB2,
244 }, {
245 .bus_id = "ssp2_tx",
246 .min_signal = 3,
247 .max_signal = 3,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB2,
251 }, {
252 .bus_id = "uart1_rx",
253 .min_signal = 4,
254 .max_signal = 4,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB2,
258 }, {
259 .bus_id = "uart1_tx",
260 .min_signal = 5,
261 .max_signal = 5,
262 .muxval = 1,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB2,
265 }, {
266 .bus_id = "uart2_rx",
267 .min_signal = 6,
268 .max_signal = 6,
269 .muxval = 1,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB2,
272 }, {
273 .bus_id = "uart2_tx",
274 .min_signal = 7,
275 .max_signal = 7,
276 .muxval = 1,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB2,
279 }, {
280 .bus_id = "i2c1_rx",
281 .min_signal = 8,
282 .max_signal = 8,
283 .muxval = 1,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB2,
286 }, {
287 .bus_id = "i2c1_tx",
288 .min_signal = 9,
289 .max_signal = 9,
290 .muxval = 1,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB2,
293 }, {
294 .bus_id = "i2c2_rx",
295 .min_signal = 10,
296 .max_signal = 10,
297 .muxval = 1,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB2,
300 }, {
301 .bus_id = "i2c2_tx",
302 .min_signal = 11,
303 .max_signal = 11,
304 .muxval = 1,
305 .cctl = 0,
306 .periph_buses = PL08X_AHB2,
307 }, {
308 .bus_id = "i2s_rx",
309 .min_signal = 12,
310 .max_signal = 12,
311 .muxval = 1,
312 .cctl = 0,
313 .periph_buses = PL08X_AHB2,
314 }, {
315 .bus_id = "i2s_tx",
316 .min_signal = 13,
317 .max_signal = 13,
318 .muxval = 1,
319 .cctl = 0,
320 .periph_buses = PL08X_AHB2,
321 }, {
322 .bus_id = "rs485_rx",
323 .min_signal = 14,
324 .max_signal = 14,
325 .muxval = 1,
326 .cctl = 0,
327 .periph_buses = PL08X_AHB2,
328 }, {
329 .bus_id = "rs485_tx",
330 .min_signal = 15,
331 .max_signal = 15,
332 .muxval = 1,
333 .cctl = 0,
334 .periph_buses = PL08X_AHB2,
335 },
336};
337
338static struct pl022_ssp_controller spear320_ssp_data[] = {
339 {
340 .bus_id = 1,
341 .enable_dma = 1,
342 .dma_filter = pl08x_filter_id,
343 .dma_tx_param = "ssp1_tx",
344 .dma_rx_param = "ssp1_rx",
345 .num_chipselect = 2,
346 }, {
347 .bus_id = 2,
348 .enable_dma = 1,
349 .dma_filter = pl08x_filter_id,
350 .dma_tx_param = "ssp2_tx",
351 .dma_rx_param = "ssp2_rx",
352 .num_chipselect = 2,
353 }
354};
355
356static struct amba_pl011_data spear320_uart_data[] = {
357 {
358 .dma_filter = pl08x_filter_id,
359 .dma_tx_param = "uart1_tx",
360 .dma_rx_param = "uart1_rx",
361 }, {
362 .dma_filter = pl08x_filter_id,
363 .dma_tx_param = "uart2_tx",
364 .dma_rx_param = "uart2_rx",
365 },
366};
513 367
514/* spear320 routines */ 368/* Add SPEAr310 auxdata to pass platform data */
515void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 369static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
516 u8 pmx_dev_count) 370 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
371 &pl022_plat_data),
372 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
373 &pl080_plat_data),
374 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
375 &spear320_ssp_data[0]),
376 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
377 &spear320_ssp_data[1]),
378 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
379 &spear320_uart_data[0]),
380 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
381 &spear320_uart_data[1]),
382 {}
383};
384
385static void __init spear320_dt_init(void)
517{ 386{
518 void __iomem *base; 387 void __iomem *base;
519 int ret = 0; 388 int ret;
389
390 pl080_plat_data.slave_channels = spear320_dma_info;
391 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
520 392
521 /* call spear3xx family common init function */ 393 of_platform_populate(NULL, of_default_bus_match_table,
522 spear3xx_init(); 394 spear320_auxdata_lookup, NULL);
523 395
524 /* shared irq registration */ 396 /* shared irq registration */
525 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); 397 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -528,29 +400,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
528 shirq_ras1.regs.base = base; 400 shirq_ras1.regs.base = base;
529 ret = spear_shirq_register(&shirq_ras1); 401 ret = spear_shirq_register(&shirq_ras1);
530 if (ret) 402 if (ret)
531 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 403 pr_err("Error registering Shared IRQ 1\n");
532 404
533 /* shirq 3 */ 405 /* shirq 3 */
534 shirq_ras3.regs.base = base; 406 shirq_ras3.regs.base = base;
535 ret = spear_shirq_register(&shirq_ras3); 407 ret = spear_shirq_register(&shirq_ras3);
536 if (ret) 408 if (ret)
537 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 409 pr_err("Error registering Shared IRQ 3\n");
538 410
539 /* shirq 4 */ 411 /* shirq 4 */
540 shirq_intrcomm_ras.regs.base = base; 412 shirq_intrcomm_ras.regs.base = base;
541 ret = spear_shirq_register(&shirq_intrcomm_ras); 413 ret = spear_shirq_register(&shirq_intrcomm_ras);
542 if (ret) 414 if (ret)
543 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 415 pr_err("Error registering Shared IRQ 4\n");
544 } 416 }
417}
545 418
546 /* pmx initialization */ 419static const char * const spear320_dt_board_compat[] = {
547 pmx_driver.base = base; 420 "st,spear320",
548 pmx_driver.mode = pmx_mode; 421 "st,spear320-evb",
549 pmx_driver.devs = pmx_devs; 422 NULL,
550 pmx_driver.devs_count = pmx_dev_count; 423};
551 424
552 ret = pmx_register(&pmx_driver); 425static void __init spear320_map_io(void)
553 if (ret) 426{
554 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 427 spear3xx_map_io();
555 ret); 428 spear320_clk_init();
556} 429}
430
431DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
432 .map_io = spear320_map_io,
433 .init_irq = spear3xx_dt_init_irq,
434 .handle_irq = vic_handle_irq,
435 .timer = &spear3xx_timer,
436 .init_machine = spear320_dt_init,
437 .restart = spear_restart,
438 .dt_compat = spear320_dt_board_compat,
439MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear320_evb.c
3 *
4 * SPEAr320 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_mii,
26 &spear3xx_pmx_uart0,
27
28 /* spear320 specific devices */
29 &spear320_pmx_fsmc,
30 &spear320_pmx_sdhci,
31 &spear320_pmx_i2s,
32 &spear320_pmx_uart1,
33 &spear320_pmx_uart2,
34 &spear320_pmx_can,
35 &spear320_pmx_pwm0,
36 &spear320_pmx_pwm1,
37 &spear320_pmx_pwm2,
38 &spear320_pmx_mii1,
39};
40
41static struct amba_device *amba_devs[] __initdata = {
42 /* spear3xx specific devices */
43 &spear3xx_gpio_device,
44 &spear3xx_uart_device,
45
46 /* spear320 specific devices */
47};
48
49static struct platform_device *plat_devs[] __initdata = {
50 /* spear3xx specific devices */
51
52 /* spear320 specific devices */
53};
54
55static void __init spear320_evb_init(void)
56{
57 unsigned int i;
58
59 /* call spear320 machine init function */
60 spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
61 ARRAY_SIZE(pmx_devs));
62
63 /* Add Platform Devices */
64 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
65
66 /* Add Amba Devices */
67 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
68 amba_device_register(amba_devs[i], &iomem_resource);
69}
70
71MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
72 .atag_offset = 0x100,
73 .map_io = spear3xx_map_io,
74 .init_irq = spear3xx_init_irq,
75 .handle_irq = vic_handle_irq,
76 .timer = &spear3xx_timer,
77 .init_machine = spear320_evb_init,
78 .restart = spear_restart,
79MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 2625ab9a6c8b..71927c717807 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
3 * 3 *
4 * SPEAr3XX machines common source file 4 * SPEAr3XX machines common source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr3xx: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/of_irq.h>
17#include <linux/io.h> 19#include <linux/io.h>
20#include <asm/hardware/pl080.h>
18#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
19#include <asm/irq.h> 22#include <plat/pl080.h>
20#include <asm/mach/arch.h>
21#include <mach/generic.h> 23#include <mach/generic.h>
22#include <mach/hardware.h> 24#include <mach/hardware.h>
23 25
24/* Add spear3xx machines common devices here */ 26/* ssp device registration */
25/* gpio device registration */ 27struct pl022_ssp_controller pl022_plat_data = {
26static struct pl061_platform_data gpio_plat_data = { 28 .bus_id = 0,
27 .gpio_base = 0, 29 .enable_dma = 1,
28 .irq_base = SPEAR3XX_GPIO_INT_BASE, 30 .dma_filter = pl08x_filter_id,
31 .dma_tx_param = "ssp0_tx",
32 .dma_rx_param = "ssp0_rx",
33 /*
34 * This is number of spi devices that can be connected to spi. There are
35 * two type of chipselects on which slave devices can work. One is chip
36 * select provided by spi masters other is controlled through external
37 * gpio's. We can't use chipselect provided from spi master (because as
38 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39 * this number now depends on number of gpios available for spi. each
40 * slave on each master requires a separate gpio pin.
41 */
42 .num_chipselect = 2,
43};
44
45/* dmac device registration */
46struct pl08x_platform_data pl080_plat_data = {
47 .memcpy_channel = {
48 .bus_id = "memcpy",
49 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
50 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
51 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
52 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
53 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
54 PL080_CONTROL_PROT_SYS),
55 },
56 .lli_buses = PL08X_AHB1,
57 .mem_buses = PL08X_AHB1,
58 .get_signal = pl080_get_signal,
59 .put_signal = pl080_put_signal,
29}; 60};
30 61
31AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, 62/*
32 {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); 63 * Following will create 16MB static virtual/physical mappings
33 64 * PHYSICAL VIRTUAL
34/* uart device registration */ 65 * 0xD0000000 0xFD000000
35AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, 66 * 0xFC000000 0xFC000000
36 {SPEAR3XX_IRQ_UART}, NULL); 67 */
37
38/* Do spear3xx familiy common initialization part here */
39void __init spear3xx_init(void)
40{
41 /* nothing to do for now */
42}
43
44/* This will initialize vic */
45void __init spear3xx_init_irq(void)
46{
47 vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
48}
49
50/* Following will create static virtual/physical mappings */
51struct map_desc spear3xx_io_desc[] __initdata = { 68struct map_desc spear3xx_io_desc[] __initdata = {
52 { 69 {
53 .virtual = VA_SPEAR3XX_ICM1_UART_BASE, 70 .virtual = VA_SPEAR3XX_ICM1_2_BASE,
54 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), 71 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
55 .length = SZ_4K, 72 .length = SZ_16M,
56 .type = MT_DEVICE
57 }, {
58 .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
59 .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
60 .length = SZ_4K,
61 .type = MT_DEVICE 73 .type = MT_DEVICE
62 }, { 74 }, {
63 .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, 75 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
64 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), 76 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
65 .length = SZ_4K, 77 .length = SZ_16M,
66 .type = MT_DEVICE
67 }, {
68 .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
69 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
70 .length = SZ_4K,
71 .type = MT_DEVICE 78 .type = MT_DEVICE
72 }, 79 },
73}; 80};
@@ -76,436 +83,8 @@ struct map_desc spear3xx_io_desc[] __initdata = {
76void __init spear3xx_map_io(void) 83void __init spear3xx_map_io(void)
77{ 84{
78 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 85 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
79
80 /* This will initialize clock framework */
81 spear3xx_clk_init();
82} 86}
83 87
84/* pad multiplexing support */
85/* devices */
86static struct pmx_dev_mode pmx_firda_modes[] = {
87 {
88 .ids = 0xffffffff,
89 .mask = PMX_FIRDA_MASK,
90 },
91};
92
93struct pmx_dev spear3xx_pmx_firda = {
94 .name = "firda",
95 .modes = pmx_firda_modes,
96 .mode_count = ARRAY_SIZE(pmx_firda_modes),
97 .enb_on_reset = 0,
98};
99
100static struct pmx_dev_mode pmx_i2c_modes[] = {
101 {
102 .ids = 0xffffffff,
103 .mask = PMX_I2C_MASK,
104 },
105};
106
107struct pmx_dev spear3xx_pmx_i2c = {
108 .name = "i2c",
109 .modes = pmx_i2c_modes,
110 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
111 .enb_on_reset = 0,
112};
113
114static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
115 {
116 .ids = 0xffffffff,
117 .mask = PMX_SSP_CS_MASK,
118 },
119};
120
121struct pmx_dev spear3xx_pmx_ssp_cs = {
122 .name = "ssp_chip_selects",
123 .modes = pmx_ssp_cs_modes,
124 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
125 .enb_on_reset = 0,
126};
127
128static struct pmx_dev_mode pmx_ssp_modes[] = {
129 {
130 .ids = 0xffffffff,
131 .mask = PMX_SSP_MASK,
132 },
133};
134
135struct pmx_dev spear3xx_pmx_ssp = {
136 .name = "ssp",
137 .modes = pmx_ssp_modes,
138 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
139 .enb_on_reset = 0,
140};
141
142static struct pmx_dev_mode pmx_mii_modes[] = {
143 {
144 .ids = 0xffffffff,
145 .mask = PMX_MII_MASK,
146 },
147};
148
149struct pmx_dev spear3xx_pmx_mii = {
150 .name = "mii",
151 .modes = pmx_mii_modes,
152 .mode_count = ARRAY_SIZE(pmx_mii_modes),
153 .enb_on_reset = 0,
154};
155
156static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
157 {
158 .ids = 0xffffffff,
159 .mask = PMX_GPIO_PIN0_MASK,
160 },
161};
162
163struct pmx_dev spear3xx_pmx_gpio_pin0 = {
164 .name = "gpio_pin0",
165 .modes = pmx_gpio_pin0_modes,
166 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
167 .enb_on_reset = 0,
168};
169
170static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
171 {
172 .ids = 0xffffffff,
173 .mask = PMX_GPIO_PIN1_MASK,
174 },
175};
176
177struct pmx_dev spear3xx_pmx_gpio_pin1 = {
178 .name = "gpio_pin1",
179 .modes = pmx_gpio_pin1_modes,
180 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
181 .enb_on_reset = 0,
182};
183
184static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
185 {
186 .ids = 0xffffffff,
187 .mask = PMX_GPIO_PIN2_MASK,
188 },
189};
190
191struct pmx_dev spear3xx_pmx_gpio_pin2 = {
192 .name = "gpio_pin2",
193 .modes = pmx_gpio_pin2_modes,
194 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
195 .enb_on_reset = 0,
196};
197
198static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
199 {
200 .ids = 0xffffffff,
201 .mask = PMX_GPIO_PIN3_MASK,
202 },
203};
204
205struct pmx_dev spear3xx_pmx_gpio_pin3 = {
206 .name = "gpio_pin3",
207 .modes = pmx_gpio_pin3_modes,
208 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
209 .enb_on_reset = 0,
210};
211
212static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
213 {
214 .ids = 0xffffffff,
215 .mask = PMX_GPIO_PIN4_MASK,
216 },
217};
218
219struct pmx_dev spear3xx_pmx_gpio_pin4 = {
220 .name = "gpio_pin4",
221 .modes = pmx_gpio_pin4_modes,
222 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
223 .enb_on_reset = 0,
224};
225
226static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
227 {
228 .ids = 0xffffffff,
229 .mask = PMX_GPIO_PIN5_MASK,
230 },
231};
232
233struct pmx_dev spear3xx_pmx_gpio_pin5 = {
234 .name = "gpio_pin5",
235 .modes = pmx_gpio_pin5_modes,
236 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
237 .enb_on_reset = 0,
238};
239
240static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
241 {
242 .ids = 0xffffffff,
243 .mask = PMX_UART0_MODEM_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_uart0_modem = {
248 .name = "uart0_modem",
249 .modes = pmx_uart0_modem_modes,
250 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
251 .enb_on_reset = 0,
252};
253
254static struct pmx_dev_mode pmx_uart0_modes[] = {
255 {
256 .ids = 0xffffffff,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_uart0 = {
262 .name = "uart0",
263 .modes = pmx_uart0_modes,
264 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
265 .enb_on_reset = 0,
266};
267
268static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
269 {
270 .ids = 0xffffffff,
271 .mask = PMX_TIMER_3_4_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_timer_3_4 = {
276 .name = "timer_3_4",
277 .modes = pmx_timer_3_4_modes,
278 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
279 .enb_on_reset = 0,
280};
281
282static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
283 {
284 .ids = 0xffffffff,
285 .mask = PMX_TIMER_1_2_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_timer_1_2 = {
290 .name = "timer_1_2",
291 .modes = pmx_timer_1_2_modes,
292 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
293 .enb_on_reset = 0,
294};
295
296#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
297/* plgpios devices */
298static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
299 {
300 .ids = 0x00,
301 .mask = PMX_FIRDA_MASK,
302 },
303};
304
305struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
306 .name = "plgpio 0 and 1",
307 .modes = pmx_plgpio_0_1_modes,
308 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
313 {
314 .ids = 0x00,
315 .mask = PMX_UART0_MASK,
316 },
317};
318
319struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
320 .name = "plgpio 2 and 3",
321 .modes = pmx_plgpio_2_3_modes,
322 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
327 {
328 .ids = 0x00,
329 .mask = PMX_I2C_MASK,
330 },
331};
332
333struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
334 .name = "plgpio 4 and 5",
335 .modes = pmx_plgpio_4_5_modes,
336 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
341 {
342 .ids = 0x00,
343 .mask = PMX_SSP_MASK,
344 },
345};
346
347struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
348 .name = "plgpio 6 to 9",
349 .modes = pmx_plgpio_6_9_modes,
350 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
355 {
356 .ids = 0x00,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
362 .name = "plgpio 10 to 27",
363 .modes = pmx_plgpio_10_27_modes,
364 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
369 {
370 .ids = 0x00,
371 .mask = PMX_GPIO_PIN0_MASK,
372 },
373};
374
375struct pmx_dev spear3xx_pmx_plgpio_28 = {
376 .name = "plgpio 28",
377 .modes = pmx_plgpio_28_modes,
378 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
379 .enb_on_reset = 1,
380};
381
382static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
383 {
384 .ids = 0x00,
385 .mask = PMX_GPIO_PIN1_MASK,
386 },
387};
388
389struct pmx_dev spear3xx_pmx_plgpio_29 = {
390 .name = "plgpio 29",
391 .modes = pmx_plgpio_29_modes,
392 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
393 .enb_on_reset = 1,
394};
395
396static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
397 {
398 .ids = 0x00,
399 .mask = PMX_GPIO_PIN2_MASK,
400 },
401};
402
403struct pmx_dev spear3xx_pmx_plgpio_30 = {
404 .name = "plgpio 30",
405 .modes = pmx_plgpio_30_modes,
406 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
407 .enb_on_reset = 1,
408};
409
410static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
411 {
412 .ids = 0x00,
413 .mask = PMX_GPIO_PIN3_MASK,
414 },
415};
416
417struct pmx_dev spear3xx_pmx_plgpio_31 = {
418 .name = "plgpio 31",
419 .modes = pmx_plgpio_31_modes,
420 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
421 .enb_on_reset = 1,
422};
423
424static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
425 {
426 .ids = 0x00,
427 .mask = PMX_GPIO_PIN4_MASK,
428 },
429};
430
431struct pmx_dev spear3xx_pmx_plgpio_32 = {
432 .name = "plgpio 32",
433 .modes = pmx_plgpio_32_modes,
434 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
435 .enb_on_reset = 1,
436};
437
438static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
439 {
440 .ids = 0x00,
441 .mask = PMX_GPIO_PIN5_MASK,
442 },
443};
444
445struct pmx_dev spear3xx_pmx_plgpio_33 = {
446 .name = "plgpio 33",
447 .modes = pmx_plgpio_33_modes,
448 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
449 .enb_on_reset = 1,
450};
451
452static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
453 {
454 .ids = 0x00,
455 .mask = PMX_SSP_CS_MASK,
456 },
457};
458
459struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
460 .name = "plgpio 34 to 36",
461 .modes = pmx_plgpio_34_36_modes,
462 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
463 .enb_on_reset = 1,
464};
465
466static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
467 {
468 .ids = 0x00,
469 .mask = PMX_UART0_MODEM_MASK,
470 },
471};
472
473struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
474 .name = "plgpio 37 to 42",
475 .modes = pmx_plgpio_37_42_modes,
476 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
477 .enb_on_reset = 1,
478};
479
480static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
481 {
482 .ids = 0x00,
483 .mask = PMX_TIMER_1_2_MASK,
484 },
485};
486
487struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
488 .name = "plgpio 43, 44, 47 and 48",
489 .modes = pmx_plgpio_43_44_47_48_modes,
490 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
491 .enb_on_reset = 1,
492};
493
494static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
495 {
496 .ids = 0x00,
497 .mask = PMX_TIMER_3_4_MASK,
498 },
499};
500
501struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
502 .name = "plgpio 45, 46, 49 and 50",
503 .modes = pmx_plgpio_45_46_49_50_modes,
504 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
505 .enb_on_reset = 1,
506};
507#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
508
509static void __init spear3xx_timer_init(void) 88static void __init spear3xx_timer_init(void)
510{ 89{
511 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
@@ -538,3 +117,13 @@ static void __init spear3xx_timer_init(void)
538struct sys_timer spear3xx_timer = { 117struct sys_timer spear3xx_timer = {
539 .init = spear3xx_timer_init, 118 .init = spear3xx_timer_init,
540}; 119};
120
121static const struct of_device_id vic_of_match[] __initconst = {
122 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
123 { /* Sentinel */ }
124};
125
126void __init spear3xx_dt_init_irq(void)
127{
128 of_irq_init(vic_of_match);
129}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 23:13:41 -0500