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authorArnd Bergmann <arnd@arndb.de>2012-04-11 13:30:11 -0400
committerArnd Bergmann <arnd@arndb.de>2012-04-22 16:44:04 -0400
commit5019f0b1345b8f6a8e8a0c7c2f89d4a31819a317 (patch)
tree0856f4be673561e8131ef9df7b6904e9bca7a135 /arch/arm/mach-spear3xx
parentf3215b427bec2add8b5c776e8f50c3ba35b0e8f1 (diff)
ARM: spear: remove most mach/*.h header contents
The register and irq definitions in mach/*.h for spear3xx and spear6xx are now mostly obsolete, after the platforms have been converted to device tree based probing and the data is now part of the device tree files. The misc_regs.h contents are moved into clock.c because that is the only user, aside from the DMA_CHN_CFG that should eventually get handled differently. Some of the contents of mach/spear.h still remain, because they are used to set up the static map table, timer, uart and auxdata tables, but almost everything got removed. We might remove everything but the map table as the DT conversion completes, but that is not a priority. I've also made sure to make both copies of spear.h more or less identical so we can eventually combine them. The spear3?0.h files were only used by the spear3?0.c files, so I merged the contents in there and removed the bits that were unused. This is something that should still be looked at. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@st.com>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r--arch/arm/mach-spear3xx/clock.c98
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h11
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h21
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h130
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h38
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/spear300.c41
-rw-r--r--arch/arm/mach-spear3xx/spear310.c62
-rw-r--r--arch/arm/mach-spear3xx/spear320.c62
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c4
13 files changed, 268 insertions, 522 deletions
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index eeafe38eab25..cd6c11099083 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -19,6 +19,104 @@
19#include <asm/mach-types.h> 19#include <asm/mach-types.h>
20#include <plat/clock.h> 20#include <plat/clock.h>
21#include <mach/misc_regs.h> 21#include <mach/misc_regs.h>
22#include <mach/spear.h>
23
24#define PLL1_CTR (MISC_BASE + 0x008)
25#define PLL1_FRQ (MISC_BASE + 0x00C)
26#define PLL1_MOD (MISC_BASE + 0x010)
27#define PLL2_CTR (MISC_BASE + 0x014)
28/* PLL_CTR register masks */
29#define PLL_ENABLE 2
30#define PLL_MODE_SHIFT 4
31#define PLL_MODE_MASK 0x3
32#define PLL_MODE_NORMAL 0
33#define PLL_MODE_FRACTION 1
34#define PLL_MODE_DITH_DSB 2
35#define PLL_MODE_DITH_SSB 3
36
37#define PLL2_FRQ (MISC_BASE + 0x018)
38/* PLL FRQ register masks */
39#define PLL_DIV_N_SHIFT 0
40#define PLL_DIV_N_MASK 0xFF
41#define PLL_DIV_P_SHIFT 8
42#define PLL_DIV_P_MASK 0x7
43#define PLL_NORM_FDBK_M_SHIFT 24
44#define PLL_NORM_FDBK_M_MASK 0xFF
45#define PLL_DITH_FDBK_M_SHIFT 16
46#define PLL_DITH_FDBK_M_MASK 0xFFFF
47
48#define PLL2_MOD (MISC_BASE + 0x01C)
49#define PLL_CLK_CFG (MISC_BASE + 0x020)
50#define CORE_CLK_CFG (MISC_BASE + 0x024)
51/* CORE CLK CFG register masks */
52#define PLL_HCLK_RATIO_SHIFT 10
53#define PLL_HCLK_RATIO_MASK 0x3
54#define HCLK_PCLK_RATIO_SHIFT 8
55#define HCLK_PCLK_RATIO_MASK 0x3
56
57#define PERIP_CLK_CFG (MISC_BASE + 0x028)
58/* PERIP_CLK_CFG register masks */
59#define UART_CLK_SHIFT 4
60#define UART_CLK_MASK 0x1
61#define FIRDA_CLK_SHIFT 5
62#define FIRDA_CLK_MASK 0x3
63#define GPT0_CLK_SHIFT 8
64#define GPT1_CLK_SHIFT 11
65#define GPT2_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART_CLK_ENB 3
73#define SSP_CLK_ENB 5
74#define I2C_CLK_ENB 7
75#define JPEG_CLK_ENB 8
76#define FIRDA_CLK_ENB 10
77#define GPT1_CLK_ENB 11
78#define GPT2_CLK_ENB 12
79#define ADC_CLK_ENB 15
80#define RTC_CLK_ENB 17
81#define GPIO_CLK_ENB 18
82#define DMA_CLK_ENB 19
83#define SMI_CLK_ENB 21
84#define GMAC_CLK_ENB 23
85#define USBD_CLK_ENB 24
86#define USBH_CLK_ENB 25
87#define C3_CLK_ENB 31
88
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90
91#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
92#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
93#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
94/* gpt synthesizer register masks */
95#define GPT_MSCALE_SHIFT 0
96#define GPT_MSCALE_MASK 0xFFF
97#define GPT_NSCALE_SHIFT 12
98#define GPT_NSCALE_MASK 0xF
99
100#define AMEM_CLK_CFG (MISC_BASE + 0x050)
101#define EXPI_CLK_CFG (MISC_BASE + 0x054)
102#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
103#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
104#define UART_CLK_SYNT (MISC_BASE + 0x064)
105#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
106#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
107#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
108#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
109#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
110/* aux clk synthesiser register masks for irda to ras4 */
111#define AUX_SYNT_ENB 31
112#define AUX_EQ_SEL_SHIFT 30
113#define AUX_EQ_SEL_MASK 1
114#define AUX_EQ1_SEL 0
115#define AUX_EQ2_SEL 1
116#define AUX_XSCALE_SHIFT 16
117#define AUX_XSCALE_MASK 0xFFF
118#define AUX_YSCALE_SHIFT 0
119#define AUX_YSCALE_MASK 0xFFF
22 120
23/* root clks */ 121/* root clks */
24/* 32 KHz oscillator clock */ 122/* 32 KHz oscillator clock */
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index a7569584cbe8..e4f4d721cda2 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -22,22 +22,13 @@
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <plat/padmux.h> 23#include <plat/padmux.h>
24 24
25/* spear3xx declarations */
26/*
27 * Each GPT has 2 timer channels
28 * Following GPT channels will be used as clock source and clockevent
29 */
30#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
31#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
32#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
33
34/* Add spear3xx family device structure declarations here */ 25/* Add spear3xx family device structure declarations here */
35extern struct sys_timer spear3xx_timer; 26extern struct sys_timer spear3xx_timer;
36extern struct pl022_ssp_controller pl022_plat_data; 27extern struct pl022_ssp_controller pl022_plat_data;
37extern struct pl08x_platform_data pl080_plat_data; 28extern struct pl08x_platform_data pl080_plat_data;
38 29
39/* Add spear3xx family function declarations here */ 30/* Add spear3xx family function declarations here */
40void __init spear_setup_timer(void); 31void __init spear_setup_timer(resource_size_t base, int irq);
41void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
42void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
43 34
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index defa374f5bee..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,20 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear3xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..319620a1afb4 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,15 @@
14#ifndef __MACH_IRQS_H 14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* FIXME: probe all these from DT */
18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define SPEAR3XX_IRQ_CPU_GPT1_1 2 19#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define SPEAR3XX_IRQ_JPEG 16
35#define SPEAR3XX_IRQ_IRDA 17
36#define SPEAR3XX_IRQ_ADC 18
37#define SPEAR3XX_IRQ_UART 19
38#define SPEAR3XX_IRQ_SSP 20
39#define SPEAR3XX_IRQ_I2C 21
40#define SPEAR3XX_IRQ_MAC_1 22
41#define SPEAR3XX_IRQ_MAC_2 23
42#define SPEAR3XX_IRQ_USB_DEV 24
43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define SPEAR3XX_IRQ_GEN_RAS_1 28 20#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define SPEAR3XX_IRQ_GEN_RAS_2 29 21#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define SPEAR3XX_IRQ_GEN_RAS_3 30 22#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define SPEAR3XX_IRQ_VIC_END 32 23#define SPEAR3XX_IRQ_VIC_END 32
52
53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END 24#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 25
55/* SPEAr300 Virtual irq definitions */ 26#define NR_IRQS 160
56/* IRQs sharing IRQ_GEN_RAS_1 */
57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
69
70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
72
73/* SPEAr310 Virtual irq definitions */
74/* IRQs sharing IRQ_GEN_RAS_1 */
75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
83
84/* IRQs sharing IRQ_GEN_RAS_2 */
85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
90
91/* IRQs sharing IRQ_GEN_RAS_3 */
92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
94
95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
99
100/* SPEAr320 Virtual irq definitions */
101/* IRQs sharing IRQ_GEN_RAS_1 */
102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
105
106/* IRQs sharing IRQ_GEN_RAS_2 */
107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
108
109/* IRQs sharing IRQ_GEN_RAS_3 */
110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
113
114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
138#endif
139
140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
149#endif
150
151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
152#define NR_IRQS SPEAR3XX_VIRQ_END
153 27
154#endif /* __MACH_IRQS_H */ 28#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..e0ab72e61507 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,7 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h>
18
19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 17#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 11
64#define GPT2_CLK_SHIFT 12
65#define GPT_CLK_MASK 0x1
66#define AUX_CLK_PLL3_VAL 0
67#define AUX_CLK_PLL1_VAL 1
68
69#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5
73#define I2C_CLK_ENB 7
74#define JPEG_CLK_ENB 8
75#define FIRDA_CLK_ENB 10
76#define GPT1_CLK_ENB 11
77#define GPT2_CLK_ENB 12
78#define ADC_CLK_ENB 15
79#define RTC_CLK_ENB 17
80#define GPIO_CLK_ENB 18
81#define DMA_CLK_ENB 19
82#define SMI_CLK_ENB 21
83#define GMAC_CLK_ENB 23
84#define USBD_CLK_ENB 24
85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31
87
88#define SOC_CORE_ID (MISC_BASE + 0x030)
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90#define PERIP1_SOF_RST (MISC_BASE + 0x038)
91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8
93
94#define SOC_USER_ID (MISC_BASE + 0x03C)
95#define RAS_SOF_RST (MISC_BASE + 0x040)
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
127#define ICM2_ARB_CFG (MISC_BASE + 0x080)
128#define ICM3_ARB_CFG (MISC_BASE + 0x084)
129#define ICM4_ARB_CFG (MISC_BASE + 0x088)
130#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
131#define ICM6_ARB_CFG (MISC_BASE + 0x090)
132#define ICM7_ARB_CFG (MISC_BASE + 0x094)
133#define ICM8_ARB_CFG (MISC_BASE + 0x098)
134#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
135#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 18#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
136#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
137#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
138#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
139#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
140#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
141#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
142#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
143#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
144#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
145#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
146#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
147#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
148#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
149#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
150#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
151#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
152#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
153#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
154#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
155#define BIST4_CFG_CTR (MISC_BASE + 0x100)
156#define BIST5_CFG_CTR (MISC_BASE + 0x104)
157#define BIST1_STS_RES (MISC_BASE + 0x108)
158#define BIST2_STS_RES (MISC_BASE + 0x10C)
159#define BIST3_STS_RES (MISC_BASE + 0x110)
160#define BIST4_STS_RES (MISC_BASE + 0x114)
161#define BIST5_STS_RES (MISC_BASE + 0x118)
162#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
163 19
164#endif /* __MACH_MISC_REGS_H */ 20#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 8e3900aa0d45..6d4dadc67633 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,61 +15,27 @@
15#define __MACH_SPEAR3XX_H 15#define __MACH_SPEAR3XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear300.h>
19#include <mach/spear310.h>
20#include <mach/spear320.h>
21
22#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
23
24#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
25 18
26/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 20#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) 21#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 22#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) 23#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 24#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
34#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
35#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
36#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
37
38/* ICM2 - Application Subsystem */
39#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
40#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
41
42/* ICM4 - High Speed Connection */
43#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
44#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
45#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
46#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
47#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
48#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
49#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
50#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
51#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
52 25
53/* ML1 - Multi Layer CPU Subsystem */ 26/* ML1 - Multi Layer CPU Subsystem */
54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) 29#define SPEAR3XX_CPU_TMR_BASE UL(0xF0000000)
57 30
58/* ICM3 - Basic Subsystem */ 31/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 32#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 33#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 34#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
65#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 35#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) 36#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 37#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) 38#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
73 39
74/* Debug uart for linux, will be used for debug and uncompress messages */ 40/* Debug uart for linux, will be used for debug and uncompress messages */
75#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE 41#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
22/* Interrupt registers offsets and masks */
23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000)
39#define SPEAR300_NAND_0_BASE UL(0x80000000)
40#define SPEAR300_NAND_1_BASE UL(0x84000000)
41#define SPEAR300_NAND_2_BASE UL(0x88000000)
42#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43#define SPEAR300_NOR_0_BASE UL(0x90000000)
44#define SPEAR300_NOR_1_BASE UL(0x91000000)
45#define SPEAR300_NOR_2_BASE UL(0x92000000)
46#define SPEAR300_NOR_3_BASE UL(0x93000000)
47#define SPEAR300_FSMC_BASE UL(0x94000000)
48#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
52#endif /* __MACH_SPEAR300_H */
53
54#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE UL(0x40000000)
20#define SPEAR310_FSMC_BASE UL(0x44000000)
21#define SPEAR310_UART1_BASE UL(0xB2000000)
22#define SPEAR310_UART2_BASE UL(0xB2080000)
23#define SPEAR310_UART3_BASE UL(0xB2100000)
24#define SPEAR310_UART4_BASE UL(0xB2180000)
25#define SPEAR310_UART5_BASE UL(0xB2200000)
26#define SPEAR310_HDLC_BASE UL(0xB2800000)
27#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
56#endif /* __MACH_SPEAR310_H */
57
58#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
38/* Interrupt registers offsets and masks */
39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
65#endif /* __MACH_SPEAR320_H */
66
67#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f46fc2692ab6..febcdd8d4e92 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -19,7 +19,46 @@
19#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
20#include <plat/shirq.h> 20#include <plat/shirq.h>
21#include <mach/generic.h> 21#include <mach/generic.h>
22#include <mach/hardware.h> 22#include <mach/spear.h>
23
24/* Base address of various IPs */
25#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
27/* Interrupt registers offsets and masks */
28#define SPEAR300_INT_ENB_MASK_REG 0x54
29#define SPEAR300_INT_STS_MASK_REG 0x58
30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39
40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41
42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43
44
45/* SPEAr300 Virtual irq definitions */
46/* IRQs sharing IRQ_GEN_RAS_1 */
47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56
57/* IRQs sharing IRQ_GEN_RAS_3 */
58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
23 62
24/* pad multiplexing support */ 63/* pad multiplexing support */
25/* muxing registers */ 64/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 063e7da0438a..b26e41566b50 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -20,7 +20,67 @@
20#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
21#include <plat/shirq.h> 21#include <plat/shirq.h>
22#include <mach/generic.h> 22#include <mach/generic.h>
23#include <mach/hardware.h> 23#include <mach/spear.h>
24
25#define SPEAR310_UART1_BASE UL(0xB2000000)
26#define SPEAR310_UART2_BASE UL(0xB2080000)
27#define SPEAR310_UART3_BASE UL(0xB2100000)
28#define SPEAR310_UART4_BASE UL(0xB2180000)
29#define SPEAR310_UART5_BASE UL(0xB2200000)
30#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR310_INT_STS_MASK_REG 0x04
34#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42#define SPEAR310_UART1_IRQ_MASK (1 << 8)
43#define SPEAR310_UART2_IRQ_MASK (1 << 9)
44#define SPEAR310_UART3_IRQ_MASK (1 << 10)
45#define SPEAR310_UART4_IRQ_MASK (1 << 11)
46#define SPEAR310_UART5_IRQ_MASK (1 << 12)
47#define SPEAR310_EMI_IRQ_MASK (1 << 13)
48#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
51
52#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
56
57/* SPEAr310 Virtual irq definitions */
58/* IRQs sharing IRQ_GEN_RAS_1 */
59#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
67
68/* IRQs sharing IRQ_GEN_RAS_2 */
69#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
74
75/* IRQs sharing IRQ_GEN_RAS_3 */
76#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
78
79/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83
24 84
25/* pad multiplexing support */ 85/* pad multiplexing support */
26/* muxing registers */ 86/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 1e74031e1213..2f5979b0c169 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -21,7 +21,67 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <plat/shirq.h> 22#include <plat/shirq.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/spear.h>
25
26#define SPEAR320_UART1_BASE UL(0xA3000000)
27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR320_INT_STS_MASK_REG 0x04
34#define SPEAR320_INT_CLR_MASK_REG 0x04
35#define SPEAR320_INT_ENB_MASK_REG 0x08
36#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
37#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
38#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
39#define SPEAR320_EMI_IRQ_MASK (1 << 7)
40#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
41#define SPEAR320_SPP_IRQ_MASK (1 << 9)
42#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
43#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
44#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
45#define SPEAR320_UART1_IRQ_MASK (1 << 13)
46#define SPEAR320_UART2_IRQ_MASK (1 << 14)
47#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
48#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
49#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
50#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
51#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
52#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
53#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
54
55#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
56#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
57#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
58
59/* SPEAr320 Virtual irq definitions */
60/* IRQs sharing IRQ_GEN_RAS_1 */
61#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
62#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
63#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
64
65/* IRQs sharing IRQ_GEN_RAS_2 */
66#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
67
68/* IRQs sharing IRQ_GEN_RAS_3 */
69#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
70#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
71#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
72
73/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
74#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
75#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
76#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
77#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
78#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
79#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
80#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
81#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
82#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
25 85
26/* pad multiplexing support */ 86/* pad multiplexing support */
27/* muxing registers */ 87/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 17d4ac9a95e1..bbb11efa6056 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -21,7 +21,7 @@
21#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
22#include <plat/pl080.h> 22#include <plat/pl080.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/spear.h>
25 25
26/* pad multiplexing support */ 26/* pad multiplexing support */
27/* devices */ 27/* devices */
@@ -534,7 +534,7 @@ static void __init spear3xx_timer_init(void)
534 clk_put(gpt_clk); 534 clk_put(gpt_clk);
535 clk_put(pclk); 535 clk_put(pclk);
536 536
537 spear_setup_timer(); 537 spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1);
538} 538}
539 539
540struct sys_timer spear3xx_timer = { 540struct sys_timer spear3xx_timer = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 03:30:16 -0500