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authorArnd Bergmann <arnd@arndb.de>2012-05-14 11:31:45 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 11:31:45 -0400
commit66a2886d867343eff6bf2646bea2c923d0cbf620 (patch)
treead44dcca4fa410ab2c16b4964f6c19571421b4df /arch/arm/mach-spear3xx
parentd2819f80d465672b09c2f4cb52303b7f951c4d0f (diff)
parentf613e220aebfafb653f7ce264950c15c99e27f2a (diff)
Merge branch 'spear/dt' into spear/clock
Conflicts: arch/arm/mach-spear3xx/clock.c arch/arm/mach-spear3xx/include/mach/generic.h arch/arm/mach-spear3xx/include/mach/misc_regs.h arch/arm/mach-spear3xx/spear320.c arch/arm/mach-spear6xx/clock.c arch/arm/mach-spear6xx/include/mach/misc_regs.h Resolve even more merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h11
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h21
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h131
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h37
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/spear300.c42
-rw-r--r--arch/arm/mach-spear3xx/spear310.c63
-rw-r--r--arch/arm/mach-spear3xx/spear320.c71
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c4
12 files changed, 178 insertions, 383 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index c10eac6c10cb..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -21,22 +21,13 @@
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23 23
24/* spear3xx declarations */
25/*
26 * Each GPT has 2 timer channels
27 * Following GPT channels will be used as clock source and clockevent
28 */
29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32
33/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
34extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
35extern struct pl022_ssp_controller pl022_plat_data; 26extern struct pl022_ssp_controller pl022_plat_data;
36extern struct pl08x_platform_data pl080_plat_data; 27extern struct pl08x_platform_data pl080_plat_data;
37 28
38/* Add spear3xx family function declarations here */ 29/* Add spear3xx family function declarations here */
39void __init spear_setup_timer(void); 30void __init spear_setup_of_timer(void);
40void __init spear3xx_clk_init(void); 31void __init spear3xx_clk_init(void);
41void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
42void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index defa374f5bee..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,20 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear3xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..51bd62a0254c 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,14 @@
14#ifndef __MACH_IRQS_H 14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* FIXME: probe all these from DT */
18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define SPEAR3XX_IRQ_JPEG 16
35#define SPEAR3XX_IRQ_IRDA 17
36#define SPEAR3XX_IRQ_ADC 18
37#define SPEAR3XX_IRQ_UART 19
38#define SPEAR3XX_IRQ_SSP 20
39#define SPEAR3XX_IRQ_I2C 21
40#define SPEAR3XX_IRQ_MAC_1 22
41#define SPEAR3XX_IRQ_MAC_2 23
42#define SPEAR3XX_IRQ_USB_DEV 24
43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define SPEAR3XX_IRQ_GEN_RAS_1 28 19#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define SPEAR3XX_IRQ_GEN_RAS_2 29 20#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define SPEAR3XX_IRQ_GEN_RAS_3 30 21#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define SPEAR3XX_IRQ_VIC_END 32 22#define SPEAR3XX_IRQ_VIC_END 32
52
53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END 23#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 24
55/* SPEAr300 Virtual irq definitions */ 25#define NR_IRQS 160
56/* IRQs sharing IRQ_GEN_RAS_1 */
57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
69
70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
72
73/* SPEAr310 Virtual irq definitions */
74/* IRQs sharing IRQ_GEN_RAS_1 */
75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
83
84/* IRQs sharing IRQ_GEN_RAS_2 */
85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
90
91/* IRQs sharing IRQ_GEN_RAS_3 */
92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
94
95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
99
100/* SPEAr320 Virtual irq definitions */
101/* IRQs sharing IRQ_GEN_RAS_1 */
102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
105
106/* IRQs sharing IRQ_GEN_RAS_2 */
107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
108
109/* IRQs sharing IRQ_GEN_RAS_3 */
110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
113
114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
138#endif
139
140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
149#endif
150
151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
152#define NR_IRQS SPEAR3XX_VIRQ_END
153 26
154#endif /* __MACH_IRQS_H */ 27#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 50cfe0d1a7c4..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,9 +14,9 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h>
18#include <mach/spear.h> 17#include <mach/spear.h>
19 18
20#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
21 21
22#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index e7bc8bab83fe..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,61 +15,26 @@
15#define __MACH_SPEAR3XX_H 15#define __MACH_SPEAR3XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear300.h>
19#include <mach/spear310.h>
20#include <mach/spear320.h>
21
22#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
23
24#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
25 18
26/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 20#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) 21#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 22#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) 23#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 24#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
34#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
35#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
36#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
37
38/* ICM2 - Application Subsystem */
39#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
40#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
41
42/* ICM4 - High Speed Connection */
43#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
44#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
45#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
46#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
47#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
48#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
49#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
50#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
51#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
52 25
53/* ML1 - Multi Layer CPU Subsystem */ 26/* ML1 - Multi Layer CPU Subsystem */
54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
57 29
58/* ICM3 - Basic Subsystem */ 30/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 31#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 32#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 33#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
65#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 34#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) 35#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 36#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) 37#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
73 38
74/* Debug uart for linux, will be used for debug and uncompress messages */ 39/* Debug uart for linux, will be used for debug and uncompress messages */
75#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE 40#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
22/* Interrupt registers offsets and masks */
23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000)
39#define SPEAR300_NAND_0_BASE UL(0x80000000)
40#define SPEAR300_NAND_1_BASE UL(0x84000000)
41#define SPEAR300_NAND_2_BASE UL(0x88000000)
42#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43#define SPEAR300_NOR_0_BASE UL(0x90000000)
44#define SPEAR300_NOR_1_BASE UL(0x91000000)
45#define SPEAR300_NOR_2_BASE UL(0x92000000)
46#define SPEAR300_NOR_3_BASE UL(0x93000000)
47#define SPEAR300_FSMC_BASE UL(0x94000000)
48#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
52#endif /* __MACH_SPEAR300_H */
53
54#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE UL(0x40000000)
20#define SPEAR310_FSMC_BASE UL(0x44000000)
21#define SPEAR310_UART1_BASE UL(0xB2000000)
22#define SPEAR310_UART2_BASE UL(0xB2080000)
23#define SPEAR310_UART3_BASE UL(0xB2100000)
24#define SPEAR310_UART4_BASE UL(0xB2180000)
25#define SPEAR310_UART5_BASE UL(0xB2200000)
26#define SPEAR310_HDLC_BASE UL(0xB2800000)
27#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
56#endif /* __MACH_SPEAR310_H */
57
58#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
38/* Interrupt registers offsets and masks */
39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
65#endif /* __MACH_SPEAR320_H */
66
67#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2db0bd14e481..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -19,7 +19,46 @@
19#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
20#include <plat/shirq.h> 20#include <plat/shirq.h>
21#include <mach/generic.h> 21#include <mach/generic.h>
22#include <mach/hardware.h> 22#include <mach/spear.h>
23
24/* Base address of various IPs */
25#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
27/* Interrupt registers offsets and masks */
28#define SPEAR300_INT_ENB_MASK_REG 0x54
29#define SPEAR300_INT_STS_MASK_REG 0x58
30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39
40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41
42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43
44
45/* SPEAr300 Virtual irq definitions */
46/* IRQs sharing IRQ_GEN_RAS_1 */
47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56
57/* IRQs sharing IRQ_GEN_RAS_3 */
58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
23 62
24/* spear3xx shared irq */ 63/* spear3xx shared irq */
25static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
@@ -298,7 +337,6 @@ static const char * const spear300_dt_board_compat[] = {
298static void __init spear300_map_io(void) 337static void __init spear300_map_io(void)
299{ 338{
300 spear3xx_map_io(); 339 spear3xx_map_io();
301 spear300_clk_init();
302} 340}
303 341
304DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") 342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index aec07c951205..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -20,7 +20,67 @@
20#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
21#include <plat/shirq.h> 21#include <plat/shirq.h>
22#include <mach/generic.h> 22#include <mach/generic.h>
23#include <mach/hardware.h> 23#include <mach/spear.h>
24
25#define SPEAR310_UART1_BASE UL(0xB2000000)
26#define SPEAR310_UART2_BASE UL(0xB2080000)
27#define SPEAR310_UART3_BASE UL(0xB2100000)
28#define SPEAR310_UART4_BASE UL(0xB2180000)
29#define SPEAR310_UART5_BASE UL(0xB2200000)
30#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR310_INT_STS_MASK_REG 0x04
34#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42#define SPEAR310_UART1_IRQ_MASK (1 << 8)
43#define SPEAR310_UART2_IRQ_MASK (1 << 9)
44#define SPEAR310_UART3_IRQ_MASK (1 << 10)
45#define SPEAR310_UART4_IRQ_MASK (1 << 11)
46#define SPEAR310_UART5_IRQ_MASK (1 << 12)
47#define SPEAR310_EMI_IRQ_MASK (1 << 13)
48#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
51
52#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
56
57/* SPEAr310 Virtual irq definitions */
58/* IRQs sharing IRQ_GEN_RAS_1 */
59#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
67
68/* IRQs sharing IRQ_GEN_RAS_2 */
69#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
74
75/* IRQs sharing IRQ_GEN_RAS_3 */
76#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
78
79/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83
24 84
25/* spear3xx shared irq */ 85/* spear3xx shared irq */
26static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
@@ -418,7 +478,6 @@ static const char * const spear310_dt_board_compat[] = {
418static void __init spear310_map_io(void) 478static void __init spear310_map_io(void)
419{ 479{
420 spear3xx_map_io(); 480 spear3xx_map_io();
421 spear310_clk_init();
422} 481}
423 482
424DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") 483DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fb28c189688e..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -21,9 +21,67 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <plat/shirq.h> 22#include <plat/shirq.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h>
25#include <mach/spear.h> 24#include <mach/spear.h>
26 25
26#define SPEAR320_UART1_BASE UL(0xA3000000)
27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR320_INT_STS_MASK_REG 0x04
33#define SPEAR320_INT_CLR_MASK_REG 0x04
34#define SPEAR320_INT_ENB_MASK_REG 0x08
35#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38#define SPEAR320_EMI_IRQ_MASK (1 << 7)
39#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40#define SPEAR320_SPP_IRQ_MASK (1 << 9)
41#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44#define SPEAR320_UART1_IRQ_MASK (1 << 13)
45#define SPEAR320_UART2_IRQ_MASK (1 << 14)
46#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
53
54#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
57
58/* SPEAr320 Virtual irq definitions */
59/* IRQs sharing IRQ_GEN_RAS_1 */
60#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
63
64/* IRQs sharing IRQ_GEN_RAS_2 */
65#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
71
72/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
84
27/* spear3xx shared irq */ 85/* spear3xx shared irq */
28static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
29 { 87 {
@@ -422,10 +480,19 @@ static const char * const spear320_dt_board_compat[] = {
422 NULL, 480 NULL,
423}; 481};
424 482
483struct map_desc spear320_io_desc[] __initdata = {
484 {
485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
486 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
487 .length = SZ_16M,
488 .type = MT_DEVICE
489 },
490};
491
425static void __init spear320_map_io(void) 492static void __init spear320_map_io(void)
426{ 493{
494 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
427 spear3xx_map_io(); 495 spear3xx_map_io();
428 spear320_clk_init();
429} 496}
430 497
431DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") 498DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 71927c717807..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -21,7 +21,7 @@
21#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
22#include <plat/pl080.h> 22#include <plat/pl080.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/spear.h>
25 25
26/* ssp device registration */ 26/* ssp device registration */
27struct pl022_ssp_controller pl022_plat_data = { 27struct pl022_ssp_controller pl022_plat_data = {
@@ -111,7 +111,7 @@ static void __init spear3xx_timer_init(void)
111 clk_put(gpt_clk); 111 clk_put(gpt_clk);
112 clk_put(pclk); 112 clk_put(pclk);
113 113
114 spear_setup_timer(); 114 spear_setup_of_timer();
115} 115}
116 116
117struct sys_timer spear3xx_timer = { 117struct sys_timer spear3xx_timer = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 03:26:23 -0500