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authorviresh kumar <viresh.kumar@st.com>2010-04-01 07:30:19 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-04-14 06:26:22 -0400
commita7e9c45219b2d40a80fbd1b7337cbecab85be2bd (patch)
tree88521a51ddfa7485254b4adcd50d8109c4e4e947 /arch/arm/mach-spear3xx
parent39710479303fd3affb3e204e9a7a75cc676977b5 (diff)
ARM: 6010/1: ST SPEAr: Added basic header files for SPEAr3xx machine family
Reviewed-by: Linus Walleij <linux.walleij@stericsson.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r--arch/arm/mach-spear3xx/include/mach/debug-macro.S14
-rw-r--r--arch/arm/mach-spear3xx/include/mach/entry-macro.S46
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/gpio.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h20
-rw-r--r--arch/arm/mach-spear3xx/include/mach/io.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h65
-rw-r--r--arch/arm/mach-spear3xx/include/mach/memory.h19
-rwxr-xr-xarch/arm/mach-spear3xx/include/mach/misc_regs.h163
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h67
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h46
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h70
-rw-r--r--arch/arm/mach-spear3xx/include/mach/system.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/timex.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/uncompress.h19
-rw-r--r--arch/arm/mach-spear3xx/include/mach/vmalloc.h19
17 files changed, 826 insertions, 0 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..590519f10d6e
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/debug-macro.S
3 *
4 * Debugging macro include header spear3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..947625d6b48d
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <mach/hardware.h>
15#include <mach/spear.h>
16#include <asm/hardware/vic.h>
17
18 .macro disable_fiq
19 .endm
20
21 .macro get_irqnr_preamble, base, tmp
22 .endm
23
24 .macro arch_ret_to_user, tmp1, tmp2
25 .endm
26
27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
28 ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE
29 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
30 teq \irqstat, #0
31 beq 1001f @ this will set/reset
32 @ zero register
33 /*
34 * Following code will find bit position of least significang
35 * bit set in irqstat, using following equation
36 * least significant bit set in n = (n & ~(n-1))
37 */
38 sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
39 mvn \tmp, \tmp @ tmp = ~tmp
40 and \irqstat, \irqstat, \tmp @ irqstat &= tmp
41 /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
42 clz \tmp, \irqstat @ tmp = leading zeros
43 rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1
44
451001: /* EQ will be set if no irqs pending */
46 .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
new file mode 100644
index 000000000000..aeea8453a9e2
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -0,0 +1,58 @@
1/*
2 * arch/arm/mach-spear3xx/generic.h
3 *
4 * SPEAr3XX machine family generic header file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H
16
17#include <asm/mach/time.h>
18#include <asm/mach/map.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/amba/bus.h>
22
23/*
24 * Each GPT has 2 timer channels
25 * Following GPT channels will be used as clock source and clockevent
26 */
27#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
28#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
29#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
30
31/* Add spear3xx family device structure declarations here */
32extern struct amba_device gpio_device;
33extern struct amba_device uart_device;
34extern struct sys_timer spear_sys_timer;
35
36/* Add spear3xx family function declarations here */
37void __init spear3xx_map_io(void);
38void __init spear3xx_init_irq(void);
39void __init spear3xx_init(void);
40void __init spear300_init(void);
41void __init spear310_init(void);
42void __init spear320_init(void);
43void __init clk_init(void);
44
45/* Add spear300 machine device structure declarations here */
46#ifdef CONFIG_MACH_SPEAR300
47extern struct amba_device gpio1_device;
48#endif /* CONFIG_MACH_SPEAR300 */
49
50/* Add spear310 machine device structure declarations here */
51#ifdef CONFIG_MACH_SPEAR310
52#endif /* CONFIG_MACH_SPEAR310 */
53
54/* Add spear320 machine device structure declarations here */
55#ifdef CONFIG_MACH_SPEAR320
56#endif /* CONFIG_MACH_SPEAR320 */
57
58#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
new file mode 100644
index 000000000000..451b2081bfc9
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/gpio.h
3 *
4 * GPIO macros for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_GPIO_H
15#define __MACH_GPIO_H
16
17#include <plat/gpio.h>
18
19#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
new file mode 100644
index 000000000000..4a86e6a3c444
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17/* Vitual to physical translation of statically mapped space */
18#define IO_ADDRESS(x) (x | 0xF0000000)
19
20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h
new file mode 100644
index 000000000000..30cff8a1f6b5
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/io.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/io.h
3 *
4 * IO definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_IO_H
15#define __MACH_IO_H
16
17#include <plat/io.h>
18
19#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
new file mode 100644
index 000000000000..fe980e07b6ab
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -0,0 +1,65 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/irqs.h
3 *
4 * IRQ helper macros for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H
16
17/* IRQ definitions */
18#define IRQ_HW_ACCEL_MOD_0 0
19#define IRQ_INTRCOMM_RAS_ARM 1
20#define IRQ_CPU_GPT1_1 2
21#define IRQ_CPU_GPT1_2 3
22#define IRQ_BASIC_GPT1_1 4
23#define IRQ_BASIC_GPT1_2 5
24#define IRQ_BASIC_GPT2_1 6
25#define IRQ_BASIC_GPT2_2 7
26#define IRQ_BASIC_DMA 8
27#define IRQ_BASIC_SMI 9
28#define IRQ_BASIC_RTC 10
29#define IRQ_BASIC_GPIO 11
30#define IRQ_BASIC_WDT 12
31#define IRQ_DDR_CONTROLLER 13
32#define IRQ_SYS_ERROR 14
33#define IRQ_WAKEUP_RCV 15
34#define IRQ_JPEG 16
35#define IRQ_IRDA 17
36#define IRQ_ADC 18
37#define IRQ_UART 19
38#define IRQ_SSP 20
39#define IRQ_I2C 21
40#define IRQ_MAC_1 22
41#define IRQ_MAC_2 23
42#define IRQ_USB_DEV 24
43#define IRQ_USB_H_OHCI_0 25
44#define IRQ_USB_H_EHCI_0 26
45#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0
46#define IRQ_USB_H_OHCI_1 27
47#define IRQ_GEN_RAS_1 28
48#define IRQ_GEN_RAS_2 29
49#define IRQ_GEN_RAS_3 30
50#define IRQ_HW_ACCEL_MOD_1 31
51#define IRQ_VIC_END 32
52
53#define SPEAR_GPIO_INT_BASE IRQ_VIC_END
54
55#ifdef CONFIG_MACH_SPEAR300
56#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
57#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
58#else
59#define SPEAR_GPIO_INT_END (SPEAR_GPIO_INT_BASE + 8)
60#endif
61
62#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
63#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
64
65#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h
new file mode 100644
index 000000000000..51735221ea19
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/memory.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/memory.h
3 *
4 * Memory map for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_MEMORY_H
15#define __MACH_MEMORY_H
16
17#include <plat/memory.h>
18
19#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
new file mode 100755
index 000000000000..38d767a1aba0
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -0,0 +1,163 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/misc_regs.h
3 *
4 * Miscellaneous registers definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H
16
17#include <mach/spear.h>
18
19#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE
20
21#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000))
22#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004))
23#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008))
24#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C))
25#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010))
26#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014))
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018))
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C))
48#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020))
49#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024))
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028))
57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 11
64#define GPT2_CLK_SHIFT 12
65#define GPT_CLK_MASK 0x1
66#define AUX_CLK_PLL3_MASK 0
67#define AUX_CLK_PLL1_MASK 1
68
69#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C))
70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5
73#define I2C_CLK_ENB 7
74#define JPEG_CLK_ENB 8
75#define FIRDA_CLK_ENB 10
76#define GPT1_CLK_ENB 11
77#define GPT2_CLK_ENB 12
78#define ADC_CLK_ENB 15
79#define RTC_CLK_ENB 17
80#define GPIO_CLK_ENB 18
81#define DMA_CLK_ENB 19
82#define SMI_CLK_ENB 21
83#define GMAC_CLK_ENB 23
84#define USBD_CLK_ENB 24
85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31
87
88#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030))
89#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034))
90#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038))
91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8
93
94#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C))
95#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040))
96#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044))
97#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048))
98#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C))
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050))
106#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054))
107#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C))
108#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060))
109#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064))
110#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068))
111#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C))
112#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070))
113#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074))
114#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078))
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_EQ_SEL_SHIFT 30
117#define AUX_EQ_SEL_MASK 1
118#define AUX_EQ1_SEL 0
119#define AUX_EQ2_SEL 1
120#define AUX_XSCALE_SHIFT 16
121#define AUX_XSCALE_MASK 0xFFF
122#define AUX_YSCALE_SHIFT 0
123#define AUX_YSCALE_MASK 0xFFF
124
125#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C))
126#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080))
127#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084))
128#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088))
129#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C))
130#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090))
131#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094))
132#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098))
133#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C))
134#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0))
135#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4))
136#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8))
137#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC))
138#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0))
139#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4))
140#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8))
141#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC))
142#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0))
143#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4))
144#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8))
145#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC))
146#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0))
147#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4))
148#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8))
149#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC))
150#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0))
151#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4))
152#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8))
153#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC))
154#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100))
155#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104))
156#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108))
157#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C))
158#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110))
159#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114))
160#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118))
161#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C))
162
163#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
new file mode 100644
index 000000000000..dcca8568a486
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -0,0 +1,144 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear.h
3 *
4 * SPEAr3xx Machine family specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SPEAR3XX_H
15#define __MACH_SPEAR3XX_H
16
17#include <mach/hardware.h>
18#include <mach/spear300.h>
19#include <mach/spear310.h>
20#include <mach/spear320.h>
21
22#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
23#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000
24
25#define SPEAR3XX_ICM9_BASE 0xC0000000
26#define SPEAR3XX_ICM9_SIZE 0x10000000
27
28/* ICM1 - Low speed connection */
29#define SPEAR3XX_ICM1_2_BASE 0xD0000000
30#define SPEAR3XX_ICM1_2_SIZE 0x10000000
31
32#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
33#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
34#define SPEAR3XX_ICM1_UART_SIZE 0x00080000
35
36#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
37#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000
38
39#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
40#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000
41
42#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
43#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000
44
45#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
46#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000
47
48#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
49#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000
50
51#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
52#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000
53
54/* ICM2 - Application Subsystem */
55#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
56#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000
57
58#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
59#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000
60
61/* ICM4 - High Speed Connection */
62#define SPEAR3XX_ICM4_BASE 0xE0000000
63#define SPEAR3XX_ICM4_SIZE 0x08000000
64
65#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
66#define SPEAR3XX_ICM4_MII_SIZE 0x00800000
67
68#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
69#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000
70
71#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
72#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000
73
74#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
75#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000
76
77#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
78#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000
79
80#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
81#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000
82
83#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
84#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000
85
86#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
87#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000
88
89/* ML1 - Multi Layer CPU Subsystem */
90#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
91#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000
92
93#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
94#define SPEAR3XX_ML1_TMR_SIZE 0x00100000
95
96#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
97#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
98#define SPEAR3XX_ML1_VIC_SIZE 0x00100000
99
100/* ICM3 - Basic Subsystem */
101#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
102#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000
103
104#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
105#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000
106
107#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
108#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000
109
110#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
111#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
112
113#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
114#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000
115
116#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
117#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000
118
119#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
120#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000
121
122#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
123#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000
124
125#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
126#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
127#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000
128
129#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
130#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
131#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000
132
133#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
134#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000
135
136/* Debug uart for linux, will be used for debug and uncompress messages */
137#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
138#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE
139
140/* Sysctl base for spear platform */
141#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
142#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
143
144#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
new file mode 100644
index 000000000000..40c16f385cfa
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -0,0 +1,67 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE 0x50000000
21#define SPEAR300_TELECOM_SIZE 0x10000000
22
23#define SPEAR300_CLCD_BASE 0x60000000
24#define SPEAR300_CLCD_SIZE 0x10000000
25
26#define SPEAR300_SDIO_BASE 0x70000000
27#define SPEAR300_SDIO_SIZE 0x10000000
28
29#define SPEAR300_NAND_0_BASE 0x80000000
30#define SPEAR300_NAND_0_SIZE 0x04000000
31
32#define SPEAR300_NAND_1_BASE 0x84000000
33#define SPEAR300_NAND_1_SIZE 0x04000000
34
35#define SPEAR300_NAND_2_BASE 0x88000000
36#define SPEAR300_NAND_2_SIZE 0x04000000
37
38#define SPEAR300_NAND_3_BASE 0x8c000000
39#define SPEAR300_NAND_3_SIZE 0x04000000
40
41#define SPEAR300_NOR_0_BASE 0x90000000
42#define SPEAR300_NOR_0_SIZE 0x01000000
43
44#define SPEAR300_NOR_1_BASE 0x91000000
45#define SPEAR300_NOR_1_SIZE 0x01000000
46
47#define SPEAR300_NOR_2_BASE 0x92000000
48#define SPEAR300_NOR_2_SIZE 0x01000000
49
50#define SPEAR300_NOR_3_BASE 0x93000000
51#define SPEAR300_NOR_3_SIZE 0x01000000
52
53#define SPEAR300_FSMC_BASE 0x94000000
54#define SPEAR300_FSMC_SIZE 0x05000000
55
56#define SPEAR300_SOC_CONFIG_BASE 0x99000000
57#define SPEAR300_SOC_CONFIG_SIZE 0x00000008
58
59#define SPEAR300_KEYBOARD_BASE 0xA0000000
60#define SPEAR300_KEYBOARD_SIZE 0x09000000
61
62#define SPEAR300_GPIO_BASE 0xA9000000
63#define SPEAR300_GPIO_SIZE 0x07000000
64
65#endif /* __MACH_SPEAR300_H */
66
67#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
new file mode 100644
index 000000000000..d4f58d6469d9
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE 0x40000000
20#define SPEAR310_NAND_SIZE 0x04000000
21
22#define SPEAR310_FSMC_BASE 0x44000000
23#define SPEAR310_FSMC_SIZE 0x01000000
24
25#define SPEAR310_UART1_BASE 0xB2000000
26#define SPEAR310_UART2_BASE 0xB2080000
27#define SPEAR310_UART3_BASE 0xB2100000
28#define SPEAR310_UART4_BASE 0xB2180000
29#define SPEAR310_UART5_BASE 0xB2200000
30#define SPEAR310_UART_SIZE 0x00080000
31
32#define SPEAR310_HDLC_BASE 0xB2800000
33#define SPEAR310_HDLC_SIZE 0x00800000
34
35#define SPEAR310_RS485_0_BASE 0xB3000000
36#define SPEAR310_RS485_0_SIZE 0x00800000
37
38#define SPEAR310_RS485_1_BASE 0xB3800000
39#define SPEAR310_RS485_1_SIZE 0x00800000
40
41#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
42#define SPEAR310_SOC_CONFIG_SIZE 0x00000070
43
44#endif /* __MACH_SPEAR310_H */
45
46#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
new file mode 100644
index 000000000000..e8ad2ed82e24
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -0,0 +1,70 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE 0x40000000
20#define SPEAR320_EMI_CTRL_SIZE 0x08000000
21
22#define SPEAR320_FSMC_BASE 0x4C000000
23#define SPEAR320_FSMC_SIZE 0x01000000
24
25#define SPEAR320_I2S_BASE 0x60000000
26#define SPEAR320_I2S_SIZE 0x10000000
27
28#define SPEAR320_SDIO_BASE 0x70000000
29#define SPEAR320_SDIO_SIZE 0x10000000
30
31#define SPEAR320_CLCD_BASE 0x90000000
32#define SPEAR320_CLCD_SIZE 0x10000000
33
34#define SPEAR320_PAR_PORT_BASE 0xA0000000
35#define SPEAR320_PAR_PORT_SIZE 0x01000000
36
37#define SPEAR320_CAN0_BASE 0xA1000000
38#define SPEAR320_CAN0_SIZE 0x01000000
39
40#define SPEAR320_CAN1_BASE 0xA2000000
41#define SPEAR320_CAN1_SIZE 0x01000000
42
43#define SPEAR320_UART1_BASE 0xA3000000
44#define SPEAR320_UART2_BASE 0xA4000000
45#define SPEAR320_UART_SIZE 0x01000000
46
47#define SPEAR320_SSP0_BASE 0xA5000000
48#define SPEAR320_SSP0_SIZE 0x01000000
49
50#define SPEAR320_SSP1_BASE 0xA6000000
51#define SPEAR320_SSP1_SIZE 0x01000000
52
53#define SPEAR320_I2C_BASE 0xA7000000
54#define SPEAR320_I2C_SIZE 0x01000000
55
56#define SPEAR320_PWM_BASE 0xA8000000
57#define SPEAR320_PWM_SIZE 0x01000000
58
59#define SPEAR320_SMII0_BASE 0xAA000000
60#define SPEAR320_SMII0_SIZE 0x01000000
61
62#define SPEAR320_SMII1_BASE 0xAB000000
63#define SPEAR320_SMII1_SIZE 0x01000000
64
65#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
66#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
67
68#endif /* __MACH_SPEAR320_H */
69
70#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
new file mode 100644
index 000000000000..92cee6335c90
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/system.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/system.h
3 *
4 * SPEAr3xx Machine family specific architecture functions
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SYSTEM_H
15#define __MACH_SYSTEM_H
16
17#include <plat/system.h>
18
19#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h
new file mode 100644
index 000000000000..a38cc9de876f
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/timex.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/timex.h
3 *
4 * SPEAr3XX machine family specific timex definitions
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_TIMEX_H
15#define __MACH_TIMEX_H
16
17#include <plat/timex.h>
18
19#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..53ba8bbc0dfa
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_UNCOMPRESS_H
15#define __MACH_UNCOMPRESS_H
16
17#include <plat/uncompress.h>
18
19#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..df977b3c9a63
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/vmalloc.h
3 *
4 * Defining Vmalloc area for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_VMALLOC_H
15#define __MACH_VMALLOC_H
16
17#include <plat/vmalloc.h>
18
19#endif /* __MACH_VMALLOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 20:40:20 -0400